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4.9.2 Controlling clock manager
The clock manager generates the down-count clock for each timer by dividing the OSC1 or OSC3 clock.
Table 4.9.2.1 lists the 15 count clocks that can be generated by the clock manager, and the clock to be used
for each timer can be selected using the count clock frequency select register PTPSx0–PTPSx3. At initial
reset, the PTPSx register is set to "0H" and the clock supply from the clock manager to the programmable
timer is disabled. Before the timer can be run, select a clock to enable the clock supply.
Stop the clock supply to the timers shown below by setting PTPSx to "0H" to reduce current consumption.
• Unused timer
• Timer used as an event counter that inputs an external clock
• Upper 8-bit timer (Timer 1/3/5/7) when the timer unit is used as a 16-bit × 1 channel configuration.
Table 4.9.2.1 Selecting count clock frequency
PTPSx3
PTPSx2
PTPSx1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
f
: OSC1 oscillation frequency. ( ) indicates the frequency when f
OSC1
f
: OSC3 oscillation frequency
OSC3
PTPSx0
Timer clock
1
1
f
OSC3
1
0
f
/ 2
OSC3
0
1
f
/ 4
OSC3
0
0
f
/ 8
OSC3
1
1
f
/ 16
OSC3
1
0
f
/ 32
OSC3
0
1
f
/ 64
OSC3
0
0
f
/ 256
OSC3
1
1
f
OSC1
1
0
f
/ 2
OSC1
0
1
f
/ 4
OSC1
0
0
f
/ 16
OSC1
1
1
f
/ 32
OSC1
1
0
f
/ 64
OSC1
0
1
f
/ 256 (128 Hz)
OSC1
0
0
OFF
SIC63616-(Rev. 1.0) NO. P100
(32 kHz)
(16 kHz)
(8 kHz)
(2 kHz)
(1 kHz)
(512 Hz)
= 32 kHz.
OSC1
3240-0412
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