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4.10 Serial Interface
4.10.1 Configuration of serial interface
The S1C63616 has a built-in 8-bit clock synchronous type serial interface.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via the
same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of seven
types of master mode (internal clock mode: when the S1C63616 is to be the master for serial input/output)
and a type of slave mode (external clock mode: when the S1C63616 is to be the slave for serial input/
output).
The configuration of the serial interface is shown in Figure 4.10.1.1.
SIN
(P22)
f
OSC1
Clock
f
OSC3
manager
Programmable
timer 1
SIFCKS0–SIFCKS2
SIF clock selection
Interrupt request
SCLK
(P20)
4.10.2 Serial interface terminals
The following shows the terminals used in the serial interface and their functions:
SCLK (P20)
Inputs or outputs the serial clock. By writing "1" to the ESIF register to enable the serial interface, the
P20 terminal is switched to the SCLK terminal. In master mode, the SCLK terminal is configured for
output and it outputs the synchronous clock generated in the IC during data transfer. In slave mode, the
SCLK terminal inputs the synchronous clock output by the external master device.
SIN (P22)
Inputs serial data. By writing "1" to the ESIF register to enable the serial interface, the P22 terminal is
switched to the SIN terminal.
SOUT (P21)
Outputs serial data. By default, the SOUT terminal is not enabled even if "1" is written to the ESIF regis-
ter. When using the SOUT output, write "1" to the ESOUT register.
If serial input only is required, the P21 terminal can be used as an I/O port terminal.
SRDY (P23)
In slave mode, this terminal outputs the SRDY signal to the master device to indicate that the serial
interface is ready to transfer. By default, the SRDY terminal is not enabled even if the serial interface is
set to slave mode. When using the SRDY output in slave mode, write "1" to the ENCS and ESREADY
registers.
SS (P23)
Inputs the SS (Slave Select) signal when the S1C63616 is used as an SPI slave device. When using the SS
input, write "1" to ENCS and write "0" to ESREADY.
8-bit shift register
SCPS0–SCPS1
Clock format selection
Clock
Interrupt control
control
Fig. 4.10.1.1 Configuration of serial interface
Data bus
Output
SD0–SD7
latch
SDP
Data I/O permutation
ESIF
SIF enable (P2)
SCTRG
SIF clock trigger
ENCS
ESREADY
SMOD
Transfer
mode control
SIC63616-(Rev. 1.0) NO. P121
SOUT
(P21)
ESOUT
SOUT enable
SIF enable (P23)
P23 function selection
Mode selection
SS
or
SRDY
(P23)
Serial interface
3240-0412
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