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16.3
Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to the addresses shown in
table 16.1 are directed to the on-chip RAM. In modes 1 to 5 (expanded modes), when the RAME
bit is cleared to 0, the off-chip address space is accessed. In mode 6, 7 (single-chip mode), when
the RAME bit is cleared to 0, the on-chip RAM is not accessed: read access always results in H'FF
data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
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