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34
The Processor and the Operating System
Indirect Addressing
Some instructions may also employ "indirect addressing". This is indicated by including the
optional indicator ;
I,
such as -
.... ) =_ ..
1,
= ...
=
'r
...... ::
..
:
..
There is only one level of indirect addreSSing provided with the processor. Of course, if further
levels are deSired, it is possible to implement them on your own. Some flagging scheme could
be adopted, for example. One approach could be to adopt the policy that the sign bit (bit 15) of
a word would indicate further indirection, with the remaining bits being the value. In such an
approach, a load accumulator instruction would become two instructions -
1SOURCE
i
nR
A,1
1SOUR(E
SAM *-1
Load/ Store Group
Use
curr~rt
contents
ct~
pointer
This group of instructions allows transfers of data to take place. With the instructions below you
can move information to and from the arithmetic accumulators (the A and B registers). You can
also transfer the contents of one contiguous set of words in memory to another contiguous set.
Instruction
LDF:i {location} [; I]
,
·r·
~-.
{I
. } [
~
]
L..U.b
ocatton
;
J..
:=:TF! {location}
L
I]
:=:TB {location} [; I]
{value}
><FF:
{value}
Description
Loads register A with the contents of the specified location.
Loads register B with the contents of the specified location.
Stores the contents of the A register into the specified loca-
tion.
Stores the contents of the B register into the specified loca-
tion.
Clears (zeroes out) the specified number of words, beginning
at the location specified by the A register. {value} must be an
integer between 1 and 16.
Transfers the specified number of words, from one location to
another. The starting address of the location being transfer-
red from must be stored in the A register. The starting ad-
dress of the location being transferred to must be stored in
the B register. {value} must be an integer between 1 and 16.
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