NEC V850E/IA1 mPD703116 User Manual page 148

32-bit single-chip microcontrollers

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Bit Position

Remark n = 0 to 3

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

This status bit indicates whether DMA transfer through DMA channel n has ended or not.

This bit is read-only. It is set to 1 when DMA transfer ends and cleared (to 0) when it is

0: DMA transfer had not ended.

1: DMA transfer had ended.

When this bit is set to 1 at terminal count output, the Enn bit is not cleared to 0 and the

DMA transfer enable state is retained. When the next DMA transfer request is the

DMARQn signal (internal signal) or an interrupt from the on-chip peripheral I/O (hardware

DMA), the DMA transfer request can be accepted even when the TCn bit is not read.

When the next DMA transfer request is the setting of the STGn bit to 1 (software DMA),

the DMA transfer request can be accepted by reading and clearing the TCn bit to 0.

When this bit is cleared to 0 at terminal count output, the Enn bit is cleared to 0 and the

DMA transfer disable state is entered. At the next DMA transfer request, the setting of the

Enn bit to 1 and the reading of the TCn bit are required.

When this bit is set to 1, DMA transfer is forcibly terminated.

If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA

transfer is started.

Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This

bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA transfer is

forcibly terminated by means of setting the INITn bit to 1 or by NMI input.

0: DMA transfer disabled

1: DMA transfer enabled

Do not clear the Enn bit to 0 to cancel DMA transfer during DMA transfer.

User's Manual U14492EJ3V0UD

Initial value