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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(b) Up/down counter mode (UDC mode)
In the UDC mode, TM1n functions as a 16-bit up/down counter, counting based on the TCUD1n and
TIUD1n input signals.
Two operation modes can be set with the MSEL bit of the TUMn register for this mode.
(i) UDC mode A (when CMD bit = 1, MSEL bit = 0)
TM1n can be cleared by setting the CLR1 and CLR0 bits of the TMC1n register.
(ii) UDC mode B (when CMD bit = 1, MSEL bit = 1)
TM1n is cleared upon match with CM1n0 during TM1n up count operation.
TM1n is cleared upon match with CM1n1 during TM1n down count operation.
When the TM1CEn bit of the TMC1n register is "1", TM1n counts up when the operation mode is the general-
purpose mode, and it counts up/down when the operation mode is the UDC mode.
The conditions for clearing the TM1n are classified as follows depending on the operation mode.
Operation Mode
TUMn Register
CMD
Bit
General-purpose
0
timer mode
UDC mode A
1
UDC mode B
1
Settings other than the above
Remarks 1. n = 0, 1
2. ×: Indicates that the set value of that bit is ignored.
Table 9-5. Timer 1 (TM1n) Clear Conditions
TMC1n Register
MSEL
ENMD
CLR1
Bit
Bit
Bit
×
0
0
×
1
×
0
0
×
0
×
1
×
1
×
×
1
User's Manual U14492EJ3V0UD
CLR0
Bit
×
Clearing not performed
×
Cleared upon match with CM1n0 set value
0
Cleared only by TCLR1n input
1
Cleared upon match with CM1n0 set value during up
count operation
0
Cleared by TCLR1n input or upon match with CM1n0 set
value during up count operation
1
Clearing not performed
×
Cleared upon match with CM1n0 set value during up
count operation or upon match with CM1n1 set value
during down count operation
Setting prohibited
TM1n Clear
303
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