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Chapter 17
Processing by master device
IICn
IICn
ACKDn
STDn
SPDn
WTIMn
H
ACKEn
H
MSTSn
STTn
SPTn
L
WRELn
L
INTIICn
TRCn
H
Transfer lines
SCL0n
SDA0n
Start condition
Processing by slave device
IICn
ACKDn
STDn
SPDn
WTIMn
H
ACKEn
H
MSTSn
L
STTn
L
SPTn
L
WRELn
INTIICn
TRCn
L
Receive
Figure 17-19
Note
520
←
address
Transmit
1
2
3
4
5
AD6 AD5 AD4 AD3 AD2 AD1 AD0
(When EXCn = 1)
Example of master to slave communication
(when 9-clock wait is selected for both master and slave) (1/3)
start condition ~ address
To cancel slave wait, write FFH to IICn or set WRELn.
User's Manual U18743EE1V2UM00
6
7
8
9
W
ACK
2
I
C Bus (IIC)
←
IICn
data
1
2
3
4
D7
D6
D5
D4
←
Note
IICn
FFH
Note
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