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CAN Controller (CAN)
18.12 Interrupt Function
Table 18-25
Interrupt status bit
No.
Name
Register
1
CINTS0
CnINTS
2
CINTS1
CnINTS
3
CINTS2
CnINTS
4
CINTS3
CnINTS
5
CINTS4
CnINTS
6
CINTS5
CnINTS
a)
The IE bit (message buffer interrupt enable bit) in the CnMCTRL register of the corresponding message buffer
has to be set to 1 for that message buffer to participate in the interrupt generation process
Supplements
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status
registers. Four separate interrupt request signals are generated from the six
interrupt sources. When an interrupt request signal that corresponds to two or
more interrupt sources is generated, the interrupt sources can be identified by
using an interrupt status register. After an interrupt source has occurred, the
corresponding interrupt status bit must be cleared to 0 by software.
List of CAN module interrupt sources
Interrupt enable bit
Name
Register
a
CIE0
CnIE
a
CIE1
CnIE
CIE2
CnIE
CIE3
CnIE
CIE4
CnIE
CIE5
CnIE
1.
This interrupt is generated when the transmission/reception error counter
is at the warning level, or in the error passive or bus-off state.
2.
This interrupt is generated when a stuff error, form error, ACK error, bit
error, or CRC error occurs.
3.
This interrupt is generated when the CAN module is woken up from the
CAN sleep mode because a falling edge is detected at the CAN reception
pin (CAN bus transition from recessive to dominant).
User's Manual U18743EE1V2UM00
Interrupt
request
Interrupt source description
signal
Message frame successfully transmitted from
INTCnTRX
message buffer m
Valid message frame reception in message
INTCnREC
buffer m
CAN module error state interrupt
INTCnERR
(Supplement 1)
CAN module protocol error interrupt
(Supplement 2)
CAN module arbitration loss interrupt
CAN module wakeup interrupt from CAN
INTCnWUP
sleep mode (Supplement 3)
Chapter 18
.
623
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