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2.2
Pin States
The operation states of pins in the various modes are described below.
Bus Control Pin
AD0 to AD15
Hi-Z
A0 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Notes 1. The bus control pin is shared with a port pin, so it is initialized to the input mode (port mode).
2. The state of the pins in the idle state inserted following the T3 state is shown.
Remark
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
Low-level output
H:
High-level output
−:
Input without sampling (not acknowledged)
CHAPTER 2 PIN FUNCTIONS
Table 2-2. Pin Operation States in Various Modes
Reset
HALT Mode During
DMA Transfer
Note 1
Operating
Preliminary User's Manual U16541EJ1V0UM
IDLE1, IDLE2
Idle State
Mode,
Software STOP
Mode
Hi-Z
Held
−
−
L
Operating
H
H
−
−
Note 2
Bus Hold
Hi-Z
−
Operating
Hi-Z
L
Operating
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