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22.3.4 Interrupt control register (xxICn)
The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions
for each maskable interrupt request.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 47H.
Caution Disable interrupts (DI) to read the xxIFn bit of the xxICn register. If the xxIFn bit is read while
interrupts are enabled (EI), the correct value may not be read when acknowledging an interrupt
and reading the bit conflict.
After reset:
xxICn
xxMKn
xxPRn2
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark
xx: Identification name of each peripheral unit (see Table 22-3 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 22-3 Interrupt Control Register (xxICn)).
The addresses and bits of the interrupt control registers are as follows.
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION
47H
R/W
Address:
FFFFF112H to FFFFF17CH
<7>
<6>
xxIFn
xxMKn
0
xxIFn
0
Interrupt request not issued
1
Interrupt request issued
0
Interrupt servicing enabled
1
Interrupt servicing disabled (pending)
xxPRn1
xxPRn0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Preliminary User's Manual U16541EJ1V0UM
0
0
xxPRn2
Note
Interrupt request flag
Interrupt mask flag
Interrupt priority specification bit
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
xxPRn1
xxPRn0
755
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