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24.4 IDLE2 Mode
24.4.1 Setting and operation status
The IDLE2 mode is set by setting the PSM1 and PSM0 bits of the PSMR register to 10 and setting the STP bit of
the PSC register to 1 in the normal operation mode.
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL operation, flash
memory, and other on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with the subclock or an external clock continue operating.
Table 24-7 shows the operation status in the IDLE2 mode.
The IDLE2 mode can reduce the current consumption more than the IDLE1 mode because it stops the operations
of the on-chip peripheral functions and flash memory. However, because the PLL operation and flash memory are
stopped, a setup time for the PLL operation and flash memory is required when IDLE2 mode is released.
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
set the IDLE2 mode.
24.4.2 Releasing IDLE2 mode
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES
signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operation status before the IDLE2
mode was set.
After the IDLE2 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is processed as follows.
Caution The interrupt request signal that is disabled by setting the NMI1M, NMI0M, and INTM bits of
the PSC register to 1 becomes invalid and IDLE2 mode is not released.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, only the IDLE2 mode is released, and that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and
that interrupt request signal is acknowledged.
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CHAPTER 24 STANDBY FUNCTION
Preliminary User's Manual U16541EJ1V0UM
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