IBM A2 Manuals

Manuals and User Guides for IBM A2. We have 1 IBM A2 manual available for free PDF download: User Manual

IBM A2 User Manual (864 pages)

Brand: IBM | Category: Computer Hardware | Size: 7.4 MB

Table of Contents
3
List of Figures

21
List of Tables

23
Revision Log

29
About this Book

31
- Who Should Use this Book
  31
- How to Use this Book
  31
- Notation
  32
- Related Publications
  33
List of Acronyms and Abbreviations

35
1 Overview

45
- A2 Core Key Design Fundamentals
  45
- A2 Core Features
  46
- The A2 Core as a Power ISA Implementation
  49
  - Embedded Hypervisor
    49
- A2 Core Organization
  49
  - Instruction Unit
    50
  - Figure 1-1. A2 Core Organization
    50
  - Execution Unit
    51
  - Instruction and Data Cache Controllers
    51
    
    Instruction Cache Controller
    51
    
    Data Cache Controller
    51
  - Memory Management Unit (MMU)
    52
  - Timers
    54
  - Debug Facilities
    54
    
    Debug Modes
    54
    
    Development Tool Support
    55
  - Floating-Point Unit Organization
    55
    
    Arithmetic and Load/Store Pipelines
    56
  - IEEE 754 and Architectural Compliance
    56
    
    Figure 1-2. A2 Processor Block Diagram
    56
    
    IEEE 754 Compliance
    57
  - Floating-Point Unit Implementation
    57
    
    Reciprocal Estimates
    57
    
    Denormalized B Operands
    57
    
    Non-IEEE Mode
    57
  - Floating-Point Unit Interfaces
    57
    
    A2 Processor Core Interface
    57
    
    Clock and Power Management Interface
    58
- Core Interfaces
  58
  - System Interface
    58
  - Auxiliary Execution Unit (AXU) Port
    59
  - JTAG Port
    59
2 CPU Programming Model

61
- Logical Partitioning
  61
  - Overview
    61
- Storage Addressing
  62
- Multithreading
  70
- Registers
  82
  - Figure 2-5. User Programming Model Registers
    83
  - Register Mapping
    84
  - Register Types
    84
    
    General Purpose Registers
    84
    
    Special Purpose Registers
    84
    
    Table 2-6. Register Mapping
    84
    
    Condition Register
    85
    
    Machine State Register
    85
- 32-Bit Mode
  85
  - 64-Bit Specific Instructions
    85
  - 32-Bit Instruction Selection
    85
- Instruction Categories
  86
- Table 2-7. Category Listing
  86
- Instruction Classes
  87
- Implemented Instruction Set Summary
  88
- Branch Processing
  99
  - Branch Addressing
    99
  - Branch Instruction BI Field
    99
  - Branch Instruction BO Field
    99
  - Branch Prediction
    100
    
    Branch Decoder
    100
    
    Table 2-34. BO Field Encodings
    100
    
    Table 2-35. 'At' Bit Encodings
    100
    
    Branch Direction Prediction
    101
    
    Branch Prioritization
    104
    
    Branch Target Prediction
    104
    
    Redirection
    105
  - Branch Control Registers
    105
    
    Link Register (LR)
    105
    
    Count Register (CTR)
    106
    
    Condition Register (CR)
    107
    
    Table 2-36. CR Updating Instructions
    108
- Integer Processing
  110
  - General Purpose Registers (Gprs)
    110
  - Integer Exception Register (XER)
    110
    
    Table 2-37. GPR Registers
    110
    
    Table 2-38. XER[SO,OV] Updating Instructions
    111
    
    Table 2-39. XER[CA] Updating Instructions
    111
    
    Carry (CA) Field
    112
    
    Overflow (OV) Field
    112
    
    Summary Overflow (SO) Field
    112
    
    Transfer Byte Count (TBC) Field
    113
- Processor Control
  113
  - Special Purpose Registers General (SPRG0-SPRG8)
    114
  - Table 2-40. SPRG0 Register
    114
  - Table 2-41. SPRG1 Register
    114
  - Table 2-42. SPRG2 Register
    115
  - Table 2-43. SPRG3 Register
    115
  - Table 2-44. SPRG4 Register
    115
  - Table 2-45. SPRG5 Register
    116
  - Table 2-46. SPRG6 Register
    116
  - Table 2-47. SPRG7 Register
    116
  - Table 2-48. SPRG8 Register
    117
  - Table 2-49. GSPRG0 Register
    117
  - Table 2-50. GSPRG1 Register
    117
  - Table 2-51. GSPRG2 Register
    118
  - Table 2-52. GSPRG3 Register
    118
  - External Process ID Load Context (EPLC) Register
    119
  - External Process ID Store Context (EPSC) Register
    119
- Privileged Modes
  120
  - Privileged Instructions
    121
    
    Cache Locking Instructions
    121
    
    Table 2-53. Privileged Instructions
    121
  - Privileged Sprs
    122
- Speculative Accesses
  122
- Synchronization
  122
  - Context Synchronization
    122
  - Execution Synchronization
    124
  - Storage Ordering and Synchronization
    124
- Software Transactional Memory Acceleration
  125
  - Summary
    125
  - Implementation
    125
    
    L1 D-Cache
    126
  - Watch Operation Ordering Requirements
    126
  - Impact on Existing Software
    126
3 FU Programming Model

127
4 Initialization

153
- Core Reset
  153
- A2 Core State after Reset
  154
- Table 4-1. Register Reset Values
  155
- Table 4-2. Shadow TLB Array Entry Initialization
  158
- Software Initiated Reset Requests
  160
  - Software Reset Requests
    160
    
    From Debug
    161
    
    From Watchdog Timer
    161
  - Reset Request Status
    161
    
    Debug Facility Reset Status
    162
    
    Timer Facility Reset Status
    162
- Initialization Software Requirements
  163
- Figure 4-1. Software-Initiated Reset Request Overview
  163
5 Instruction and Data Caches

169
- Data Cache Array Organization and Operation
  169
- Table 5-1. Data Cache Array Organization
  169
- Table 5-2. Cache Size and Parameters
  169
- Instruction Cache Array Organization and Operation
  170
- Cache Line Replacement Policy
  170
- Instruction Cache Controller
  170
- Data Cache Controller
  173
  - DCC Operations
    174
    
    Load and Store Alignment
    175
    
    Load Operations
    175
    
    Store Operations
    176
    
    Data Read and Instruction Fetch Interface Requests
    176
    
    Data Write Interface Requests
    176
    
    Storage Access Ordering
    177
  - Data Cache Coherency
    177
  - Data Cache Control
    177
    
    Data Cache Management Instruction Summary
    177
    
    Dcbt and Dcbtst Operation
    178
    
    Cache Locking Mechanisms
    179
    
    Data Cache Parity Operations
    183
    
    Simulating Data Cache Parity Errors for Software Testing
    183
    
    Data Cache Disable
    183
    
    Table 5-5. XUCR Bits
    183
6 Memory Management

185
7 CPU Interrupts and Exceptions

293
- Overview
  293
- Directed Interrupts
  293
- Interrupt Classes
  294
  - Asynchronous Interrupts
    294
  - Synchronous Interrupts
    294
    
    Synchronous, Precise Interrupts
    294
    
    Synchronous, Imprecise Interrupts
    295
  - Critical and Noncritical Interrupts
    296
  - Machine Check Interrupts
    296
- Interrupt Processing
  297
  - Partially Executed Instructions
    299
- Interrupt Processing Registers
  300
- Interrupt Definitions
  323
  - Table 7-3. Interrupt and Exception Types
    323
  - Critical Input Interrupt
    326
  - Machine Check Interrupt
    327
    
    Machine Check Status Register (MCSR)
    329
  - Data Storage Interrupt
    330
  - Instruction Storage Interrupt
    334
  - External Input Interrupt
    336
  - Alignment Interrupt
    337
  - Program Interrupt
    338
  - Floating-Point Unavailable Interrupt
    342
  - System Call Interrupt
    342
  - Auxiliary Processor Unavailable Interrupt
    343
  - Decrementer Interrupt
    343
  - Fixed-Interval Timer Interrupt
    344
  - Watchdog Timer Interrupt
    344
  - Data TLB Error Interrupt
    345
  - Instruction TLB Error Interrupt
    346
  - Debug Interrupt
    347
  - Vector Unavailable Interrupt
    347
  - Processor Doorbell Interrupt
    351
  - Guest Processor Doorbell Interrupt
    352
  - Processor Doorbell Critical Interrupt
    352
  - Guest Processor Doorbell Critical Interrupt
    353
  - Guest Processor Doorbell Machine Check Interrupt
    353
  - Embedded Hypervisor Privilege Interrupt
    354
  - Embedded Hypervisor System Call Interrupt
    354
  - LRAT Error Interrupt
    355
  - Performance Monitor Interrupt
    356
  - User Decrementer Interrupt
    356
- Processor Messages
  357
- Interrupt Ordering and Masking
  362
  - Interrupt Ordering Software Requirements
    363
  - Interrupt Order
    364
- Exception Priorities
  365
8 FU Interrupts and Exceptions

371
- Floating-Point Exceptions
  371
- Exceptions List
  372
- Table 8-1. Invalid Operation Exception Categories
  372
- Table 8-2. MSR[FE0, FE1] Modes
  374
- Floating-Point Interrupts
  375
  - Floating-Point Unavailable Interrupt
    375
  - Floating-Point Assist Interrupt
    375
- Floating-Point Exception Behavior
  375
  - Invalid Operation Exception
    375
    
    Action
    376
    
    Table 8-3. Invalid Operation Exceptions
    376
  - Zero Divide Exception
    377
    
    Action
    377
  - Overflow Exception
    378
    
    Action
    378
  - Underflow Exception
    379
    
    Action
    379
  - Inexact Exception
    380
    
    Action
    380
- Exception Priorities for Floating-Point Load and Store Instructions
  380
- Exception Priorities for Other Floating-Point Instructions
  381
- Qnan
  381
- Table 8-4. Qnan Result
  381
- Updating Fprs on Exceptions
  382
- Floating-Point Status and Control Register (FPSCR)
  382
- Table 8-5. FPSCR[FPRF] Result Flags
  382
- Table 8-6. Floating-Point Status and Control Register (FPSCR)
  383
- Updating the Condition Register
  385
  - Condition Register (CR)
    385
  - Updating CR Fields
    386
  - Generation of Qnan Results
    386
  - Table 8-7. Bit Encodings for a CR Field
    386
9 Timer Facilities

387
- Figure 9-1. Relationship of Timer Facilities to the Time Base
  387
  - Time Base
    388
    
    Table 9-1. Timebase Register (TB)
    388
    
    Table 9-2. Timebase Lower Register (TBL)
    388
    
    Reading the Time Base
    389
    
    Writing the Time Base
    389
  - Decrementer (DEC)
    389
  - Table 9-3. Timebase Upper Register (TBU)
    389
  - Table 9-4. Decrementer Register (DEC)
    390
  - Table 9-5. Decrementer Auto-Reload Register (DECAR)
    390
  - User Decrementer (UDEC)
    391
  - Fixed Interval Timer (FIT)
    392
  - Table 9-6. Fixed Interval Timer Period Selection
    392
  - Watchdog Timer
    393
  - Table 9-7. Watchdog Timer Period Selection
    393
  - Table 9-8. Watchdog Timer Exception Behavior
    394
  - Timer Control Register (TCR)
    395
  - Figure 9-2. Watchdog State Machine
    395
  - Timer Status Register (TSR)
    397
  - Freezing the Timer Facilities
    397
  - Selection of the Timer Clock Source
    398
  - Synchronizing Timers Across Multiple Cores
    398
10 Debug Facilities

399
11 Performance Events and Event Selection

449
12 Implementation Dependent Instructions

481
- Miscellaneous
  481
  - Attention (Attn)
    481
- TLB Management Instructions
  482
- ERAT Management Instructions
  496
- Software Transactional Memory Instructions
  509
- Coprocessor Instructions
  513
- Data Cache Block Flush
  523
  - Data Cache Block Flush (Dcbf)
    523
- Data Cache Block Flush by External PID
  524
  - Data Cache Block Flush by External PID (Dcbfep)
    524
13 Power Management Methods

525
- Chip Power Management Controls
  525
- Power-Saving Instructions
  525
  - Power-Saving Instruction Sequence
    526
14 Register Summary

529
15 SCOM Accessible Registers

701
Appendix A. Processor Instruction Summary

737
Appendix B. FU Instruction Summary

756
- FU Instructions Sorted by Opcode
  756
- Table B-1. FU Instructions by Opcode
  756
Appendix C. Debug and Trigger Groups

761
Appendix D. Instruction Execution Performance and Code Optimizations

833
- A2 Pipeline Overview
  833
  - Figure D-1. A2 Pipeline Structure
    833
  - Arbitration Stages
    834
  - Flush Stages
    835
  - Stall Stages
    835
- Fetch
  835
  - Figure D-2. Instruction Cache
    836
  - Fetch Arbitration
    837
  - Instruction Cache Access and Alignment
    837
  - Instruction Cache Misses
    837
  - Next Instruction Fetch Address Computation
    837
  - Branches and Branch Prediction
    838
    
    Figure D-3. Branch Prediction
    839
    
    Branch Direction Prediction and the Branch History Table (BHT)
    840
    
    Branch Target Prediction
    840
    
    Taken-Branch Redirection
    840
    
    Branch Resolution and Mispredictions
    841
  - I-ERAT Misses
    838
  - Instruction Buffer Operation
    838
- Instruction Issue Operation
  841
- Instruction Pair Execution Performance Rules
  841
- Loads, Stores, and Data Cache Organization
  847
  - Overview
    847
  - Table D-3. SRAM Operations
    847
  - Loads
    848
  - Stores
    848
  - Load Miss Queue
    849
  - L2 Command Arbitration
    849
  - D-ERAT Misses
    849
  - Back Invalidations
    849
  - Address Alignment
    849
- Interrupt Effects
  850
- Floating-Point Instruction Handling
  850
- Interrupt Conditions
  854
- Table D-4. Interrupt Conditions
  854
- Flush Conditions
  858
- Table D-5. Flush Conditions
  858
Appendix E. Programming Examples

861

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IBM A2 Manuals

IBM A2 User Manual (864 pages)

Table of Contents

List of Figures

List of Tables

Revision Log

About this Book

List of Acronyms and Abbreviations

1 Overview

2 CPU Programming Model

3 FU Programming Model

4 Initialization

5 Instruction and Data Caches

6 Memory Management

7 CPU Interrupts and Exceptions

8 FU Interrupts and Exceptions

9 Timer Facilities

10 Debug Facilities

11 Performance Events and Event Selection

12 Implementation Dependent Instructions

13 Power Management Methods

14 Register Summary

15 SCOM Accessible Registers

Appendix A. Processor Instruction Summary

Appendix B. FU Instruction Summary

Appendix C. Debug and Trigger Groups

Appendix D. Instruction Execution Performance and Code Optimizations

Appendix E. Programming Examples

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