NEC V850/SB2 Manuals

Manuals and User Guides for NEC V850/SB2. We have 1 NEC V850/SB2 manual available for free PDF download: User Manual

NEC V850/SB2 User Manual (668 pages)

32-Bit Single-Chip Microcontroller

Brand: NEC | Category: Microcontrollers | Size: 5.36 MB

Table of Contents
12
Chapter 1 Introduction

29
Chapter 2 Pin Functions

73
- List of Pin Functions
  
  73
- Pin States
  
  80
- Description of Pin Functions
  
  81
- Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins
  
  92
- Pin I/O Circuits
  
  94
Chapter 3 Cpu Functions

96
- Features
  
  96
- CPU Register Set
  
  97
  - Program Register Set
    98
  - System Register Set
    99
- Operation Modes
  
  102
- Address Space
  
  103
  - CPU Address Space
    103
  - Image
    104
  - Image on Address Space
    104
    
    Wrap-Around of CPU Address Space
    105
  - Program Space
    105
  - Data Space
    105
    
    Memory Map
    106
    
    Area
    107
  - Internal ROM Area (128 KB)
    107
  - Internal Rom/Flash Memory Area (256 KB)
    107
  - Internal Rom/Flash Memory Area (384 KB)
    108
  - Internal Rom/Flash Memory Area (512 KB)
    108
  - Internal RAM Area (8 KB)
    110
  - Internal RAM Area (12 KB)
    110
  - Internal RAM Area (16 KB)
    111
  - Internal RAM Area (24 KB)
    111
  - On-Chip Peripheral I/O Area
    112
  - External Memory Area (When Expanded to 64 K, 256 K, or 1 MB)
    113
    
    External Expansion Mode
    114
  - External Memory Area (When Expanded to 4 MB)
    114
    
    Recommended Use of Address Space
    117
  - Application of Wrap-Around
    117
  - Recommended Memory Map (Flash Memory Version)
    118
    
    Peripheral I/O Registers
    119
    
    Specific Registers
    126
Chapter 4 Bus Control Function

128
- Features
  
  128
- Bus Control Pins and Control Register
  
  128
  - Bus Control Pins
    128
  - Control Register
    129
- Bus Access
  
  129
  - Number of Access Clocks
    129
  - Bus Width
    130
  - Byte Access (8 Bits)
    130
  - Halfword Access (16 Bits)
    130
  - Word Access (32 Bits)
    130
- Memory Block Function
  
  131
  - Memory Block
    131
- Wait Function
  
  132
  - Programmable Wait Function
    132
  - Example of Inserting Wait States
    133
- Idle State Insertion Function
  
  134
  - External Wait Function
    133
  - Relationship between Programmable Wait and External Wait
    133
  - Wait Control
    133
- Bus Hold Function
  
  135
  - Outline of Function
    135
  - Bus Hold Procedure
    136
  - Operation in Power Save Mode
    136
- Bus Timing
  
  137
  - Memory Read
    137
  - Memory Write
    141
  - Bus Hold Timing
    143
- Bus Priority
  
  144
- Memory Boundary Operation Conditions
  
  145
  - Program Space
    145
  - Data Space
    145
Chapter 5 Interrupt/Exception Processing Function

146
- Outline
  
  146
  - Features
    146
- Non-Maskable Interrupt
  
  149
  - Operation
    150
  - Non-Maskable Interrupt Servicing
    150
  - Acknowledging Non-Maskable Interrupt Request
    151
    
    Restore
    152
  - RETI Instruction Processing
    152
    
    NP Flag
    153
    
    Noise Eliminator of NMI Pin
    153
    
    Edge Detection Function of NMI Pin
    154
- Maskable Interrupts
  
  155
  - Operation
    155
  - Maskable Interrupt Servicing
    156
    
    Restore
    157
  - RETI Instruction Processing
    157
    
    Priorities of Maskable Interrupts
    158
  - Example of Multiple Interrupt Servicing
    159
  - Example of Servicing Interrupt Requests Generated Simultaneously
    161
    
    Interrupt Control Register (Xxicn)
    162
    
    In-Service Priority Register (ISPR)
    165
    
    ID Flag
    165
    
    Watchdog Timer Mode Register (WDTM)
    166
    
    Noise Elimination
    166
    
    Edge Detection Function
    168
- Software Exceptions
  
  169
  - Operation
    169
  - Software Exception Processing
    169
    
    Restore
    170
  - RETI Instruction Processing
    170
    
    EP Flag
    171
- Exception Trap
  
  171
  - Illegal Opcode
    171
  - Illegal Opcode Definition
    171
  - Operation
    171
  - Exception Trap Processing
    172
    
    Restore
    173
  - RETI Instruction Processing
    173
- Priority Control
  
  174
  - Priorities of Interrupts and Exceptions
    174
  - Multiple Interrupt Servicing
    174
- Interrupt Latency Time
  
  177
- Periods in Which Interrupt Is Not Acknowledged
  
  177
  - Interrupt Request Valid Timing after EI Instruction
    178
- Interrupt Control Register Bit Manipulation Instructions During DMA Transfer
  
  179
- Key Interrupt Function
  
  180
Chapter 6 Clock Generation Function

182
- Outline
  
  182
- Configuration
  
  183
- Clock Output Function
  
  183
  - Control Registers
    184
- Power Save Functions
  
  188
  - Outline
    188
  - HALT Mode
    189
  - IDLE Mode
    192
  - Software STOP Mode
    194
- Oscillation Stabilization Time
  
  196
- Notes on Power Save Function
  
  197
Chapter 7 Timer/Counter Function

200
- 16-Bit Timer (TM0, TM1)
  
  200
  - Outline
    200
  - Function
    200
  - Configuration
    202
  - Timer 0, 1 Control Registers
    205
- 16-Bit Timer Operation
  
  211
  - Operation as Interval Timer (16 Bits)
    211
  - PPG Output Operation
    213
  - Pulse Width Measurement
    215
  - Operation as External Event Counter
    222
  - Operation to Output Square Wave
    223
  - Operation to Output One-Shot Pulse
    225
  - Cautions
    230
- 8-Bit Timer (TM2 to TM7)
  
  234
  - Outline
    234
  - Functions
    234
  - Configuration
    235
  - Timer N Control Register
    236
- 8-Bit Timer Operation
  
  242
Chapter 8 Watch Timer

253
- Function
  
  253
  - Block Diagram of Watch Timer
    253
- Configuration
  
  254
- Watch Timer Control Registers
  
  255
- Operation
  
  258
Chapter 9 Watchdog Timer

260
- Functions
  
  260
  - Block Diagram of Watchdog Timer
    260
- Configuration
  
  262
- Watchdog Timer Control Register
  
  262
- Operation
  
  265
  - Operation as Watchdog Timer
    265
  - Operation as Interval Timer
    266
- Standby Function Control Register
  
  267
Chapter 10 Serial Interface Function

268
- Overview
  
  268
- 3-Wire Serial I/O (CSI0 to CSI3)
  
  268
  - Configuration
    269
  - Block Diagram of 3-Wire Serial I/O
    269
  - Csin Control Registers
    270
  - Operations
    272
  - Csimn Setting (Operation Stop Mode)
    272
  - Csimn Setting (3-Wire Serial I/O Mode)
    273
  - Timing of 3-Wire Serial I/O Mode
    274
- I C Bus (a Versions)
  
  275
  - Block Diagram of I 2 C
    276
  - C Bus
    277
  - Configuration
    278
  - C Control Registers
    280
  - I 2 C Bus Mode Functions
    291
  - C Bus's Serial Data Transfer Timing
    292
  - I C Bus Definitions and Control Methods
    292
    
    Pin Configuration Diagram
    292
    
    Address
    293
    
    Start Condition
    293
    
    Transfer Direction Specification
    294
    
    ACK Signal
    295
    
    Stop Condition
    296
    
    Wait Signal
    297
    
    I 2 C Interrupt Requests (Intiicn)
    299
  - Interrupt Request (Intiicn) Generation Timing and Wait Control
    317
  - Address Match Detection Method
    318
  - Error Detection
    318
  - Extension Code
    318
  - Arbitration
    319
  - Arbitration Timing Example
    319
  - Wakeup Function
    320
  - Communication Reservation
    321
  - Communication Reservation Timing
    322
  - Timing for Acknowledging Communication Reservations
    322
  - Communication Reservation Flowchart
    323
  - Cautions
    324
  - Communication Operations
    325
  - Master Operation Flowchart
    325
  - Slave Operation Flowchart
    326
  - Timing of Data Communication
    327
  - (When 9-Clock Wait Is Selected for both Master and Slave) (1/3
    328
  - (When 9-Clock Wait Is Selected for both Master and Slave) (1/3
    331
- I C Bus (B and H Versions)
  
  334
  - Block Diagram of I 2 C
    335
  - Bus
    336
  - Serial Bus Configuration Example Using I
    336
  - Configuration
    337
  - C Control Register
    339
    
    I 2 C Bus Mode Functions
    352
  - C Bus's Serial Data Transfer Timing
    353
  - I C Bus Definitions and Control Methods
    353
  - Pin Configuration Diagram
    353
  - Address
    354
  - Start Conditions
    354
  - Transfer Direction Specification
    355
  - ACK Signal
    356
  - Stop Condition
    357
  - Wait Signal
    358
  - C Interrupt Requests (Intiicn)
    360
  - Interrupt Request (Intiicn) Generation Timing and Wait Control
    378
  - Address Match Detection Method
    379
  - Error Detection
    379
  - Extension Code
    379
  - Arbitration
    380
  - Arbitration Timing Example
    381
  - Wakeup Function
    382
  - Communication Reservation
    383
  - Communication Reservation Timing
    384
  - Timing for Accepting Communication Reservations
    384
  - Communication Reservation Flowchart
    385
  - Timing at Which Sttn = 1 Cannot be Set
    386
  - Master Communication Start or Stop Flowchart
    387
  - Cautions
    388
  - Communication Operations
    389
  - Master Operation Flowchart (1)
    389
  - Master Operation Flowchart (2)
    390
  - Slave Operation Flowchart
    391
  - Timing of Data Communication
    392
  - (When 9-Clock Wait Is Selected for both Master and Slave) (1/3
    393
  - (When 9-Clock Wait Is Selected for both Master and Slave) (1/3
    396
- Asynchronous Serial Interface (UART0, UART1)
  
  399
- 3-Wire Variable-Length Serial I/O (CSI4)
  
  419
Chapter 11 A/D Converter

431
- Function
  
  431
  - Block Diagram of A/D Converter
    432
- Configuration
  
  433
- Control Registers
  
  435
- Operation
  
  438
- Cautions
  
  443
  - Handling of Analog Input Pin
    444
  - A/D Conversion End Interrupt Generation Timing
    445
  - DD Pin
    446
- Low Power Consumption Mode
  
  443
- How to Read A/D Converter Characteristics Table
  
  447
  - Overall Error
    447
  - Quantization Error
    448
  - Zero-Scale Error
    448
  - Full-Scale Error
    449
  - Differential Linearity Error
    449
  - Integral Linearity Error
    450
  - Sampling Time
    450
Chapter 12 Dma Functions

451
Chapter 13 Real-Time Output Function (Rto)

466
- Function
  
  466
- Features
  
  466
- Configuration
  
  467
  - Block Diagram of RTO
    467
  - Configuration of Real-Time Output Buffer Registers
    468
- RTO Control Registers
  
  469
- Usage
  
  471
- Operation
  
  472
  - Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0)
    472
- Cautions
  
  473
Chapter 14 Port Function

474
- Port Configuration
  
  474
- Port Pin Function
  
  474
  - Port 0
    474
  - Block Diagram of P00 to P07
    478
  - Port 1
    479
  - Block Diagram of P10 to P12, P14, and P15
    481
  - Block Diagram of P13
    482
  - Port 2
    483
  - Block Diagram of P20 to P22, P24, and P25
    486
  - Block Diagram of P23, P26, and P27
    487
  - Port 3
    488
  - Block Diagram of P30 to P32 and P35 to P37
    490
  - Block Diagram of P33 and P34
    491
  - Ports 4 and 5
    492
  - Block Diagram of P40 to P47 and P50 to P57
    494
  - Port 6
    495
  - Block Diagram P60 to P65
    497
  - Ports 7 and 8
    498
  - Block Diagram of P70 to P77 and P80 to P83
    499
  - Port 9
    500
  - Block Diagram of P90 to P96
    502
  - Port 10
    503
  - Block Diagram of P100 to P107
    506
  - Port 11
    507
  - Block Diagram of P110 to P113
    510
- Setting When Port Pin Is Used as Alternate Function
  
  511
- Port Function Operation
  
  515
  - Write Operation to I/O Port
    515
  - Read Operation from I/O Port
    515
Chapter 15 Reset Function

516
- General
  
  516
- Pin Operations
  
  516
  - System Reset Timing
    516
- Operation
  
  517
  - Regulator
    517
Chapter 16 Regulator

517
- Outline
  
  517
Chapter 17 Rom Correction Function

518
- General
  
  518
  - Block Diagram of ROM Correction
    518
- ROM Correction Peripheral I/O Registers
  
  519
  - ROM Correction Operation and Program Flow
    522
Chapter 18 Flash Memory

523
- Features
  
  523
  - Erase Unit
    524
  - Write/Read Time
    524
- Writing with Flash Programmer
  
  525
- Programming Environment
  
  530
- Communication Mode
  
  530
- Pin Connection
  
  533
  - VPP Pin
    533
  - Serial Interface Pin
    533
  - RESET Pin
    536
  - Port Pins (Including NMI)
    536
  - Other Signal Pins
    536
  - Power Supply
    536
- Programming Method
  
  537
  - Flash Memory Control
    537
  - Flash Memory Programming Mode
    538
  - Selection of Communication Mode
    539
  - Communication Command
    539
  - Resources Used
    540
CHAPTER 19 Iebus CONTROLLER (V850/SB2)

541
- Iebus Controller Function
  
  541
  - Communication Protocol of Iebus
    541
  - Determination of Bus Mastership (Arbitration)
    542
  - Communication Mode
    542
  - Communication Address
    543
  - Broadcasting Communication
    543
  - Transfer Format of Iebus
    544
  - Transfer Data
    554
  - Bit Format
    557
- Iebus Controller Configuration
  
  558
- Internal Registers of Iebus Controller
  
  560
  - Internal Register List
    560
  - Internal Registers
    561
- Interrupt Operations of Iebus Controller
  
  584
  - Interrupt Control Block
    584
  - Interrupt Source List
    585
  - Communication Error Source Processing List
    586
- Interrupt Generation Timing and Main CPU Processing
  
  588
  - Master Transmission
    588
  - Master Reception
    590
  - Slave Transmission
    592
  - Slave Reception
    594
  - Interval of Occurrence of Interrupt for Iebus Control
    596
Chapter 20 Electrical Specifications

600
Chapter 21 Package Drawings

635
Chapter 22 Recommended Soldering Conditions

637
Appendix Anotes on Target System Design

642
Appendix Bregister Index

644
Appendix Cinstruction Set List

651
Appendix Dindex

658
Appendix Erevision History

664

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NEC V850/SB2 Manuals

NEC V850/SB2 User Manual (668 pages)

Table of Contents

Chapter 1 Introduction

General

V850/SB1 (a Versions)

V850/SB1 (B Versions)

V850/SB2 (a Versions)

V850/SB2 (B and H Versions)

Chapter 2 Pin Functions

List of Pin Functions

Pin States

Description of Pin Functions

Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Functions

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins and Control Register

Bus Access

Memory Block Function

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Timing

Bus Priority

Memory Boundary Operation Conditions

Chapter 5 Interrupt/Exception Processing Function

Outline

Non-Maskable Interrupt

Maskable Interrupts

Software Exceptions

Exception Trap

Priority Control

Interrupt Latency Time

Periods in Which Interrupt Is Not Acknowledged

Interrupt Control Register Bit Manipulation Instructions During DMA Transfer

Key Interrupt Function

Chapter 6 Clock Generation Function

Outline

Configuration

Clock Output Function

Power Save Functions

Oscillation Stabilization Time

Notes on Power Save Function

Chapter 7 Timer/Counter Function

16-Bit Timer (TM0, TM1)

16-Bit Timer Operation

8-Bit Timer (TM2 to TM7)

8-Bit Timer Operation

Chapter 8 Watch Timer

Function

Configuration

Watch Timer Control Registers

Operation

Chapter 9 Watchdog Timer

Functions

Configuration

Watchdog Timer Control Register

Operation

Standby Function Control Register

Chapter 10 Serial Interface Function

Overview

3-Wire Serial I/O (CSI0 to CSI3)

I C Bus (a Versions)

I C Bus (B and H Versions)

Asynchronous Serial Interface (UART0, UART1)

3-Wire Variable-Length Serial I/O (CSI4)

Chapter 11 A/D Converter

Function

Configuration

Control Registers

Operation

Cautions

Low Power Consumption Mode

How to Read A/D Converter Characteristics Table