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Motorola MC92603 Reference Manual

Motorola MC92603 Reference Manual

Quad gigabit ethernet transceiver
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MC92603RM
12/2003
Rev. 0
MC92603 Quad
Gigabit Ethernet Transceiver

Reference Manual

Device Supported:
MC92603VF

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Summary of Contents for Motorola MC92603

  • Page 1: Reference Manual

    MC92603RM 12/2003 Rev. 0 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual Device Supported: MC92603VF...
  • Page 2 Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners.
  • Page 3 Introduction Transmitter Receiver Management Interface (MDIO) System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Revision History Glossary of Terms and Abbreviations Index...
  • Page 4 Introduction Transmitter Receiver Management Interface (MDIO) System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Revision History Glossary of Terms and Abbreviations Index...

  • Page 5: Table Of Contents

    Ethernet Compliant Applications Modes (COMPAT = High) ......2-9 2.5.1 Transmitting Uncoded Data—GMII or RGMII Modes......... 2-10 2.5.1.1 Auto-Negotiation Process ................2-10 2.5.1.2 Ethernet Data Transmission Process............2-11 2.5.2 Transmitting Coded Data—TBI or RTBI Modes .......... 2-12 Transmitter Redundant Link Operation ............. 2-12 MOTOROLA Contents...
  • Page 6 Jumbo Frame Considerations ..............3-22 Backplane Applications Modes (COMPAT = Low) .......... 3-22 3.8.1 Byte Mode (Uncoded Data)................3-22 3.8.2 10-Bit Mode (Coded Data) ................3-23 3.8.2.1 Double Data Rate Operation—Backplane Applications ......3-24 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA...
  • Page 7 Recovered Clock Mode ................... 5-5 5.5.5 Add/Drop Idle Mode..................5-5 5.5.6 Half-Speed Mode..................... 5-5 Configuration and Control Signals ..............5-6 Power Supply Requirements................5-7 Phase-Locked Loop (PLL) Power Supply Filtering ..........5-7 Power Supply Decoupling Recommendations ............ 5-8 MOTOROLA Contents...
  • Page 8 Receiver, DDR Centered Clock Timing (Ethernet RTBI Mode)... 7-10 7.3.3 Reference Clock Timing ................7-11 7.3.4 Serial Data Link Timing ................7-12 7.3.5 MDIO Interface Timing................. 7-13 7.3.6 JTAG Test Port Timing .................. 7-14 viii MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA...
  • Page 9 MC92603Chip Pinout Listing................8-5 Appendix A Ordering Information Appendix B 8B/10B Coding Scheme Overview......................B-1 B.1.1 Naming Transmission Characters ..............B-2 B.1.2 Encoding ......................B-2 B.1.3 Calculating Running Disparity ................B-3 Data Tables......................B-3 Appendix C Revision History Glossary of Terms and Abbreviations Index MOTOROLA Contents...
  • Page 10 Contents Paragraph Page Number Title Number MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA...
  • Page 11 Figure Page Number Title Number Figures MC92603 Simplified Block Diagram ................. 1-4 MC92603 Block Diagram ................... 1-5 PHY and Backplane Applications................1-6 MC92603 Transmitter Block Diagram ............... 2-2 Configuration Register ....................2-10 MC92603 Receiver Block Diagram................3-2 Control Register (MDIO RA 0) .................. 4-3 Status Register (MDIO RA 1)..................

  • Page 12: Figure Page

    Figures Figure Page Number Title Number MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA...
  • Page 13 MC92603 Receiver Interface Signals ................. 3-3 Receiver Channel A Redundant Link Operation ............3-7 Receiver Channel B Redundant Link Operation............3-7 MC92603 Receiver Operating Modes (Common Features/Characteristics) ....3-8 Byte Synchronization Modes ..................3-8 Word Synchronization Events................... 3-10 Receiver Reference Clock is Slower than Transmitter Reference Clock....3-14 Receiver Reference Clock is Faster than Transmitter Reference Clock ....
  • Page 14 MDIO Interface Timing Specifications ..............7-13 7-15 JTAG I/O Timing Specifications................7-14 MC92604 Package Thermal Resistance Values............8-5 MC92603 Signal to Ball Mapping ................8-5 Components of a Character Name ................B-2 Valid Data Characters....................B-4 Valid Special Characters .....................B-8 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 15: About This Book

    • Chapter 1, “Introduction,” gives an overview of the device features and shows a block diagram of the major functional blocks of the part. • Chapter 2, “Transmitter,” describes the MC92603 transmitter, its interfaces, and operational options. • Chapter 3, “Receiver,” gives a description of the receiver, its interfaces, and operation.

  • Page 16: Suggested Reading

    Edition, David A. Patterson and John L. Hennessy Related Documentation Motorola documentation is available from the sources listed on the back cover of this book; the document order numbers are included in parentheses for ease in ordering: • Reference manuals—These books provide details about individual device implementations.

  • Page 17: Conventions

    MC92603. Its operation is covered in the MC92603 Evaluation Kit User’s Guide (MC92603EKVUG). • Addenda/errata to reference manuals—Because some devices have follow-on parts an addendum provides any additional features and functionality changes. These addenda are intended for use with the corresponding reference manuals.
  • Page 18 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 19: Introduction

    MDIO register set as specified in the above standard. The MC92603 GEt is designed as four parts in one. It may be configured as either a 1 Gigabit backplane serializer/deserializer (SerDes) with functionally similar to the 1.25 Gbaud Quad SerDes (MC92600), or as a Quad 1 Gigabit Ethernet PHY and the...

  • Page 20: Features

    Features The MC92603 features transmit FIFOs and source synchronous transmit clocks per channel to further simplify interfacing. Additionally, IEEE Std 1149.1—1990™ JTAG boundary scan and built-in PRBS generator/analyzers are provided for board test support. Features The MC92603 has two applications-oriented operating modes depending on the configuration.

  • Page 21: Receiver

    — Provides the PCS and PMA layers for Ethernet PHYs as specified in IEEE Std. 802.3-2000 — MDIO slave interface and registers as defined in IEEE Std. 802.3-2002 are fully supported — Supports rate adaption within IPG for jumbo frames up to 14 Kbytes MOTOROLA Chapter 1. Introduction...

  • Page 22: Block Diagram

    No external components, other than the normal power supply decoupling network, are required. A simplified block diagram of the MC92603 device is shown in Figure 1-1, and a full block diagram is provided in Figure 1-2.

  • Page 23: Mc92603 Block Diagram

    RLINK_D_N Configuration signal inputs are: RECV_REF_A, COMPAT, REPE, HSE, ADIE, TBIE, BSYNC, LBOE, DROP_SYNC, TST_0, TST_1, WSYNC0, WSYNC1, STNDBY, XMIT_REF_A, MEDIA, RCCE, JPACK, RECV_CLK_CENT, DDR, ENABLE_AN, USE_DIFF_CLK, ENAB_RED, BROADCAST, XCVR_A_RSEL, XCVR_B_RSEL Figure 1-2. MC92603 Block Diagram MOTOROLA Chapter 1. Introduction...

  • Page 24: Phy And Backplane Applications

    (PMA) sublayer for 1000BASE-X PHY as defined in clause 36 of the IEEE Std. 802.3-2002 specification [4]. Figure 1-3 shows a typical application for the MC92603 which may be used as a quad 1000BASE-X PHY or in backplane applications. On high density line cards with a large number of Gig-Ethernet ports, it is desirable to use the RGMII interfaces to reduce the number of signal traces on the PCB.

  • Page 25: References

    [3] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-1990 (includes IEEE Std. 1149.1a-1993), Oct. 1993. [4] IEEE Standard Carrier Sense Multiple-Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Std. 802.3-2002, March 2002. MOTOROLA Chapter 1. Introduction...
  • Page 26 References MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 27: Transmitter

    • Section 2.5, “Ethernet Compliant Applications Modes (COMPAT = High)” • Section 2.6, “Transmitter Redundant Link Operation” The MC92603 is a versatile device that may be used in backplane SerDes or Ethernet PHY applications. It may be configured in multiple data interface and operational modes. The following sections provide a basic functional description of the transmitter, its operational modes, and data interfaces.

  • Page 28: Transmitter Block Diagram

    Figure 2-1. MC92603 Transmitter Block Diagram Transmitter Interface Signals This section describes the interface signals of the MC92603 transmitters. Each signal’s name, function, direction, and active state is described in Table 2-1. The table’s signal names use the letter ‘x’ as a place holder for the link identifier letter ‘A’ through ‘D.’...
  • Page 29 Transmitter Interface Signals Table 2-1. MC92603 Transmitter Interface Signals Active Signal Name Description Function Direction State XMIT_x_CLK Channel transmit clock Clock input for each channel Input — XMIT_x_[7:0] Transmit data byte 8 bits of transmit data Input — XMIT_x_K Transmit control/data bit...

  • Page 30: Transmitter Interface Configuration

    Transmitter Interface Configuration Table 2-1. MC92603 Transmitter Interface Signals (continued) Active Signal Name Description Function Direction State XCVR_x_RSEL Select redundant link Transmit data on the secondary (redundant) Input High link TST_1, TST_0 Test mode config inputs Decoded to define various test modes (see Input —...

  • Page 31: Transmit Driver Operation

    This is enabled by asserting XMIT_REF_A high. When XMIT_REF_A is high, the XMIT_A_CLK becomes the interface clock for all active channels. The configuration settings of the MC92603 affect the legal range of clock frequencies at which it may be operated. Table 5-1 shows legal transmit interface clock frequencies for all modes of operation.

  • Page 32: Repeater Mode Operation

    REPE, should be configured low during a normal transceiver operation. Backplane Application Modes (COMPAT = Low) When the configuration control signal, COMPAT, is low, the MC92603 is in the ‘backplane application mode.’ In this application mode, the MC92603 transmitters accept either uncoded data, where the input data is encoded internally by an 8B/10B encoder, or coded data, where the input data is pre-encoded and the internal encoder is bypassed.
  • Page 33 The 8 bits of uncoded data are entered with the least significant nibble on the rising clock and the most significant nibble on the falling clock edge. NOTE When operating with the reduced data interface the MC92603 input pins, XMIT_x_7–XMIT_x_4, are unused and should be terminated low.

  • Page 34: Transmitting Coded Data-10-/5-Bit Modes

    The XMIT_x_K signal is ignored by the transmitter in the backplane 10-/5-bit modes, but, it is used by the receiver. When using the MC92603 in the backplane applications (COMPAT = low), it is not necessary to use the 8B/10B code set. However, special care must be taken. The data must exhibit the same properties as 8B/10B coded data.

  • Page 35: Ethernet Compliant Applications Modes (Compat = High)

    The MC92603 Gigabit Ethernet transceiver was designed with the intent to meet the requirements of IEEE Std 802.3-2002 [4] for 1000BASE-X PHYs. When the configuration control signal, COMPAT, is high, the MC92603 is in the ‘Ethernet compliant application mode.’ In this application mode, the MC92603 transmitters accept...

  • Page 36: Transmitting Uncoded Data-Gmii Or Rgmii Modes

    This forces the remote device to also enter auto-negotiate mode. The contents of the configuration register are continuously sent until the associated receiver detects the compatible configuration being sent from the link partner. The MC92603 is configured as full-duplex 1-Gigabit; therefore, the configuration is as shown in Figure 2-2.

  • Page 37: Ethernet Data Transmission Process

    0x55 code groups followed by a 0xD5 code group. The transmitter replaces the first 0x55 code group in the preamble with a /S/ Ordered_set to indicate Start_of_Frame. The MC92603 will support shorter preambles. The minimum preamble size is a single 0x55 code group followed by a 0xD5 code group.

  • Page 38: Transmitting Coded Data-Tbi Or Rtbi Modes

    Data—10-/5-Bit Modes.” Transmitter Redundant Link Operation The MC92603 is configured as a dual channel SerDes, with redundant link input and outputs, if the enable redundancy signal, ENAB_RED, is asserted high. Only the data interface to channels A and B will accept data to be transmitted. This data will be transmitted over the appropriate link as specified by the BROADCAST and XCVR_x_RSEL inputs as shown in Table 2-9 and Table 2-10.
  • Page 39 Table 2-10. Transmit Channel B Redundant Link Operation ENAB_RED BROADCAST XCVR_B_RSEL Action Don’t care Don’t care Data transmitted over XLINK_B_P/XLINK_B_N. Data transmitted over XLINK_B_P/XLINK_B_N. Data transmitted over XLINK_D_P/XLINK_D_N. Don’t care Data transmitted over XLINK_B_P/XLINK_B_N and XLINK_D_P/XLINK_D_N. MOTOROLA Chapter 2. Transmitter 2-13...
  • Page 40 Transmitter Redundant Link Operation 2-14 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 41: Receiver

    Chapter 3 Receiver This chapter describes the MC92603 receiver, its interfaces, and operation. This chapter consists of the following sections: • Section 3.1, “Receiver Block Diagram” • Section 3.2, “Receiver Interface Signals” • Section 3.3, “Functional Description” • Section 3.4, “Receiver Interface Configuration”...

  • Page 42: Receiver Block Diagram

    Receiver Block Diagram Receiver Block Diagram Figure 3-1 shows the MC92603 receiver’s block diagram. MEDIA HSE,BSYNC rx_clock (from PLL) loop_back_data RECV Delay Line RLINK RLINK Transition Tracking Loop and Comma Detection DROP_SYNC Data Recovery Byte Alignment XCVR DISABLE (from redundant link)

  • Page 43: Receiver Interface Signals

    Receiver Interface Signals Receiver Interface Signals This section describes the interface signals of the MC92603 receiver. Each signal’s name, function, direction, and active state is described in Table 3-1. The table’s signal names use the letter ‘x’ as a place holder for the link identifier letter ‘A’ through ‘D.’ Internal signals listed in the table are not available at the external interface of the device, but are presented to help illustrate the device’s operation.
  • Page 44 Receiver Interface Signals Table 3-1. MC92603 Receiver Interface Signals (continued) Active Signal Name Description Function Direction State COMPAT IEEE Std. 802.3-2002 Indicates that the receiver is in a IEEE Std. Input High compatibility mode enable 802.3-2002 compliant mode. If code group...

  • Page 45: Functional Description

    Functional Description Functional Description The MC92603 receiver receives differential data in one of two operating ranges. It may be operated in full rate range with a maximum data rate of 1.0 Gbps (1.25 Gigabaud) or at half-rate at 500 Mbps (0.625 Gigabaud). The operating range is determined by the state of the HSE input and the frequency of the reference clock, see Table 5-1.

  • Page 46: Transition Tracking Loop And Data Recovery

    The input amplifier facilitates a loopback path for production and in-system testing. When the MC92603 is in loopback mode (loopback enable, LBE, is high), the input amplifier selects the loopback differential input signals and ignores the state on the RLINK_x_P and RLINK_x_N signals.

  • Page 47: Half-Speed Mode

    3.3.6 Receiver Redundant Link Operation The MC92603 is configured as a dual channel SerDes with redundant links if the enable redundancy signal, ENAB_RED, is high. Only channels A and B received data interfaces are active in this mode. This data will be received from the appropriate link, as specified by the XCVR_A_RSEL and XCVR_B_RSEL inputs shown in Table 3-2 and Table 3-3.

  • Page 48: Data Alignment Configurations

    Data Alignment Configurations received data is obtained, may be operated in five operating modes as described in Table 3-4. Table 3-4. MC92603 Receiver Operating Modes (Common Features/Characteristics) Operating Mode BSYNC COMPAT TBIE Backplane 10- or 5-bit coded data modes—non-aligned High Backplane 10- or 5-bit coded data modes—aligned...

  • Page 49: Non-Aligned Mode (Bsync = Low)

    Alignment remains locked until any one of three events occur that indicate loss of alignment: • Alignment is lost when a misaligned COMMA sequence is detected. The MC92603 can be configured to automatically realign to a new COMMA sequence. This mode...

  • Page 50: Word Synchronization

    3.5.3 Word Synchronization When the MC92603 is configured in either of the ‘aligned backplane’ modes (BSYNC high and COMPAT low), the four receivers can be used cooperatively to receive 32-bit (40-bit if TBIE is high) aligned word transfers. Word alignment is enabled by asserting the word synchronization enable inputs, WSYNC1 or WSYNC0, high.
  • Page 51 Idle characters. Therefore, if operating in TBI mode, either the Idle character must be a supported member of the code set or the ‘A’ character alignment must be used. MOTOROLA Chapter 3. Receiver 3-11...

  • Page 52: Receiver Interface Timing Modes

    The frequency of the receiver clock will be the local reference clock until synchronization is achieved. The RECV_x_RCLK clock signals, however, are not present during power up or when the MC92603 is in reset mode and the PLL is not locked.

  • Page 53: Reference Clock Timing Mode (Rcce = Low)

    8.2 ns. NOTE Devices that interface to a MC92603 and are run in a recovered clock mode, must be able to tolerate this modulated clock. When operating in the recovered clock timing mode, the addition or deletion of IDLEs is inappropriate.
  • Page 54 IDLE bytes when underrun is imminent. This allows the user to establish ‘packets’ of data that do not contain IDLEs and the MC92603 will not insert IDLEs in the middle of these ‘packets.’ The IDLE frequency to prevent underrun is identical to the frequency to prevent overrun, so the same conditions apply.

  • Page 55: Ethernet Compliant Applications Modes (Compat = High)

    Ethernet Compliant Applications Modes (COMPAT = High) The following sections discuss Ethernet compliant applications modes as implemented by the MC92603. Different Ethernet operations and protocols as described in the IEEE Std. 802.3-2002 specification [4], are also discussed. 3.7.1 Interface to Ethernet MAC The operation of the transceivers in the Ethernet-compatible GMII and TBI modes and the correlation of the port signal names to the names in the IEEE Std.
  • Page 56 Data Normal operation, valid data code group received. High High 0x20 Error propagation High High 0x10 Disparity error High High 0x08 Code error High High 0x04 Overrun High High 0x02 Underrun 3-16 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 57: Tbi Operation

    The Ethernet TBI interface is enabled by asserting the TBIE and COMPAT inputs high. When in this mode, the MC92603 will conform to the IEEE Std. 802.3-2002 TBI interface signals and protocol. The complete TBI connection to a standard Ethernet MAC is shown in Table 3-11.

  • Page 58: Double Data Rate Operation-Rgmi And Rtbi

    Data bit [7:4] Table 3-14. Receiver RTBI Interface Rising Edge of RECV_x_COMMA RECV_x_DV RECV_x_[3:0] Clock RECV_x_RCLK COM_DET Data bit 4 Data bit [3:0] RECV_x_RCLK_B COM_DET Data bit 9 Data bit [8:5] 3-18 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 59: Rate Adaption Of Ethernet Packet Data Streams

    3.7.2.1 Rate Adaption Method The MC92603 utilizes a FIFO in its receiver to act as an elastic buffer for the receive data interface. The elastic buffer allows for proper operation of the interface in the presence of jitter and frequency offset. However, frequency offset will eventually lead to elastic buffer overrun or underrun.

  • Page 60: Configuration Context

    /C1/ and /C2/ code group sets. On detection of an imminent overflow, the MC92603 searches for and deletes two /C1/C2/ code group sets, removing a total of 16 code groups from the packet stream. The auto-negotiation function can tolerate missing two complete sets because of its handshaking protocol.

  • Page 61: Data Context

    IPG has at least 12 code groups in length when received. On detection of an imminent underflow, the MC92603 searches for an /I2/ ordered set and repeats an /I2/ in the packet stream, adding a total of two code groups. The packet stream tolerates additional /I2/ ordered sets because maximum IPG length is not limited.

  • Page 62: Jumbo Frame Considerations

    (RCCE is high) be used to reduce power and latency. It should be noted that it is possible for the MC92603 transmit controller to shorten the IPG by two to achieve even/odd alignment and for the receiver to remove four code groups in the IPG to perform rate adaption if in ‘reference clock mode.’...

  • Page 63: 10-Bit Mode (Coded Data)

    Received data is 10 bits of coded data. The internal 8B/10B decoder is bypassed. Receiver data presented signals: RECV_x_ERR, RECV_x_DV, RECV_x_7–RECV_x_0 (making up bits 9–0, respectively). The RECV_x_COMMA is asserted high whenever the 10-bit code group is 1 of the 3 COMMA code groups. MOTOROLA Chapter 3. Receiver 3-23...

  • Page 64: Double Data Rate Operation-Backplane Applications

    Table 3-18. DDR Backplane Coded Data (10-Bit Mode) Clock Edge RECV_x_K RECV_x_COMMA RECV_x_DV RECV_x_[3:0] Rising RECV_x_K RECV_x_COMMA Data bit 4 Data bit [3:0] Falling RECV_x_K RECV_x_COMMA Data bit 9 Data bit [8:5] 3-24 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 65: Management Interface (Mdio)

    MDIO Interface The MC92603 chip MDIO interface consists of one enable input, five address inputs, one clock input, and one bidirectional data signal. Some users may wish to use the MDIO interface, and others may not. If the MDIO interface is to be used then the MDIO enable input, MDIO_EN, must be asserted high.

  • Page 66: Mdio Registers

    MDIO Registers The 2 least significant bits of the 5-bit address, MD_ADR1 and MD_ADR0, are used to uniquely identify each MC92603 channel (00 indicates channel A, 01 = B, 10 = C, and 11 = indicates channel D). The 2.5-MHz data interface clock, MD_CLK, is sourced at the MDIO master (MAC) and is used by each slave MDIO device.

  • Page 67: Mdio Ra 0-Control Register

    Bit 8 is forced to one and may not be modified. MC92603 always runs in full-duplex mode. (R) Collision test Bit 7 is forced to zero and may not be modified. MC92603 does not run in half-duplex mode and, therefore, does not detect collisions. (R) Speed select [1] Bit 6 is forced to one and may not be modified.

  • Page 68: Mdio Ra 1-Status Register

    MDIO Registers 4.2.2 MDIO RA 1—Status Register Figure 4-2 shows the format for the status register, MDIO RA 1, in the MC92603. The status register is a read-only register. 10 Mb/s 10 Mb/s 100BASE- 100BASE- 100BASE- 100BASE-X 100BASE-X Extended Full-...

  • Page 69: Mdio Ra 2 And 3-Phy Identifier Registers

    Bit 1 is forced to zero and may not be modified. (R) Extended capability Bit 0 is forced to one and may not be modified. The MC92603 has a specific status and configuration register (register 17) for each channel. (R) R = read only, LH = latches high, and SC = self-cleaning.

  • Page 70: Mdio Ra 4-Auto-Negotiation Advertisement Register

    Table 4-4. AN Advertisement Register (MDIO RA 4) Field Descriptions Bits Name Description Next page Forced to zero. The MC92603 does not support multiple pages of configuration registers. (R) Acknowledge Ack—is set when the receiver detects a valid configuration from the link partner’s transmitter. (R) Remote fault 2 Bits 13 and 12 are remote faults as detected by the receiver.

  • Page 71: Mdio Ra 5-Auto-Negotiation Link Partner Ability Register

    MDIO RA 5—Auto-Negotiation Link Partner Ability Register Figure 4-5 shows the format for the auto-negotiation (AN) link partner register, MDIO RA 5, in the MC92603. Register 5 is a read-only register and contains the advertised ability of the link partner. 11 10...

  • Page 72: Mdio Ra 6-Auto-Negotiation (An) Expansion Register

    MDIO RA 6—Auto-Negotiation (AN) Expansion Register Figure 4-6 shows the format for the auto-negotiation (AN) expansion register, MDIO RA 6, in the MC92603. All bits of register 6 are read-only and the register contains data received from the link partner. Reserved...

  • Page 73: Mdio Ra 16 (Vendor Specific)-Permanent Configuration Control Register

    They may be modified through the MDIO interface, but if they are written through this interface, the logic within the MC92603 is reset, and normal operations will be interrupted until individual channels are resynchronized. Figure 4-8 shows the content of register 16.

  • Page 74: System Design Considerations

    2 microseconds instead of the usual 10 milliseconds. Note that this is for use during test only. (R/W) Initialized to the value on the DDR input. If set, causes the MC92603 to use a DDR interface. See Section 2.5.1.2, “Ethernet Data Transmission Process” and Section 3.7.1.3, “Double Data Rate Operation—RGMI and RTBI.”...

  • Page 75: Mdio Ra 17 (Vendor Specific)-Channel Configuration And Status Register

    MDIO RA 17 contains the MC92603 channel configuration and status register. These bits are initially loaded on power up from the corresponding states of the external MC92603 configuration input pins. They may be modified through the MDIO interface. It is not necessary to reset the device logic if these bits are modified.

  • Page 76: Mdio Ra 18 (Vendor Specific)-Bert Error Counter Register

    4.2.11 MDIO RA 18 (Vendor Specific)—BERT Error Counter Register The MDIO RA 18, shown in Figure 4-10, contains the MC92603 BERT error counter register. These bits are initially cleared to all zeros. They may be read through the MDIO interface. They are updated from the appropriate channel’s BERT error counter when running any of the BERT tests.

  • Page 77: System Design Considerations

    • Section 5.7, “Power Supply Requirements” • Section 5.8, “Phase-Locked Loop (PLL) Power Supply Filtering” • Section 5.9, “Power Supply Decoupling Recommendations” This chapter describes general system considerations for the MC92603 Quad Gigabit Ethernet transceiver, including the following: • Device startup •...

  • Page 78: Reference Clock Configuration

    Startup The MC92603 begins a startup sequence on application of the reference clock input to the device. This is considered a cold startup. The cold startup sequence is as follows: 1. PLL startup 2.

  • Page 79: Standby Mode

    WSYNC1 or WSYNC0 = high Standby Mode Standby mode puts the MC92603 into a low power, inactive state. When STNDBY is asserted high, the device will force all transmitter link outputs to their disabled state as defined in Section 2.3.1, “Transmit Driver Operation,” and disables all internal clocking.

  • Page 80: Repeater Mode

    Repeater Mode Repeater Mode The MC92603 may be configured into a two-link receive-transmit repeater by setting the repeater mode enable, REPE, signal high. In repeater mode, data received on link A’s receiver is forwarded to link A’s transmitter and link B’s receiver to link B’s transmitter.

  • Page 81: Word Synchronization Mode

    5.5.4 Recovered Clock Mode The MC92603’s four transmitters are timed exclusively to the reference clock domain; therefore, the recovered clock mode cannot be used in repeater mode. The setting on the recovered clock enable input, RCCE, is ignored when in repeater mode, and all data is timed to the reference clock.

  • Page 82: Configuration And Control Signals

    However, these signals may still affect device operation. Table 5-3 lists all of the MC92603 asynchronous configuration and control signals and describes the effect of changing their state after power up.

  • Page 83: Power Supply Requirements

    Device must be reset Power Supply Requirements The recommended board for the MC92603 has a minimum of two solid planes of 1-ounce copper. One plane is to be used as a ground plane and the second plane is to be used for the 1.8-V supply.

  • Page 84: Power Supply Decoupling Recommendations

    Where the board has blind vias, these capacitors should be placed directly below the MC92603 supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the MC92603, as close to the supply and ground connections as possible.

  • Page 85: Test Features

    • Section 6.3, “BIST Sequence Test with Internal Digital Loopback Mode” The MC92603 supports several test modes for built-in system test, BIST, and production testing. The MC92603 also has an IEEE Std. 1149.1 [3] compliant test access port and boundary scan architecture implementations. This chapter covers the JTAG implementation and the system accessible test modes.

  • Page 86: Instruction Register

    Code Enabled Serial Test Data Path BYPASS 1111 Bypass register CLAMP 1100 Bypass register EXTEST 0000 Boundary scan register HIGHZ 1001 Bypass register IDCODE 0001 ID register SAMPLE 0010 Boundary scan register MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 87: Boundary Scan Register

    6.1.4 Boundary Scan Register A full description of the boundary scan register may be found in the boundary scan description language (BSDL) file provided by Motorola upon request. 6.1.5 Device Identification Register (0x0281E01D) Figure 6-2 shows the format for the device identification register. All bits of the register are read-only.

  • Page 88: System Accessible Test Modes

    6.2.1 Loopback System Test Each channel of MC92603 may be individually configured for digital loopback, where the transmitted data is looped back to its receiver independent of the receiver’s link inputs. This is enabled by asserting XCVR_x_LBE (where ‘x’ is channel A through D) high. The code groups transmitted are controlled by the normal transmitter controls.

  • Page 89: Bist Sequence System Test With External Loopback Modes

    BIST Sequence System Test with External Loopback Modes The MC92603’s transmitter has an integrated, 23rd order, pseudo-noise (PN) pattern generator. Stimulus from this generator may be used for system testing. The receiver, has a 23rd order signature analyzer that is synchronized to the incoming PN stream and may be used to count code group mismatch errors relative to the internal PN reference pattern.

  • Page 90: Bist Sequence Test With Internal Digital Loopback Mode

    In this mode, the configuration input LBOE controls whether serial data is sent on transmit link outputs (XLINK_x_P and XLINK_x_N). If LBOE is low, the link is quiescent; if LBOE is high, data is transmitted on the link). MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 91: Electrical Specifications And Characteristics

    MC92603. 7.1.1 General Parameters A summary of the general parameters for the MC92603 are as follows: • Package—256 MAPBGA, 17 x 17 mm body size, 1 mm ball pitch • Core power supply—1.8 V + 0.15 V DC •...

  • Page 92: Absolute Maximum Rating

    Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 7.1.3 Recommended Operating Conditions This section describes the recommended operating conditions for the MC92603 as provided in Table 7-2. Table 7-2. Recommended Operating Conditions 1, 2...

  • Page 93: Dc Electrical Specifications

    DC Electrical Specifications DC Electrical Specifications This section describes the MC92603 DC electrical characteristics as provided in Table 7-3. Table 7-3. DC Electrical Specifications Characteristic Symbol Unit Core supply current — PLL supply current — LVCMOS/TTL I/O supply current —...

  • Page 94: Ac Electrical Characteristics

    AC Electrical Characteristics AC Electrical Characteristics The figures and tables in the following sections describe the AC electrical characteristics of MC92603. All specifications stated are for T 40° to 105°C, V = – 1.65 to 1.95 V, V 3.0 to 3.6 V 7.3.1...

  • Page 95: Transmitter Interface, Ddr Timing

    XMIT_x_ENABLE Used only when transmitting uncoded data in backplane modes. Figure 7-2. Transmitter Interface, DDR Timing Diagram Table 7-5 provides the transmitter DDR timing specifications for the MC92603 as defined in Figure 7-2. Table 7-5. Transmitter DDR Timing Specifications Symbol...

  • Page 96: Receiver Interface Timing

    High False High Valid Ethernet RTBI High True Valid Valid High True High Valid Valid Assumes 125-MHz reference clock if HSE is disabled and 62.5-MHz reference clock if HSE is enabled. MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 97: Receiver Interface, Non-Ddr Timing

    AC Electrical Characteristics 7.3.2.1 Receiver Interface, Non-DDR Timing The following sections provide the receiver, non-DDR timing specifications for the MC92603. 7.3.2.1.1 Receiver, Non-DDR Clock Timing (All Modes Except Ethernet TBI Modes) Figure 7-3 provides the receiver interface, non-DDR timing diagram when TBIE is negated low or COMPAT is negated low.

  • Page 98: Receiver Interface, Non-Ddr Clock Timing (Ethernet Tbi Mode)

    32.20 31.800 — Rising edge of RECV_x_RCLK to rising 7.80 8.20 7.800 8.200 edge of RECV_x_RCLK_B 15.80 16.20 15.800 16.200 10 pF output load. Full-speed, HSE = low. Half-speed, HSE = high. MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 99: Receiver Interface, Ddr Timing

    AC Electrical Characteristics 7.3.2.2 Receiver Interface, DDR Timing The following sections provides the receiver, DDR timing specifications for the MC92603. 7.3.2.2.1 Receiver, DDR Clock Timing (All Modes Except Ethernet RTBI Modes) Figure 7-5 provides the receiver interface DDR timing diagram when TBIE is negated low or COMPAT is negated low.

  • Page 100: Receiver, Ddr Centered Clock Timing (Ethernet Rtbi Mode)

    Falling edge of either clock to rising edge of –0.200 0.200 –0.200 0.200 other clock –0.200 0.200 –0.200 0.200 10 pF output load. Full-speed, HSE = low. Half-speed, HSE = high. 7-10 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 101: Reference Clock Timing

    AC Electrical Characteristics 7.3.3 Reference Clock Timing The following section provides the reference clock timing for the MC92603. Figure 7-7 provides the reference clock timing diagram. REF_CLK_N REF_CLK_P diff range Figure 7-7. Reference Clock Timing Diagram Table 7-11 provides the reference clock specifications.

  • Page 102: Serial Data Link Timing

    AC Electrical Characteristics 7.3.4 Serial Data Link Timing The following section provides the serial data link timing for the MC92603. Figure 7-8 provides the link differential output timing diagram. XLINK_x_P XLINK_x_N Figure 7-8. Link Differential Output Timing Diagram Table 7-12 provides the link differential output timing specifications.

  • Page 103: Mdio Interface Timing

    AC Electrical Characteristics 7.3.5 MDIO Interface Timing The following section provides the MDIO interface timing for the MC92603. Figure 7-10 provides the MDIO interface timing diagram. MD_CLK MD_DATA MD_CLK MD_DATA Figure 7-10. MDIO Interface Timing Diagram Table 7-14 provides the MDIO interface timing specifications.

  • Page 104: Jtag Test Port Timing

    7.3.6 JTAG Test Port Timing This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MC92603. Figure 7-11 provides the JTAG I/O Timing Diagram. TRST Figure 7-11. JTAG I/O Timing Diagram Table 7-15 provides the JTAG I/O timing specifications.

  • Page 105: Package Description

    • Section 8.4, “MC92603Chip Pinout Listing” The following section provides the package parameters and mechanical dimensions of the MC92603device. The MC92603 is offered in a 256 MAPBGA package. The 256 MAPBGA utilizes an aggressive 1 mm ball pitch and 17 mm body size for applications where board space is limited.

  • Page 106: Mapbga Nomenclature

    METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 12 11 10 6 5 4 3 2 1 15X e 256X 0.25 Z X Y 0.10 BOTTOM VIEW VIEW M–M Figure 8-1. 256 MAPBGA Nomenclature MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 107: Mapbga Dimensions

    DATUM Z (SEATING PLANE) IS DEFINED BY THE 17.00 BSC SPHERICAL CROWNS OF THE SOLDER BALLS. 1.00 BSC PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF 0.50 BSC PACKAGE. Figure 8-2. 256 MAPBGA Dimensions MOTOROLA Chapter 8. Package Description...

  • Page 108: Mc92603 Package Ball Mapping

    XCVR_ LBOE A_ERR D_LBE DISABLE DISABLE A_LBE XMIT_ GTX_ XCVR_ XMIT_ XMIT_ XMIT_ XMIT_ XMIT_ XMIT_A_ TST_1 COMPAT JPACK D_ERR CLK_0 C_LBE View G-G (Bottom View) Figure 8-3. MC92603 Package Ball Mapping MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 109: Package Thermal Characteristics

    MC92603Chip Pinout Listing Table 8-2 list the MC92603signal to ball location mapping for the package. Also shown are signaling direction (input or output), and the type of logic interface. Table 8-2. MC92603 Signal to Ball Mapping Ball Number (256 Signal Name...
  • Page 110 MC92603Chip Pinout Listing Table 8-2. MC92603 Signal to Ball Mapping (continued) Ball Number (256 Signal Name Description Direction I/O Type MAPBGA) RECV_A_3 Receiver A, Data bit 3 Output LVTTL RECV_A_4 Receiver A, Data bit 4 Output LVTTL RECV_A_5 Receiver A, Data bit 5...
  • Page 111 MC92603Chip Pinout Listing Table 8-2. MC92603 Signal to Ball Mapping (continued) Ball Number (256 Signal Name Description Direction I/O Type MAPBGA) RECV_B_ERR Receiver B, Error Detect Output LVTTL RECV_B_RCLK Receiver B, Receive Data Clock Output LVTTL RECV_B_RCLK_B Receiver B, Data Clock Complement...
  • Page 112 MC92603Chip Pinout Listing Table 8-2. MC92603 Signal to Ball Mapping (continued) Ball Number (256 Signal Name Description Direction I/O Type MAPBGA) XMIT_D_0 Transmitter D, Data bit 0 Input LVTTL XMIT_D_1 Transmitter D, Data bit 1 Input LVTTL XMIT_D_2 Transmitter D, Data bit 2...
  • Page 113 MC92603Chip Pinout Listing Table 8-2. MC92603 Signal to Ball Mapping (continued) Ball Number (256 Signal Name Description Direction I/O Type MAPBGA) REF_CLK_P PECL Reference Clock Positive Input Input LVPECL REF_CLK_N PECL Reference Clock Negative Input Input LVPECL TTL_REF_CLK TTL Reference Clock Input...
  • Page 114 MC92603Chip Pinout Listing Table 8-2. MC92603 Signal to Ball Mapping (continued) Ball Number (256 Signal Name Description Direction I/O Type MAPBGA) Core Logic Supply (10) F8-9, G6, G11, H6, Supply H11, L6-7,L10-11 Core Logic Ground/ (36) A1-2, A16, B1-2, B16,...

  • Page 115: Appendix A Ordering Information

    Appendix A Ordering Information Figure A-1 provides the Motorola part numbering nomenclature for the MC92603 Quad Gigabit Ethernet transceiver. For product availability, contact your local Motorola Semiconductor sales representative. M C 9 2 6 0 3 V F — Product Code:...
  • Page 116 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 117: Appendix B 8B/10B Coding Scheme

    Appendix B 8B/10B Coding Scheme The MC92603 provides fibre channel-specific 8B/10B encoding and decoding based on the FC-1 fibre channel standard. Given 8 bits entering a channel, the 8B/10B encoding converts them to 10 bits thereby increasing the transition density of the serially transmitted signal.

  • Page 118: B.1.1 Naming Transmission Characters

    4. At the time the character is expanded into 10 bits, it is also encoded into the proper running disparity, either positive (RD+) or negative (RD-) depending on certain calculations (see Section B.1.3, “Calculating Running Disparity”). At start-up, the transmitter assumes negative running disparity. MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 119: B.1.3 Calculating Running Disparity

    Table B-2 displays the full valid data character 8B/10B codes. The values in the “Data Value HGFEDCBA” column are the possible bit values of the unencoded transmission characters. The current RD values are the possible positive and negative running disparity values. MOTOROLA Appendix B. 8B/10B Coding Scheme...
  • Page 120 101110 1001 010001 1001 D30.0 000 11110 011110 0100 100001 1011 D30.1 001 11110 011110 1001 100001 1001 D31.0 000 11111 101011 0100 010100 1011 D31.1 001 11111 101011 1001 010100 1001 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...
  • Page 121 011 11101 101110 0011 010001 1100 D30.2 010 11110 011110 0101 100001 0101 D30.3 011 11110 011110 0011 100001 1100 D31.2 010 11111 101011 0101 010100 0101 D31.3 011 11111 101011 0011 010100 1100 MOTOROLA Appendix B. 8B/10B Coding Scheme...
  • Page 122 101110 1010 010001 1010 D30.4 100 11110 011110 0010 100001 1101 D30.5 101 11110 011110 1010 100001 1010 D31.4 100 11111 101011 0010 010100 1101 D31.5 101 11111 101011 1010 010100 1010 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...
  • Page 123 111 11101 101110 0001 010001 1110 D30.6 110 11110 011110 0110 100001 0110 D30.7 111 11110 011110 0001 100001 1110 D31.6 110 11111 101011 0110 010100 0110 D31.7 111 11111 101011 0001 010100 1110 MOTOROLA Appendix B. 8B/10B Coding Scheme...
  • Page 124 110110 1000 001001 0111 K28.4 100 11100 001111 0010 110000 1101 K29.7 111 11101 101110 1000 010001 0111 K28.5 101 11100 001111 1010 110000 0101 K30.7 111 11110 011110 1000 100001 0111 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 125: Appendix C Revision History

    Appendix C Revision History This appendix provides a list of the major differences between revisions of the MC92603 Quad Gigabit Ethernet Transceiver Reference Manual (MC92603RM). This is the initial version of the manual so there currently are no changes to the document.
  • Page 126 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...

  • Page 127: Glossary Of Terms And Abbreviations

    1.25 billion symbols per second of 8B/10B encoded data. Gigabaud. A unit of speed of symbol transfer. One gigabaud indicates a data throughput of 800 million bits per second requiring a transfer rate of 1.0 billion symbols per second of 8B/10B encoded data. MOTOROLA Glossary Glossary-1...
  • Page 128 Reduced Gigabit Media Independent Interface (RGMII). The reduced interface between the reconciliation sublayer and the physical coding sublayer (PCS). The interface is reduced from 8-bit wide to 4-bit wide and data transfer is DDR. Glossary-2 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...
  • Page 129 Ten bit interface physical layer (TBI PHY) interface. Word synchronization. Alignment of two or more receivers’ data by adjusting for differences in media and systemic delay between them such that data is presented by the receivers in the same grouping as they were transmit. MOTOROLA Glossary Glossary-3...
  • Page 130 Glossary-4 MOTOROLA MC92603 Quad Gigabit Ethernet Transceiver Reference Manual...
  • Page 131 Device identification register 6-3 receiver block diagram 3-2 Disparity Modes calculating B-3 half-speed mode 3-7 repeater mode 3-7 Electrical characteristics 7-1 Operating conditions 7-2 specifications 7-1 Package Features 1-2 description 8-1 nomenclature and dimensions 8-2 parameter summary 8-1 MOTOROLA Index Index-1...
  • Page 132 3-3 DDR timing specification 7-5 7-13 Reference clock Transmitter block diagram 2-2 specification 7-11 References 1-7 Repeater mode 2-6 Revision history 1-7 Uncoded data in 8B/10B coding scheme B-1 Index-2 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA...

  • Page 133: Introduction

    Introduction Transmitter Receiver Management Interface (MDIO) System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Revision History Glossary of Terms and Abbreviations Index...

  • Page 134: Transmitter

    Introduction Transmitter Receiver Management Interface (MDIO) System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Revision History Glossary of Terms and Abbreviations Index...

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