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Figure 9-20 Example of Software Processing when Using ECH and ECL as 8-Bit Event
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown in
the example in figure 9-20. The 8-bit event counter operating clock source is asynchronous event
input from the AEVH pin for ECH, and asynchronous event input from the AEVL pin for ECL.
When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH
flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.
Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the
OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted.
When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this
time, an interrupt request is sent to the CPU.
9.7.4.
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9-21.
Table 9-21
Asynchronous Event Counter Operation Modes
Operation
Mode
Reset Active
ECCSR
Reset
ECH
Reset
ECL
Reset
Note: * When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
Set CH2 to 1
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Sleep
Functions Functions
Functions Functions*
Functions Functions*
Start
End
Counters
Watch
Subactive
Held*
Functions
Functions*
Functions
Functions*
Functions
247
Subsleep
Standby
Functions
Held*
Functions
Functions*
Functions
Functions*
Module
Standby
Held
Halted
Halted
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