Page 1 SRAMs etc.). Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have all been changed to Renesas Technology Corporation. Except for our corporate trademark, logo and corporate statement, no...
Page 2 SuperH™ RISC Engine SH7032 and SH7034 HD6417032, HD6477034, HD6437034, HD6417034 HD6437034B, HD6417034B Hardware Manual ADE-602-062E Rev. 6.0 9/18/02 Hitachi, Ltd.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 Preface The SH7032 and SH7034 are microprocessors that integrate peripheral functions necessary for system configuration with a 32-bit internal architecture SH1-DSP CPU as its core. The SH7032 and SH7034's on-chip peripheral functions include an interrupt controller, timers, serial communication interfaces, a user break controller (UBC), a bus state controller (BSC), a...
Page 5 User's Manuals on the SH7032 and SH7034: Manual Title ADE No. SH7032 and SH7034 Hardware Manual This manual SH-1, SH-2, SH-DSP Programming Manual ADE-602-085 Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual...
Page 6 Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the sections within this manual. Table 1 Manual Organization Abbrevi- Category Section Title ation Contents Overview Overview — Features, internal block diagram, pin layout, pin functions Register configuration, data structure.
Page 7 Table 1 Manual Organization (cont) Abbrevi- Category Section Title ation Contents Pins Pin Function Pin function selection Controller Parallel I/O I/O ports Ports Memory PROM mode, high-speed programming system On-chip RAM Power-Down Power-Down — Sleep mode, standby mode State State Electrical Electrical —...
Page 8 1. Overview 3. Operating modes 2. CPU On-chip modules 4. Exception handling 5. Interrupt controller (INTC) 6. User break controller (UBC) 7. Clock pulse generator (CPG) Timers Buses 10. 16-bit integrated timer 8. Bus state controller (BSC) pulse unit (ITU) 11.
Page 9 Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas in 512 byte units that contain exactly the same contents as the actual registers are thus provided in the on-chip peripheral module space.
Page 10 List of Items Revised or Added for This Version Section Page Description Edition 1.1 SuperH 6, 7 SH7034, SH7032: 2 to 16.6 MHz device deleted. Microcomputer Product On-Chip Operating Operating Temperature Marking Model No. * Number Voltage Frequency Range Model...
Page 11 Table 2.1 Initial bits are undefined Values of Registers 3.1 Types of Note amended Operating Modes and *2 Only modes 0 and 1 are available in the SH7032 and SH7034 Their Selection ROMless version. Table 3.1 Operating Mode Selection 8.11.3 Maximum...
Page 12 Section Page Description Edition 10.4.6 Description amended Complementary 3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM PWM Mode mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and Procedure for TOCXB4 become PWM pins. Selecting Complementary PWM Mode (Figure 10.33): 10.6.15 ITU Table amended...
Page 13 Section Page Description Edition 12.2.2 Timer Note added Control/Status Note: * Only 0 can be written, to clear the flag. Register (TCSR) 13.2.6 Serial Control Initial value added Register Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined) * (Initial value) Internal clock, SCK pin used for serial clock output * (Initial value)
Page 14 Section Page Description Edition 19.1.2 Register Note added Name Abbreviation Initial Value Address* Access size Table 19.2 Standby Control Register Standby control register SBYCR H'1F H'5FFFFBC 8, 16, 32 Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For (SBYCR) details on the register addresses, see section 8.3.5, Area Descriptions.
Page 15 Section Page Description Edition 16.6 MHz deleted (4) DMAC Timing Table 20.8 DMAC Timing 16.6 MHz deleted (5) 16-bit Integrated Timer Pulse Unit Timing Table 20.9 16-bit Integrated Timer Pulse Unit Timing 16.6 MHz deleted (6) Programmable Timing Pattern Controller and I/O Port Timing Table 20.10 Programmable...
Page 16 Section Page Description Edition 20.2.1 Absolute Notes amended Maximum Ratings Item Symbol Rating Unit Table 20.15 Power supply voltage –0.3 to +4.6 Absolute Maximum Input voltage (except port C) –0.3 to V + 0.3 Ratings Input voltage (port C) –0.3 to AV + 0.3 Analog power supply voltage –0.3 to +4.6...
Page 17 Section Page Description Edition 20.2.3 AC 12.5 MHz added and description amended Characteristics 12.5 MHz 20 MHz (1) Clock Timing Item Symbol Unit Figures Table 20.18 Clock EXTAL input high level — — 20.45 pulse width Timing EXTAL input low level —...
Page 18 Section Page Description Edition (4) DMAC Timing 12.5 MHz added Table 20.21 DMAC 12.5 MHz 20 MHz Timing Item Symbol Unit Figure DREQ0, DREQ1 setup time — — 20.65 DRQS DREQ0, DREQ1 hold time — — DRQH DREQ0, DREQ1 Pulse width —...
Page 19 Section Page Description Edition 20.2.4 A/D 12.5 MHz added Converter 12.5 MHz 20 MHz Characteristics Item Unit Table 20.27 A/D Resolution Converter µS Conversion time — — 11.2 — — Characteristics Analog input capacitance — — — — Permissible signal-source impedance —...
Page 20 Section Page Description Edition A.3 Register Status *2 added in Reset and Power- Watchdog timer (WDT) TCNT Initialized Initialized Held Held Down States TCSR Table A.77 Register RSTCR * Initialized Status in Reset and Serial communication Initialized Initialized Initialized Held Power-Down States interface (SCI) Held...
Page 22: Table Of Contents
Contents Section 1 Overview ......................SuperH Microcomputer Features ..................Block Diagram........................Pin Descriptions........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................11 1.3.3 Pin Layout by Mode....................15 Section 2 ........................17 Register Configuration ....................... 17 2.1.1 General Registers (Rn)..................17 2.1.2 Control Registers....................
Page 23 4.1.1 Exception Handling Types and Priorities.............. 51 4.1.2 Exception Handling Operation................53 4.1.3 Exception Vector Table ..................54 Resets..........................56 4.2.1 Reset Types ......................56 4.2.2 Power-On Reset ....................57 4.2.3 Manual Reset......................57 Address Errors........................58 4.3.1 Address Error Sources ..................58 4.3.2 Address Error Exception Handling ...............
Page 24 5.3.2 Interrupt Control Register (ICR) ................75 Interrupt Operation ......................76 5.4.1 Interrupt Sequence ....................76 5.4.2 Stack after Interrupt Exception Handling.............. 78 Interrupt Response Time ....................79 Usage Notes........................80 Section 6 User Break Controller (UBC) ..............81 Overview ..........................81 6.1.1 Features .........................
Page 25 8.2.2 Wait State Control Register 1 (WCR1)..............109 8.2.3 Wait State Control Register 2 (WCR2)..............111 8.2.4 Wait State Control Register 3 (WCR3)..............113 8.2.5 DRAM Area Control Register (DCR) ..............114 8.2.6 Refresh Control Register (RCR) ................117 8.2.7 Refresh Timer Control/Status Register (RTCSR)..........
Page 26 Section 9 Direct Memory Access Controller (DMAC) .......... 175 Overview ..........................175 9.1.1 Features ......................... 175 9.1.2 Block Diagram ...................... 176 9.1.3 Pin Configuration ....................178 9.1.4 Register Configuration ..................179 Register Descriptions......................180 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........... 180 9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........
Page 27 10.2.9 Timer Control Register (TCR) ................242 10.2.10 Timer I/O Control Register (TIOR) ..............244 10.2.11 Timer Status Register (TSR) ................. 246 10.2.12 Timer Interrupt Enable Register (TIER) ............... 247 10.3 CPU Interface ........................249 10.3.1 16-Bit Accessible Registers .................. 249 10.3.2 8-Bit Accessible Registers ..................
Page 28 11.1.2 Block Diagram ...................... 310 11.1.3 Input/Output Pins ....................311 11.1.4 Registers........................ 312 11.2 Register Descriptions......................313 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2) ..........313 11.2.2 Port B Data Register (PBDR)................314 11.2.3 Next Data Register A (NDRA) ................314 11.2.4 Next Data Register B (NDRB)................
Page 29 12.4.5 Internal Reset With Watchdog Timer ..............347 Section 13 Serial Communication Interface (SCI) ............. 349 13.1 Overview ..........................349 13.1.1 Features ......................... 349 13.1.2 Block Diagram ...................... 350 13.1.3 Input/Output Pins ....................351 13.1.4 Register Configuration ..................351 13.2 Register Descriptions......................352 13.2.1 Receive Shift Register ...................
Page 30 14.7 A/D Converter Usage Notes....................423 14.7.1 Setting Analog Input Voltage................423 14.7.2 Handling of Analog Input Pins................423 14.7.3 Switchover between Analog Input and General Port Functions ......424 Section 15 Pin Function Controller (PFC) ..............425 15.1 Overview ..........................425 15.2 Register Configuration .......................
Page 31 19.4.2 Exiting Standby Mode ..................463 19.4.3 Standby Mode Application..................463 Section 20 Electrical Characteristics ................465 20.1 SH7032 and SH7034 Electrical Characteristics ..............465 20.1.1 Absolute Maximum Ratings.................. 465 20.1.2 DC Characteristics....................465 20.1.3 AC Characteristics....................472 (1) Clock Timing....................472 (2) Control Signal Timing..................
Page 32 (10) AC Characteristics Test Conditions.............. 553 20.2.4 A/D Converter Characteristics ................554 Appendix A On-Chip Supporting Module Registers ..........555 List of Registers........................555 Register Tables ........................565 A.2.1 Serial Mode Register (SMR) SCI................565 A.2.2 Bit Rate Register (BRR) SCI ................566 A.2.3 Serial Control Register (SCR) SCI................
Page 33 A.2.38 Break Address Mask Register L (BAMRL) UBC ..........604 A.2.39 Break Bus Cycle Register (BBR) UBC ..............605 A.2.40 Bus Control Register (BCR) BSC................. 606 A.2.41 Wait State Control Register 1 (WCR1) BSC ............607 A.2.42 Wait State Control Register 2 (WCR2) BSC ............608 A.2.43 Wait State Control Register 3 (WCR3) BSC ............
Page 34 A.2.74 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different) ..642 A.2.75 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different) ..642 Register Status in Reset and Power-Down States ..............
Page 36: Overview
SuperH Microcomputer Features SuperH microcomputers (SH7000 series) comprise a new generation of reduced instruction set computers (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has a RISC-type instruction set. Most instructions can be executed in one system clock cycle, which strikingly improves instruction execution speed.
Page 37 Table 1.1 Features of the SH7032 and SH7034 Microcomputers Feature Description Original Hitachi architecture 32-bit internal data paths General-register machine: • Sixteen 32-bit general registers • Three 32-bit control registers • Four 32-bit system registers RISC-type instruction set: • Instruction length: 16-bit fixed length for improved code efficiency •...
Page 38: Operating
Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description Nine external interrupt pins (NMI, IRQ0–IRQ7) Interrupt controller (INTC) Thirty-one internal interrupt sources Sixteen programmable priority levels User break controller Generates an interrupt when the CPU or DMAC generates a bus cycle...
Page 39: Modes Internal
Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description Direct memory Permits DMA transfer between the following modules: access • External memory controller (DMAC) • External I/O (4 channels) • On-chip memory • Peripheral on-chip modules (except DMAC)
Page 40: Clock
Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): • Port A: 16 input/output lines (input or output can be selected for each bit) •...
Page 41 On-Chip Operating Operating Temperature Marking Model No. * Number Voltage Frequency Range Model Package SH7032 ROMless 5.0 V 2 to 20 MHz -20 to +75°C HD6417032F20 HD6417032F20 112-pin plastic QFP (FP-112) -40 to +85°C HD6417032FI20 HD6417032FI20 3.3 V 2 to 12.5 MHz -20 to +75°C...
Page 42 Table 1.2 Product Lineup (cont) Product On-Chip Operating Operating Temperature Marking Model No. * Number Voltage Frequency Range Model Package SH7034B * Mask 3.3 V 4 to 12.5 MHz -20 to +75°C HD6437034BVF12 6437034B(***)F 112-pin plastic QFP (FP-112) -40 to +85°C HD6437034BVFW12 6437034B(***)FW -20 to +75°C HD6437034BVX12...
Page 43: Block Diagram
: Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Notes: *1 The SH7032 has 8 kB of RAM and no PROM or masked ROM. The SH7034 has 4 kB of RAM and 64 kB of PROM or masked ROM.
Page 44: Pin Descriptions
Pin Descriptions 1.3.1 Pin Arrangement PA3/CS7/WAIT PA2/CS6/TIOCB0 PC0/AN0 PA1/CS5/RAS PC1/AN1 PA0/CS4/TIOCA0 PC2/AN2 PC3/AN3 CS3/CASL PC4/AN4 CS1/CASH PC5/AN5 PC6/AN6 PC7/AN7 PB0/TP0/TIOCA2 Top view PB1/TP1/TIOCB2 (FP-112) PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/TCLKC PB7/TP7/TOCXB4/TCLKD PB8/TP8/RxD0 PB9/TP9/TxD0 PB10/TP10/RxD1 PB11/TP11/TxD1 PB12/TP12/IRQ4/SCK0 PB13/TP13/IRQ5/SCK1 Notes: *1 V : SH7034 (PROM version) only *2 Initial value (output) Figure 1.2 Pin Arrangement (FP-112)
Page 45 PA3/CS7/WAIT PC0/AN0 PA2/CS6/TIOCB0 PC1/AN1 PA1/CS5/RAS PC2/AN2 PA0/CS4/TIOCA0 PC3/AN3 CS3/CASL PC4/AN4 PC5/AN5 CS1/CASH PC6/AN6 PC7/AN7 PB0/TP0/TIOCA2 Top view (TFP-120) PB1/TP1/TIOCB2 PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/TCLKC PB7/TP7/TOCXB4/TCLKD PB8/TP8/RxD0 PB9/TP9/TxD0 PB10/TP10/RxD1 PB11/TP11/TxD1 PB12/TP12/IRQ4/SCK0 PB13/TP13/IRQ5/SCK1 Notes: *1 V : SH7034 (PROM version) only *2 Initial value (output) *3 Do not make any connection.
Page 46: Pin Functions
By receiving the BACK signal, a device that has sent a BREQ signal can confirm that it has been granted the bus. Note: * Pin 77 is V in the SH7032 and SH7034 (masked ROM version), and V in the SH7034 (PROM version).
Page 47 I/O Upper data bus parity: Parity data for D15–D8. I/O Lower data bus parity: Parity data for D7–D0. Notes: *1 Use prohibited in the SH7032 and SH7034 ROM-less versions. *2 Can be used in the SH7034 PROM version.
Page 48: Data
Table 1.3 Pin Functions (cont) Pin No. Pin No. Type Symbol (FP-112) (TFP-120) I/O Name and Function WAIT Bus control Wait: Requests the insertion of wait states (cont) ) into the bus cycle when the external address space is accessed. Row address strobe: DRAM row-address strobe timing signal.
Page 49 Table 1.3 Pin Functions (cont) Pin No. Pin No. Type Symbol (FP-112) (TFP-120) I/O Name and Function TIOCA4, 102, 103 109, 110 I/O ITU input capture/output compare (channel 4): 16-bit TIOCB4 Input capture or output compare pins. integrated timer pulse TOCXA4, 104, 105 111, 112...
Page 50: Pin Layout By Mode
1.3.3 Pin Layout by Mode Table 1.4 Pin Layout by Mode PROM Mode PROM Mode Pin No. Pin No. (SH7034 PROM Pin No. Pin No. (SH7034 PROM (FP-112) (TFP-120) MCU Mode Version) (FP-112) (TFP-120) MCU Mode Version) — — PB14/TP14/IRQ6 PB15/TP15/IRQ7 AD10 AD11...
Page 51 Table 1.4 Pin Layout by Mode (cont) PROM Mode PROM Mode Pin No. Pin No. (SH7034 PROM Pin No. Pin No. (SH7034 PROM (FP-112) (TFP-120) MCU Mode Version) (FP-112) (TFP-120) MCU Mode Version) — PA4/WRL (WR) PA5/WRH (LBS) PC0/AN0 PA6/RD PC1/AN1 PA7/BACK PC2/AN2...
Page 52: Section 2 Cpu
Section 2 CPU Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data processing and address calculation.
Page 53: Control Registers
2.1.2 Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip supporting modules.
Page 54: System Registers
2.1.3 System Registers System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address for a subroutine procedure.
Page 55: Data Formats
Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when stored into a register (figure 2.4).
Page 56: Immediate Data Format
2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is handled as longword data.
Page 57 Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded into to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption during branching is reduced by first executing the instruction that follows the branch instruction, and then branching.
Page 58 Table 2.5 Immediate Data Accessing Classification SH7000 Series CPU Conventional CPU 8-bit immediate #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 ..DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 MOV.L #H'12345678, ..DATA.L H'12345678 Note: The address of the immediate data is accessed by @(disp, PC). Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table.
Page 59: Addressing Modes
2.3.2 Addressing Modes Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses Addressing Mnemonic Mode Expression Effective Addresses Calculation Equation Direct The effective address is register Rn. (The operand — register is the contents of register Rn.) addressing Indirect...
Page 60 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation Equation Indirect @(disp:4, Rn) The effective address is Rn plus a 4-bit Byte: Rn + register displacement (disp). disp is zero-extended, and disp addressing remains the same for a byte operation, is doubled Word: Rn + with for a word operation, and is quadrupled for a...
Page 61 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation Equation PC relative @(disp:8, PC) The effective address is the PC value plus an 8-bit Word: PC + disp × 2 addressing displacement (disp). disp is zero-extended, is with dis- doubled for a word operation, and is quadrupled for Longword:...
Page 62: Instruction Formats
Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation Equation Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, — addressing OR, and XOR instructions is zero-extended. #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, —...
Page 63 Table 2.9 Instruction Formats Destination Instruction Format Source Operand Operand Example 0 format — — xxxx xxxx xxxx xxxx n format — nnnn: Register MOVT Rn direct xxxx nnnn xxxx xxxx Control register or nnnn: Register MACH,Rn system register direct Control register or nnnn: Register STC.L...
Page 64 Table 2.9 Instruction Formats (cont) Destination Instruction Format Source Operand Operand Example nm format mmmm: Register nnnn: Register Rm,Rn direct direct mmmm: Register nnnn: Register MOV.L Rm,@Rn xxxx nnnn xxxx direct indirect mmmm mmmm: Register MACH, MACL MAC.W indirect with post- @Rm+,@Rn+ increment (multiply- and-accumulate)
Page 65 Table 2.9 Instruction Formats (cont) Destination Instruction Format Source Operand Operand Example d format dddddddd: GBR R0 (Register MOV.L indirect with direct) @(disp,GBR),R0 displacement xxxx xxxx dddd dddd R0 (Register direct) dddddddd: GBR MOV.L indirect with R0,@(disp,GBR) displacement dddddddd: PC R0 (Register MOVA relative with...
Page 66: Instruction Set
Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions Classifi- Operation Number of cation Types Code Function Instructions Data Data transfer, immediate data transfer, transfer supporting module data transfer, structure data transfer MOVA Effective address transfer...
Page 67 Table 2.10 Classification of Instructions (cont) Classifi- Operation Number of cation Types Code Function Instructions Logic oper- 6 Logical AND and T bit set ations Exclusive OR (cont) Shift ROTL One-bit left rotation ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAL...
Page 68 The following tables (arranged by instruction classification) show instruction codes, operations, and execution states, using the format shown below. Table 2.11 Instruction Code Format Item Format Explanation Instruction OP: Operation code OP.Sz SRC,DEST mnemonic Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data...
Page 69 Table 2.12 Data Transfer Instructions Execu- tion Instruction Instruction Code Operation Cycles T Bit #imm → Sign extension → — #imm,Rn 1110nnnniiiiiiii (disp × 2 + PC) → Sign — MOV.W @(disp,PC),Rn 1001nnnndddddddd extension → Rn (disp × 4 + PC) → Rn —...
Page 70 Table 2.12 Data Transfer Instructions (cont) Execu- tion Instruction Instruction Code Operation Cycles T Bit Rm → (R0 + Rn) — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 (R0 + Rm) → Sign — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 extension → Rn (R0 + Rm) → Sign —...
Page 71 Table 2.13 Arithmetic Instructions Execution Instruction Instruction Code Operation Cycles T Bit Rn + Rm → Rn — Rm,Rn 0011nnnnmmmm1100 Rn + imm → Rn — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, Carry ADDC Rm,Rn 0011nnnnmmmm1110 Carry → T Rn + Rm →...
Page 72 Table 2.13 Arithmetic Instructions (cont) Execution Instruction Instruction Code Operation Cycles T Bit A word in Rm is sign- — EXTS.W Rm,Rn 0110nnnnmmmm1111 extended → Rn A byte in Rm is zero- — EXTU.B Rm,Rn 0110nnnnmmmm1100 extended → Rn A word in Rm is zero- —...
Page 73 Table 2.14 Logic Operation Instructions Execution Instruction Instruction Code Operation Cycles T Bit Rn & Rm → Rn — Rm,Rn 0010nnnnmmmm1001 R0 & imm → R0 — #imm,R0 11001001iiiiiiii (R0 + GBR) & imm — AND.B #imm,@(R0,GBR) 11001101iiiiiiii → (R0 + GBR) ~Rm →...
Page 74 Table 2.15 Shift Instructions Instruction Instruction Code Operation Execution Cycles T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 LSB → Rn → T ROTR 0100nnnn00000101 T ← Rn ← T ROTCL 0100nnnn00100100 T → Rn → T ROTCR 0100nnnn00100101 T ←...
Page 75 Table 2.17 System Control Instructions Execution Instruction Instruction Code Operation Cycles T Bit 0 → T CLRT 0000000000001000 0 → MACH, MACL — CLRMAC 0000000000101000 Rm → SR Rm,SR 0100mmmm00001110 Rm → GBR — Rm,GBR 0100mmmm00011110 Rm → VBR — Rm,VBR 0100mmmm00101110 (Rm) →...
Page 76 Table 2.17 System Control Instructions (cont) Execution Instruction Instruction Code Operation Cycles T Bit MACL → Rn — MACL,Rn 0000nnnn00011010 PR → Rn — PR,Rn 0000nnnn00101010 Rn–4 → Rn, MACH → (Rn) — STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACL → (Rn) —...
Page 77: Operation Code Map
2.4.2 Operation Code Map Table 2.18 shows an operation code map. Table 2.18 Operation Code Map Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011–1111 MD: 00 MD: 01 MD: 10 MD: 11 0000 0000 0000 0001 0000 0010 SR,Rn GBR,Rn VBR,Rn...
Page 78 Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011–1111 MD: 00 MD: 01 MD: 10 MD: 11 0100 Rn 0011 STC.L STC.L| STC.L SR,@–Rn GBR,@–Rn VBR,@–Rn 0100 Rn 0100 ROTL ROTCL Rn 0100 Rn 0101 ROTR CMP/PL Rn...
Page 79 Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011–1111 MD: 00 MD: 01 MD: 10 MD: 11 1100 00MD imm/disp MOV.B R0,@ MOV.W R0,@ MOV.L R0,@ TRAPA #imm:8 (disp:8,GBR) (disp:8,GBR) (disp:8,GBR) 1100 01MD disp MOV.B MOV.W...
Page 80: Cpu State
CPU State 2.5.1 State Transitions The CPU has five processing states: reset, exception handling, bus-released, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception handling states, see section 4, Exception Handling. For details on the power-down state, see section 19, Power-Down State.
Page 81 From any state when From any state when RES = 0 and NMI = 1 RES = 0 and NMI = 0 RES = 0, NMI = 0 Power-on reset state Manual reset state RES = 0, NMI = 1 Reset states RES = 1, RES = 1,...
Page 82 Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. When turning on the power, be sure to carry out a power-on reset.
Page 83: Power-Down State
2.5.2 Power-Down State In addition to the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts and power consumption is reduced There are two power-down state modes: sleep mode and standby mode. Sleep Mode: When the standby bit SBY (in the standby control register, SBYCR) is cleared to 0 and a SLEEP instruction is executed, the CPU switches from program execution state to sleep mode.
Page 84: Section 3 Operating Modes
Types of Operating Modes and Their Selection The SH7032 microcomputer operates in one of two operating modes (modes 0 and 1) and the SH7034 operates in one of four operating modes (modes 0, 1, 2, and 7). Modes 0 and 1 differ in the bus width of memory area 0.
Page 86: Section 4 Exception Handling
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priorities As figure 4.1 indicates, exception handling may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two or more exceptions occur simultaneously, they are accepted and handled in the priority order shown.
Page 87 Priority High • Power-on reset Reset • Manual reset • CPU address error Address error • DMA address error • NMI • User break • IRQ • IRQ0–IRQ7 Interrupt • Direct memory access controller Exception • 16-bit integrated timer source pulse unit •...
Page 88: Exception Handling Operation
4.1.2 Exception Handling Operation Exception sources are detected at the times indicated in table 4.1, whereupon handling starts. Table 4.1 Exception Source Detection and Start of Handling Exception Type Source Detection and Start of Handling Low-to-high transition at RES pin when NMI is high Reset Power-on Low-to-high transition at RES pin when NMI is low...
Page 89: Exception Vector Table
4.1.3 Exception Vector Table Before exception handling can execute, the exception vector table must be set in memory. The exception vector table holds the start addresses of exception handling routines (the table for reset exception handling stores initial PC and SP values). Different vector numbers and vector table address offsets are assigned to different exception sources.
Page 90 Table 4.2 Exception Vector Table Vector Exception Source Number Vector table Address Offset Power-on reset H'00000000–H'00000003 H'00000004–H'00000007 Manual reset H'00000008–H'0000000B H'0000000C–H'0000000F General illegal instruction H'00000010–H'00000013 (Reserved for system use) H'00000014–H'00000017 Illegal slot instruction H'00000018–H'0000001B (Reserved for system use) H'0000001C–H'0000001F H'00000020–H'00000023 CPU address error H'00000024–H'00000027 DMA address error...
Page 91: Resets
Table 4.3 Calculation of Exception Vector Table Addresses Exception Source Calculation of Vector Table Address Reset (Vector table address) = (vector table address offset) = (vector number) × 4 Address error, interrupt, instructions (Vector table address) = VBR + (vector table address offset) = VBR + (vector number) ×...
Page 92: Power-On Reset
4.2.2 Power-On Reset When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state. The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or while the CPG is operating during the oscillation settling time) for at least 20 t to assure that the chip is reset.
Page 93: Address Errors
Address Errors 4.3.1 Address Error Sources Address errors occur during instruction fetches and data reading/writing as shown in table 4.5. Table 4.5 Address Error Sources Bus Cycle Type Bus Master Operation Address Error Instruction fetch Instruction fetch from even address None (normal) Instruction fetch from odd address Address error...
Page 94: Interrupts
Interrupts 4.4.1 Interrupt Sources Table 4.6 lists the types of interrupt exception handling sources (NMI, user break, IRQ, on-chip supporting module). Table 4.6 Interrupt Sources Interrupt Requesting Pin or Module Number of Sources NMI pin (external input) User break User break controller IRQ0–IRQ7 pin (external input) On-chip supporting Direct Memory Access Controller...
Page 95: Interrupt Exception Handling
Table 4.7 Interrupt Priority Rankings Type Priority Comments Fixed and unmaskable User break Fixed IRQ and on-chip supporting 0–15 Set in interrupt priority level registers A–E modules (IPRA–IPRE) 4.4.3 Interrupt Exception Handling When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the interrupt mask bits (I3–I0) of SR.
Page 96: Instruction Exceptions
Instruction Exceptions 4.5.1 Types of Instruction Exceptions Table 4.8 shows the three types of instruction that start exception handling (trap instructions, illegal slot instructions, and general illegal instructions). Table 4.8 Types of Instruction Exceptions Type Source Instruction Comments Trap instruction TRAPA —...
Page 97: Illegal Slot Instruction
4.5.3 Illegal Slot Instruction An instruction located immediately after a delayed branch instruction is called an “instruction placed in a delay slot.” If an undefined instruction is located in a delay slot, illegal slot instruction exception handling begins executing when the undefined code is decoded. Illegal slot instruction exception handling also begins when the instruction located in the delay slot is an instruction that rewrites the program counter.
Page 98: Cases In Which Exceptions Are Not Accepted
Cases in which Exceptions are Not Accepted In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is accepted when an instruction that can accept the exception is decoded. Table 4.9 Cases in which Exceptions are Not Accepted Exception Source...
Page 99: Stack Status After Exception Handling
Stack Status after Exception Handling Table 4.10 shows the stack after exception handling. Table 4.10 Stack after Exception Handling Type Stack Status Type Stack Status Address Interrupt Address of Address of error instruction instruction Upper 16 bits Upper 16 bits after instruc- after instruc- tion that has...
Page 100: Notes
Notes 4.8.1 Value of the Stack Pointer (SP) An address error occurs if the stack is accessed for exception handling when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four should always be stored in the 4.8.2 Value of the Vector Base Register (VBR) An address error occurs if the vector table is accessed for exception handling when the value of...
Page 102: Interrupt Controller (Intc)
Section 5 Interrupt Controller (INTC) Overview The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according to user-specified priorities. 5.1.1 Features The interrupt controller has the following features:...
Page 103 IRQOUT IRQ0 IRQ1 Input IRQ2 control IRQ3 Priority decision IRQ4 Com- logic IRQ5 Interrupt request parator IRQ6 IRQ7 (Interrupt request) (Interrupt request) DMAC (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) IPRA–IPRE Module bus interface INTC UBC: User break controller WDT: Watchdog timer DMAC: Direct memory access controller...
Page 104: Pin Configuration
5.1.3 Pin Configuration INTC pins are summarized in table 5.1. Table 5.1 INTC Pin Configuration Name Abbr. Function Nonmaskable interrupt input pin NMI Inputs a non-maskable interrupt request signal. IRQ0– Interrupt request input pins Inputs maskable interrupt request signals. IRQ7 IRQOUT Interrupt request output pin Outputs a signal indicating an interrupt...
Page 105: Interrupt Sources
Interrupt Sources There are four types of interrupt sources: NMI, user break, IRQ, and on-chip supporting module interrupts. Interrupt rankings are expressed as priority levels (0–16), with 0 the lowest and 16 the highest. An interrupt set to level 0 is masked. 5.2.1 NMI Interrupts NMI is the highest-priority interrupt (level 16) and is always accepted.
Page 106: On-Chip Interrupts
5.2.4 On-Chip Interrupts On-chip interrupts are interrupts generated by the following 6 on-chip supporting modules: • Direct memory access controller (DMAC) • 16-bit integrated timer pulse unit (ITU) • Serial communication interface (SCI) • Bus state controller (BSC) • A/D converter (A/D) •...
Page 107 Table 5.3 Interrupt Exception Vectors and Rankings Interrupt Pri- Priority Vec- Default ority Order IPR (Bit Within Address Offset in Priority Interrupt Source (Initial Value) Numbers) Module Vector Table Order — — H'0000002C–H'0000002F High User break — — H'00000030–H'00000033 IRQ0 0–15 (0) IPRA (15–12) —...
Page 108 Table 5.3 Interrupt Exception Vectors and Rankings (cont) Interrupt Pri- Priority Vec- Default ority Order IPR (Bit Within Address Offset in Priority Interrupt Source (Initial Value) Numbers) Module Vector Table Order ITU3 IMIA3 0–15 (0) IPRD (11–8) 3 H'00000170–H'00000173 IMIB3 H'00000174–H'00000177 OVI3 H'00000178–H'0000017B...
Page 109: Register Descriptions
Register Descriptions 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) The five registers IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15 to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources are mapped onto IPRA–IPRE as shown in table 5.4. Bit: Bit name: Initial value:...
Page 110: Interrupt Control Register (Icr)
5.3.2 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input detection mode of external interrupt input pins NMI and IRQ0–IRQ7, and indicates the input signal level at the NMI pin. A reset initializes ICR but standby mode does not. Bit: Bit name: NMIL...
Page 111: Interrupt Operation
Interrupt Operation 5.4.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 5.2 shows a flowchart of the operations up to acceptance of the interrupt. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2.
Page 112 Program execution state Interrupt? NMI? User break? Level 15 interrupt? IRQOUT low Level 14 interrupt? Push SR onto stack I3 to I0 ≤ level 14? Level 1 Push PC onto stack interrupt? I3 to I0 ≤ Copy level of accep- level 13? tance from I3 to I0 I3 to I0 =...
Page 113: Stack After Interrupt Exception Handling
5.4.2 Stack after Interrupt Exception Handling Figure 5.3 shows the stack after interrupt exception handling. Address Upper 16 bits 4n–8 Lower 16 bits 4n–6 Upper 16 bits 4n–4 4n–2 Lower 16 bits Notes: Bus width is 16 bits. *1 PC stores the start address of the next instruction (return instruction) after the executed instruction.
Page 114: Interrupt Response Time
Interrupt Response Time Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is accepted. Table 5.5 Interrupt Response Time Number of States...
Page 115: Usage Notes
Interrupt accepted 5 + m1 + m2 + m3 m1 m2 1 m3 1 Instruction (instruction replaced by M M E M E E interrupt exception handling) Overrun fetch Interrupt service routine— F D E first instruction (edge) IRQOUT (level) When m1 = m2 = m3, the interrupt response time is 11 cycles.
Page 116: User Break Controller (Ubc)
Section 6 User Break Controller (UBC) Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to the contents of a CPU or DMAC bus cycle.
Page 117: Block Diagram
6.1.2 Block Diagram Figure 6.1 shows a block diagram of the user break controller. Module bus interface BAMRH BARH BAMRL BARL Break condition comparator User break Interrupt request interrupt generating circuit Interrupt controller BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address mask registers H and L BBR: Break bus cycle register Figure 6.1 Block Diagram of User Break Controller...
Page 118: Register Configuration
6.1.3 Register Configuration The user break controller has five registers as listed in table 6.1. These registers are used for setting break conditions. Table 6.1 User Break Controller Registers Initial Address * Name Abbr. Value Bus width Break address register high BARH H'5FFFF90 H'0000...
Page 119: Register Descriptions
Register Descriptions 6.2.1 Break Address Registers (BAR) There are two break address registers—break address register H (BARH) and break address register L (BARL)—that together form a single group. Both are 16-bit read/write registers. BARH stores the upper bits (bits 31–16) of the address of the break condition. BARL stores the lower bits (bits 15–0) of the address of the break condition.
Page 120: Break Address Mask Register (Bamr)
6.2.2 Break Address Mask Register (BAMR) The two break address mask registers—break address mask register H (BAMRH) and break address mask register L (BARML)—together form a single group. Both are 16-bit read/write registers. BAMRH determines which of the bits in the break address set in BARH are masked. BAMRL determines which of the bits in the break address set in BARL are masked.
Page 121: Break Bus Cycle Register (Bbr)
6.2.3 Break Bus Cycle Register (BBR) The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four break conditions: • CPU cycle or DMA cycle • Instruction fetch or data access • Read or write •...
Page 122 • Bits 5 and 4 (Instruction Fetch/Data Access Select (ID1, ID0)): ID1 and ID0 select whether to break on instruction fetch and/or data access bus cycles. Bit 5: ID1 Bit 4: ID0 Description No break interrupt occurs (Initial value) Break only on instruction fetch cycles Break only on data access cycles Break on both instruction fetch and data access cycles •...
Page 123: Operation
Operation 6.3.1 Flow of User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below. 1. Break conditions are set in the break address register (BAR), break address mask register (BAMR), and break bus cycle register (BBR). Set the break address in BAR, the address bits to be masked in BAMR and the type of break bus cycle in BBR.
Page 124 BARH/BARL BAMRH/BAMRL Internal address bits 31–0 CPU cycle DMA cycle Instruction fetch User break interrupt Data access Read cycle Write cycle Byte size Word size Longword size Figure 6.2 Break Condition Logic...
Page 125: Break On Instruction Fetch Cycles To On-Chip Memory
6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory On-chip memory (on-chip ROM (SH7034 only) and RAM) is always accessed 32 bits each bus cycle. Two instructions are therefore fetched in a bus cycle from on-chip memory . Although only a single bus cycle occurs for the two-instruction fetch, a break can be set on either instruction by placing the corresponding address in the break address registers (BAR).
Page 126: Setting User Break Conditions
Setting User Break Conditions CPU Instruction Fetch Bus Cycle: • Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054 Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size not included in conditions) A user break interrupt will occur immediately before the instruction at address H'00000404. If the instruction at address H'00000402 can accept an interrupt, the user break exception handling will be executed after that instruction is executed.
Page 127: Notes
Notes 6.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched.
Page 128: Instruction Fetch Break
If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after the interrupt B exception handling. (1) Cause The SH7032/SH7034 chip operates as follows. Interrupt B accepted UBC interrupt accepted Interrupt exception...
Page 130: Clock Pulse Generator (Cpg)
Section 7 Clock Pulse Generator (CPG) Overview The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the chip and external devices with a clock pulse. The CPG makes the chip run at the oscillation frequency of the crystal resonator. The CPG consists of an oscillator and a duty cycle correction circuit (figure 7.1).
Page 131 EXTAL =10–22 pF XTAL Figure 7.2 Connection of Crystal Resonator (Example) Table 7.1 Damping Resistance Frequency [MHz] Rd [Ω] Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 7.2. XTAL EXTAL Figure 7.3 Crystal Resonator Equivalent Circuit...
Page 132: External Clock Input
7.2.2 External Clock Input An external clock signal can be input at the EXTAL pin as shown in figure 7.4. The XTAL pin should be left open. The frequency must be equal to the system clock (CK) frequency. The specifications for the waveform of the external clock input are given below. Make the external clock frequency the same as the system clock (CK).
Page 133: Usage Notes
Usage Notes Board Design: When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Route no other signal lines near the XTAL and EXTAL pin signal lines to prevent induction from interfering with correct oscillation. See figure 7.6.
Page 134 Input duty * (MHz) Input frequency Note: * With the SH7034B, compensation is performed in the input duty range of 60% to 40%. Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics...
Page 136: Bus State Controller (Bsc)
Section 8 Bus State Controller (BSC) Overview The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM, SRAM, ROM, and peripheral chips without the use of external circuits, simplifying system design and allowing high-speed data transfer in a compact system.
Page 137: Block Diagram
8.1.2 Block Diagram Figure 8.1 shows a block diagram of the bus state controller. interface WCR1 Wait control WAIT WCR2 unit WCR3 WRH, WRL Area control HBS, LBS unit CS7 to CS0 CASH, CASL DRAM control RTCSR unit CMI interrupt request RTCNT Comparator DPH, DPL...
Page 138: Pin Configuration
8.1.3 Pin Configuration Table 8.1 shows the BSC pin configuration. Table 8.1 Pin Configuration Name Abbreviation Function CS7–CS0 Chip select 7–0 Chip select signal that indicates the area being accessed Read Strobe signal that indicates the read cycle High write Strobe signal that indicates write cycle to upper 8 bits Low write...
Page 139: Register Configuration
8.1.4 Register Configuration The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM interface, and parity check. Table 8.2 Register Configuration Address * Name Abbr. Initial Value Bus width Bus control register H'0000 H'5FFFFA0 8,16,32 Wait state control register 1 WCR1...
Page 140: Overview Of Areas
Area 0 can be used as an on-chip ROM space or external memory space in the SH7034. In the SH7032, it can only be used as external memory space. Area 1 can be used as DRAM space or external memory space. DRAM space enables direct connection to DRAM and outputs RAS, CAS and multiplexed addresses.
Page 141 For details, see the sections on the individual modules.) *6 Divided into 8-bit space and 16-bit space by value of address bit A14 *7 Select with IOE bit in BCR *8 For SH7032 *9 For SH7034...
Page 142: Register Descriptions
Register Descriptions 8.2.1 Bus Control Register (BCR) The bus control register (BCR) is a 16-bit read/write register that selects the functions of areas and status of bus cycles. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 143 • Bit 13 (Warp Mode Bit (WARP)): WARP selects warp or normal mode. 0 sets normal mode and 1 sets warp mode. In warp mode, some external accesses are carried out in parallel with internal access. Bit 13: WARP Description Normal mode: External and internal accesses are not performed simultaneously (Initial value)
Page 144: Wait State Control Register 1 (Wcr1)
8.2.2 Wait State Control Register 1 (WCR1) Wait state control register 1 is a 16-bit read/write register that controls the number of states for accessing each area and whether wait states are used. WCR1 is initialized to H'FFFF by a power- on reset.
Page 145 Table 8.4 summarizes read cycle state information. Table 8.4 Read Cycle States Read Cycle States External Memory Space Internal Space WAIT Pin Multi- On-Chip On-Chip Bits 15–8: Input External Memory plexed Supporting ROM and RW7–RW0 Signal Space DRAM Space Modules Areas 1, 3–5,7: 1 Column add- 4 states...
Page 146: Wait State Control Register 2 (Wcr2)
8.2.3 Wait State Control Register 2 (WCR2) Wait state control register 2 is a 16-bit read/write register that controls the number of states for accessing each area with a DMA single address mode transfer and whether wait states are used. WCR2 is initialized to H'FFFF by a power-on reset.
Page 147 Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space) Single-Mode DMA Memory Read Cycle States (External Memory Space) WAIT Pin Input Bits 15–8: Multiplexed DRW7–DRW0 Signal External Memory Space DRAM Space Not sampled during Areas 1, 3–5,7: 1 state, Column address 4 states + single-mode DMA...
Page 148: Wait State Control Register 3 (Wcr3)
Table 8.6 Single-Mode DMA Memory Write Cycle States (External Memory Space) Single-Mode DMA Memory Write Cycle States (External Memory Space) WAIT Pin Input Bits 15–8: External Memory Multiplexed DWW7–DWW0 Signal Space DRAM Space Not sampled during Areas 1, 3–5,7: 1 state, Column address 4 states + single-mode DMA...
Page 149: Dram Area Control Register (Dcr)
• Bits 14 and 13 (Long Wait Insertion in Areas 0 and 2, Bits 1, 0 (A02LW1 and A02LW0)): A02LW1 and A02LW0 select the long wait states to be inserted (1–4 states) when accessing external memory space of areas 0 and 2. Bit 14: A02LW1 Bit 13: A02LW0 Description...
Page 150 Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — — • Bit 15 (Dual-CAS or Dual-WE Select Bit (CW2)): When accessing a 16-bit bus width space, CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and WRL signals are valid ;...
Page 151 Bit 12: BE Description Normal mode: full access (Initial value) Burst operation: high-speed page mode • Bit 11 (CAS Duty (CDTY)): CDTY selects 35% or 50% of the TC state as the high-level duty ratio of the signal CAS in short-pitch access. When cleared to 0, the CAS signal high level duty is 50%;...
Page 152: Refresh Control Register (Rcr)
8.2.6 Refresh Control Register (RCR) The refresh control register (RCR) is a 16-bit read/write register that controls the start of refresh- ing and selects the refresh mode and the number of wait states during refreshing. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RCR from being written incorrectly, it must be written by a different method from most other registers.
Page 153: Refresh Timer Control/Status Register (Rtcsr)
Bit 6: RMODE Description CAS-before-RAS refresh (Initial value) Self-refresh • Bits 5 and 4—CBR Refresh Wait State Insertion Bits 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted (1–4) during CAS-before-RAS refreshing. When CBR refresh is performed and the RW1 bit in WCR1 is set to 1, the number of wait states selected by RLW1 and RLW0 is inserted regardless of the WAIT signal.
Page 154 • Bits 15–8 (Reserved): These bits are always read as 0. • Bit 7 (Compare Match Flag (CMF)): Indicates whether the values of RTCNT and the refresh time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not match;...
Page 155: Refresh Timer Counter (Rtcnt)
8.2.8 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is a 16-bit read/write register that is used as an 8-bit upcounter that generates refresh or interrupt requests. When the input clock is selected by clock select bits 2– 0 (CKS2–CKS0) in RTCSR, that clock makes the RTCNT start incrementing. When the values of RTCNT and the refresh time constant register (RTCOR) match, RTCNT is cleared to H'0000 and the CMF flag in RTCSR is set to 1.
Page 156: Parity Control Register (Pcr)
RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RTCOR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'96 is written in the upper byte, and the actual data is written in the lower byte.
Page 157 • Bit 15 (Parity Error Flag (PEF)): When a parity check is carried out, PEF indicates whether a parity error has occurred. 0 indicates that no parity error has occurred; 1 indicates that a parity error has occurred. Bit 15: PEF Description No parity error (Initial value)
Page 158: Notes On Register Access
8.2.11 Notes on Register Access RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write. Data requires a password when it is written. This prevents data from being mistakenly overwritten by program overruns and so on. Writing to RCR, RTCSR, RTCNT, and RTCOR: Use only word transfer instructions.
Page 159: Address Space Subdivision
Address Space Subdivision 8.3.1 Address Spaces and Areas Figure 8.3 shows the address format used in this chip. 4-Gbyte space 128-Mbyte space 16-Mbyte space 4-Mbyte space A31–A28 A27 A26–A24 A23,A22 Output address: Output from address pins A21–A0 Ignored: Only valid when the address multiplex function is being used in the DRAM space (area 1);...
Page 160 For details, see the sections on the individual modules.) *6 Divided into 8-bit space and 16-bit space by value of address bit A14 *7 Select with IOE bit in BCR *8 For SH7032 *9 For SH7034...
Page 161: Bus Width
As figure 8.4 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral chips will be output by the chip to devices connected to an area allocated to the appropriate type of space.
Page 162: Shadows
Table 8.8 A26–A24 Bits and Chip Select Signals Address Area Selected Chip Select Pin Driven Low Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 The chip select signal is output only for external accesses. When accessing the on-chip ROM (area 0), on-chip supporting modules (area 5), and on-chip RAM (area 7), the CS0, CS5, and CS7 pins are not driven low.
Page 163 Logical address space H'B000000 H'3000000 Shadow H'B3FFFFF (A23, A22 = 00) H'B400000 H'33FFFFF H'3400000 Actual space Shadow H'B7FFFFF (A23, A22 = 01) H'B800000 Area H'37FFFFF accessible 4 Mbytes H'3800000 with A21–A0 H'BBFFFFF Shadow (A23, A22 = 10) H'BC00000 H'3BFFFFF H'3C00000 Shadow H'BFFFFFF (A23, A22 = 11)
Page 164: Area Descriptions
0 is a 16-bit external memory space; and when they are 010, it is a 32-bit on-chip ROM space. In the SH7032, area 0 can only be used as external memory space since there is no on-chip ROM, and this last setting is meaningless.
Page 165 Logical address space Logical address space H'8000000 H'8000000 H'800FFFF H'0000000 H'8010000 H'0000000 Shadow H'000FFFF Shadow H'0010000 Shadow H'83FFFFF Shadow H'8400000 H'03FFFFF H'0400000 Actual space Shadow H'87FFFFF Actual space H'8800000 External On-chip ROM H'07FFFFF memory H'0800000 (64 kbytes) space (4 Mbytes) •...
Page 166 DRAM control register (DCR) is set to 1 to use the address multiplex function, bits A23–A0 are multiplexed and output from pins A15–A0, so a maximum 16-Mbyte space can be used. When DRAM space is accessed, the CS1 signal is not valid and the pin function controller should be set for access with CAS (CASH and CASL) and RAS signals.
Page 167 Areas 2–4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1. A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When areas 2–4 are accessed, the CS2, CS3, and CS4 signals are valid.
Page 168 Area 5: Area 5 is an area with address bits A26–A24 set to 101 and an address range of H'5000000–H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8.8 shows a memory map of area 5. Area 5 is allocated to on-chip supporting module space when the A27 address bit is 0 and external memory space when A27 is 1.
Page 169 Area 6: Area 6 is an area with address bits A26–A24 set to 110 and an address range of H'6000000–H'6FFFFFF and H'E000000–H'EFFFFFF. Figure 8.9 shows a memory map of area 6. In area 6, a space for which address bit A27 is 0 is allocated to address/data multiplexed I/O space when the multiplexed I/O enable bit (IOE) of the bus control register (BCR) is 1, and to external memory space when the IOE bit is 0.
Page 170 4-Mbyte units. When external memory is accessed, the CS7 signal is valid. The on-chip RAM space has a bus width of 32 bits. In the SH7032, the on-chip RAM capacity is 8 kbytes, so A23–A13 are ignored and the shadows are in 8-kbyte units. In the SH7034, the on-chip RAM capacity is 4 kbytes, so A23–A12 are ignored and the shadows are in 4-kbyte units.
Page 171: Accessing External Memory Space
Accessing External Memory Space In external memory space, a strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: • Area 0 (when MD2–MD0 are 000 or 001) •...
Page 172 A21–A0 When RDDTY = 0 When RDDTY = 1 Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR.
Page 173: Wait State Control
8.4.2 Wait State Control The number of external memory space access states and the insertion of wait states can be controlled using the WCR1–WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC dual mode read cycle. The bus cycle that can be controlled using the WCR2 is the DMAC single-mode read/write cycle.
Page 174 Tw (wait state) A21–A0 Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.13 Wait State Timing for External Memory Space Access (2 States Plus Wait States from WAIT Signal) Areas 0, 2, and 6 have long wait functions. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the access cycle is 1 state plus the number of long wait states (set in WCR3, selectable between 1 and 4) and the WAIT pin input signal is not sampled.
Page 175 Wait state Wait from WAIT Wait states states set set in WCR3 signal input in WCR3 A21–A0 Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.14 Wait State Timing for External Memory Space Access (1 State Plus Long Wait State (When Set to Insert 3 States) Plus Wait States from WAIT Signal) For CPU write cycles and DMAC dual mode write cycles to external memory space, the number of states and wait state insertion cannot be controlled by WCR1.
Page 176: Byte Access Control
8.4.3 Byte Access Control The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) in BCR is set to 1, the WRH, WRL, and A0 pins output WR, LBS, and HBS signals. Figure 8.15 illustrates the control signal output timing in the byte write cycle.
Page 177: Dram Interface Operation
DRAM Interface Operation When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this chip to DRAMs. 8.5.1 DRAM Address Multiplexing When the multiplex enable bit (MXE) in the DRAM area control register (DCR) is set to 1, row addresses and column addresses are multiplexed.
Page 178 Table 8.10 Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing 8-Bit Shift 9-Bit Shift 10-Bit Shift Output Output Output Output Output Output Column Column Column Output Pin Address Address Address Address Address Address Undefined Undefined Undefined Value Value Value Note: The MXC1=1, MX0=1 setting is reserved, and must not be used.
Page 179: Basic Timing
For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23–A8 address bit values are output to pins A15–A0 the row address. The values for A21–A16 are undefined. The values of bits address A21–A0 are output to pins A21–A0 as the column address. Figure 8.16 depicts address multiplexing with an 8-bit shift.
Page 180 Row address Column address A21–A0 CDTY CDTY WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.17 Short Pitch Access Timing...
Page 181: Wait State Control
Row address Column address A21–A0 WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may not always be sufficient for the precharge time for the RAS signal when the DRAM is accessed.
Page 182 Row address Column address A21–A0 Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends in 1 state and no wait states are inserted.
Page 183: Byte Access Control
8.5.4 Byte Access Control 16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By setting the dual CAS signals/dual WE signals select bit (CW2) in DCR, the BSC allows selection of either the dual CAS signal or dual WE signal system of control signals. When 16-bit space is being accessed and the CW2 bit is cleared to 0 for dual CAS signals, CASH, CASL, and WRL signals are output;...
Page 184 Row address Column address A21–A0 CASH Byte control CASL High Fixed high (a) Dual CAS signals (CW2 = 0) Row address Column address A21–A0 CASH Fixed high CASL Byte control High (b) Dual WE signals (CW2 = 1) Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Pitch)
Page 185: Dram Burst Mode
8.5.5 DRAM Burst Mode In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously accessing the same row. The high speed page mode enables fast access of data simply by changing the column address after the row address is output (burst mode).
Page 186 Short-Pitch, High-Speed Page Mode and Long-Pitch High-Speed Page Mode: When burst operation is selected by setting the BE bit to 1 in DCR, short pitch high-speed page mode or long pitch high-speed page mode can be selected by setting the RW1, WW1, DRW1, and DWW1 bits in WCR1 and WCR2.
Page 187 Access A Access B Silent cycle Column Column Column Column address A-1 address A-2 address B-1 address B-2 A21– Row address AD15– Data A-1 Data A-2 Data B-1 Data B-2 Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces.
Page 188 The high-level duty of the CAS signal can be selected in short-pitch, high-speed page mode using the CAS duty bit (CDTY) in DCR. When the CDTY bit is cleared to 0, the high-level duty is 50% of the T state; when CDTY is set to 1, it is 35% of the T state.
Page 189 RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal low while this other access is occurring allows burst operation to continue the next time the same row of the DRAM is accessed.
Page 190: Refresh Control
• RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a DRAM access pauses for access to another space. Burst operation continues only while DRAM access is continuous. Figure 8.28 shows the timing when an external memory space access occurs during burst operation in RAS up mode.
Page 191 When the clock is selected with the CKS2–CKS0 bits, RTCNT immediately begins to increment from its current value. This means that when the RTCOR cycle is set after the CKS2–CKS0 bits are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow once (from H'FF to H'00) and incrementing will start again.
Page 192 Self-Refresh Mode: Some DRAMs have a self-refresh mode (battery back-up mode). This is a type of a standby mode in which the refresh timing and refresh addresses are generated inside the DRAM chip. When the RFSHE and RMODE bits in RCR are both set to 1, the DRAM will enter self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31.
Page 193 Table 8.11 Refresh and Bus Cycle Contention Type of Bus Cycle External Space Access External Memory Space, Multiplexed I/O Space DRAM Space On-Chip ROM, On-Chip Type of Read Write Read Write RAM, On-Chip Supporting Refresh Cycle Cycle Cycle Cycle Module Access CAS-before- RAS refresh Self-refresh...
Page 194: Address/Data Multiplexed I/O Space Access
Address/Data Multiplexed I/O Space Access The BSC is equipped with a function that multiplexes address and data input/output on pins AD15–AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral chips that require address/data multiplexing. 8.6.1 Basic Timing When the multiplexed I/O enable bit (IOE) in BCR is set to 1, the area 6 space with address bit...
Page 195: Wait State Control
A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or T w state, lengthening the access time for external devices. 8.6.2 Wait State Control When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled...
Page 196: Parity Check And Generation
memory space access. These types can be selected using the BAS bit in BCR. See section 8.4.3, Byte Access Control, for details. Parity Check and Generation The BSC can check and generate parity for data input and output to or from the DRAM space of area 1 and the external memory space of area 2.
Page 197: Warp Mode
Warp Mode In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently and in parallel. Warp mode is entered by setting the warp mode bit (WARP) in BCR to 1. This allows the chip to be operated at high speed.
Page 198: Wait State Control
External space writing On-chip peripheral module read/write A21– External space address External space write AD15– Write data External space address On-chip supporting module address Internal address Internal On-chip write supporting strobe module write Internal Write data data bus Internal On-chip read supporting strobe...
Page 199 Table 8.12 Bus Cycle States when Accessing Address Spaces CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single Mode Memory Read/Write Cycle Corresponding Bits in Corresponding Bits in Address Space WCR1 and WCR2 = 0 WCR1 and WCR2 = 1 External memory (areas 1, 3–5, 7) 1 state fixed;...
Page 200 Accesses to on-chip spaces are as follows: On-chip supporting module spaces (area 5 when address bit A27 is 1) are always 3-state access spaces, regardless of WCR, with no WAIT signal sampling. Accesses to on-chip ROM (area 0 when MD2–MD0 are 010) and on-chip RAM (area 7 when address bit A27 is 0) are always performed in 1 state, regardless of WCR, with no WAIT signal sampling.
Page 201: Bus Arbitration
8.10 Bus Arbitration The SuperH microcomputer can release the bus to external devices when they request the bus. It has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these two are as follows. Bus request from external device >...
Page 202: Operation Of Bus Arbitration
8.10.1 Operation of Bus Arbitration If there is conflict between bus arbitration and refreshing, the operation is as follows. 1. If DRAM refreshing is requested in this chip when the bus is released and BACK is low, BACK goes high and the occurrence of the refresh request can be indicated externally. At this time, the external device may generate a bus cycle when BREQ is low even if BACK is high.
Page 203: Back Operation
If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level. BREQ BACK BACK does not go low. Refresh request Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release. Figure 8.37 BACK Operation in Response to Refresh Request (2) 3.
Page 204: Usage Notes
Note that delay of the BACK signal increases in units of approximately 0.1 ns/pF. (When a capacitance of 220 pF is added, the delay increases by approximately 22 ns.) BACK SuperH Microcomputer Circuit with capacitor for eliminating spikes c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may or may not be successful due to the narrow pulse width of the spike.
Page 205 Corresponding DRAM conditions: Long-pitch/normal mode Long-pitch/high-speed page mode There are no problems regarding operations except for the above conditions. There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines).
Page 206 RES latch timing Manual reset A0–A21 Row address Column address FFFF Figure 8.40 Long-Pitch Mode Read (1) RES latch timing Manual reset A0–A21 Row address FFFF Figure 8.41 Long-Pitch Mode Read (2) For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM data must be held after a reset, take one of the measures described below.
Page 207: Usage Notes On Parity Data Pins Dph And Dpl
8.11.2 Usage Notes on Parity Data Pins DPH and DPL The following specifies the setup time, t , of parity data DPH and DPL with respect to the fall of the CAS signal when parity data DPH and DPL are written to DRAM in long-pitch mode (early write).
Page 208 The maximum number of states from BREQ input to bus release are used when B is a cycle comprising the maximum number of states for which the bus is not released; the number of states is the maximum number of states for which bus is not released + approx. 4.5 states. The maximum number of states for which the bus is not released requires careful investigation.
Page 209 The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032 and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next).
Page 210: Direct Memory Access Controller (Dmac)
Section 9 Direct Memory Access Controller (DMAC) Overview The SuperH microcomputer chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, on-chip memory, and on-chip supporting modules (excluding the DMAC itself).
Page 211: Block Diagram
• Transfer requests  External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level)  Requests from on-chip supporting modules (serial communication interface (SCI), A/D converter (A/D), and 16-bit integrated timer pulse unit (ITU)) ...
Page 212 On-chip SARn On-chip DARn On-chip TCRn Iteration supporting control module Register control CHCRn DREQ0, DREQ1 Start-up control DMAOR A/D converter Request priority DACK0, DACK1 control DEIn External External External device (memory- mapped) Bus interface External device (with DMAC acknowledge) Bus controller DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination address register...
Page 213: Pin Configuration
9.1.3 Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Channel Name Symbol Function DREQ0 DMA transfer request DMA transfer request input from external device to channel 0 DMA transfer request DACK0 DMA transfer request acknowledge acknowledge output from channel 0 to external device DREQ1...
Page 214: Register Configuration
9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels. Table 9.2 DMAC Registers Chan- Abbrevi- Initial Access Name ation Value...
Page 215: Register Descriptions
Register Descriptions 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address (in single-address mode, SAR is ignored in transfers from external devices with DACK to memory-mapped external devices or external memory).
Page 216: Dma Transfer Count Registers 0-3 (Tcr0-Tcr3)
9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMA transfer count registers 0–3 (TCR0–TCR3) are 16-bit read/write registers that specify the DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001, 65535 when the setting is H'FFFF, and 65536 (the maximum) when H'0000 is set. During a DMA transfer, these registers indicate the remaining transfer count.
Page 217 • Bits 15 and 14 (Destination Address Mode Bits 1 and 0 (DM1 and DM0)): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed (in the single address mode, DM1 and DM0 are ignored when transfers are made from memory- mapped external devices or external memory to external devices with DACK).
Page 218 Bit 11: Bit 10: Bit 9: Bit 8: Description DREQ (External request * , dual address mode) (Initial value) Reserved (illegal setting) DREQ (External request * , single address mode * DREQ (External request * , single address mode * RXI0 (On-chip serial communication interface 0 receive data full interrupt transfer request) * TXI0 (On-chip serial communication interface 0 transmit data...
Page 219 • Bit 7 (Acknowledge Mode Bit (AM)): In dual address mode, AM selects whether the DACK signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1. The AM bit is initialized to 0 by a reset and in standby mode. The AM bit is not valid in single address mode.
Page 220 Bit 3: TS Description Byte (8 bits) (Initial value) Word (16 bits) • Bit 2 (Interrupt Enable Bit (IE)): IE determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is sent to the CPU when the TE bit is set.
Page 221: Dma Operation Register (Dmaor)
Bit 0: DE Description DMA transfer disabled (Initial value) DMA transfer enabled 9.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in standby mode.
Page 222 • Bit 2 (Address Error Flag Bit (AE)): AE indicates that an address error has occurred in the DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read 1 from it and then write 0.
Page 223: Operation
Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Page 224 Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? Transfer request occurs? Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); TCR–1 → TCR, SAR and DAR updated Does NMIF = 1, AE = 1, TCR = 0?
Page 225: Dma Transfer Requests
9.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip supporting modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Page 226 source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI’s receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI’s transmit data register (TDR).
Page 227: Channel Priority
When outputting transfer requests from on-chip supporting modules, the appropriate interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from on- chip supporting modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well.
Page 228 (1) When channel 0 transfers ch0 > ch3 > ch2 > ch1 Initial priority order Channel 0 becomes bottom priority Priority order ch3 > ch2 > ch1 > ch0 after transfer (2) When channel 3 transfers ch0 > ch3 > ch2 > ch1 Initial priority order Channel 3 becomes bottom priority.
Page 229 1. Transfer requests are generated simultaneously for channels 1 and 0. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for transfer). 3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4.
Page 230 External-Pin Round-Robin Mode: External-pin round-robin mode switches the priority levels of channel 0 and channel 1, which are the channels that can receive transfer requests from external pins DREQ0 and DREQ1. The priority levels are changed after each (byte or word) transfer on channel 0 or channel 1 is completed.
Page 231 Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels (2) Channel 1 0 and 1 3 > 2 > 1 > 0 transfer starts Priority order changes (3) Channel 1 3 > 2 > 0 > 1 transfer ends (4) Channel 0 transfer starts None...
Page 232: Dma Transfer Types
9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.5. It can operate in single address mode or dual address mode, which are defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode.
Page 233 External address bus External data bus SuperH microcomputer External DMAC memory Read Write External device with DACK DACK DREQ : Data flow Note: The read/write direction is decided by the RS3-RS0 bits in the CHCRn registers. If RS3–RS0 = 0010, the direction is as shown in case 1 (circled number above); if RS3– RS0 = 0011, the direction is as shown in case 2.
Page 234 A21–A0 Address output to external memory space Data output from external device with DACK D15–D0 DACK signal to external device with DACK DACK (active-low) WR signal to external memory space (a) External device with DACK to external memory space A21–A0 Address output to external memory space Data output from external memory space D15–D0...
Page 235 External data bus SuperH microcomputer External DMAC memory External memory : Data flow 1: Read cycle 2: Write cycle Figure 9.8 Data Flow in Dual Address Mode In dual address mode transfers, external memory, memory-mapped external devices, on-chip memory and on-chip supporting modules can be mixed without restriction. Specifically, this enables the following transfer types: 1.
Page 236 A21–A0 Source address Destination address D15–D0 DACK Figure 9.9 DMA Transfer Timing in Dual Address Mode (External Memory Space to External Memory Space Transfer with DACK Output in Read Cycle) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TM bits in CHCR0–CHCR3.
Page 237 • Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In external request mode with low-level detection at the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied.
Page 238 Table 9.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category Transfer Address Request Size Usable Mode Transfer Category Mode Mode (bits) Channels Single External device with DACK and External 8/16 external memory External device with DACK and External 8/16 0, 1...
Page 239: Number Of Bus Cycle States And Dreq Pin Sample Timing
Bus Mode and Channel Priority Order: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (2) with a higher priority, the transfer of the channel with higher priority (2) will begin immediately. When channel 2 is also operating in burst mode, the channel 1 transfer will continue when the channel 2 transfer has completely finished.
Page 240 • DREQ pin sampling timing in cycle-steal mode In cycle-steal mode, the sampling timing is the same regardless of whether DREQ is detected by edge or level. With edge detection, however, once the signal is sampled it will not be sampled again until the next edge detection.
Page 241 DREQ Bus cycle DMAC (R) DMAC (W) DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC read cycle. Figure 9.14 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 1 State) DREQ Bus cycle...
Page 242 DREQ Bus cycle DMAC (R) DMAC (W) DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC write cycle. Figure 9.16 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States) DREQ Bus cycle...
Page 243 DREQ Bus cycle DMAC (R) DMAC (W) DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Figure 9.18 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State) DREQ Bus cycle DMAC...
Page 244 DREQ Bus cycle DMAC DMAC DMAC(R) DMAC (R) DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.20 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = DRAM Bus Cycle (Long Pitch Normal Mode))
Page 245 DREQ Bus cycle DMAC DMAC DMAC(R) DMAC (R) DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.22 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = Address/Data Multiplex I/O Bus Cycle)
Page 246 DREQ DMAC DMAC DMAC cycle DACK Figure 9.23 DREQ Pin Sampling Timing in Burst Mode (Single Address DREQ Level Detection, DACK Active-Low, 1 Bus Cycle = 2 States) DREQ DMAC(R) DMAC(W) DMAC(R) DMAC(W) cycle DACK Figure 9.24 DREQ Pin Sampling Timing in Burst Mode (Dual Address DREQ Level Detection, DACK Active-Low, DACK Output in Read Cycle, 1 Bus Cycle = 2 States)
Page 247: Dma Transfer Ending Conditions
9.3.6 DMA Transfer Ending Conditions The DMA transfer ending conditions differ for individual channel ending and ending on all channels together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel’s DMA transfer count register (TCR) is 0, or when the DE bit in the channel’s CHCR is cleared to 0.
Page 248: Examples Of Use
Examples of Use 9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External Device In the following example, data is transferred from on-chip RAM to a memory-mapped external device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit integrated timer pulse unit (ITU) as the transfer request signal.
Page 249: Example Of Dma Transfer Between On-Chip Sci And External Memory
9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory In this example, receive data of on-chip serial communication interface (SCI) channel 0 is transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions and register settings. Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory...
Page 250: Example Of Dma Transfer Between On-Chip A/D Converter And External Memory
9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External Memory In this example, the results of an A/D conversion by the on-chip A/D converter are transferred to external memory using DMAC channel 3. Input from channel 0 (AN0) is A/D-converted using scan mode.
Page 251: Usage Notes
Usage Notes 1. All registers other than the DMA operation register (DMAOR) and DMA channel control registers 0–3 (CHCR0–CHCR3) should be accessed in word or longword units. 2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance).
Page 252 6. Notes on use of the SLEEP instruction a. Operation contents When a DMAC bus cycle is entered immediately after executing a SLEEP instruction, there are cases when DMA transfer is not carried out correctly. b. Remedy • Stop operation (for example, by clearing the DMA enable bit (DE) in the DMA channel control register (CHCRn)) before entering sleep mode.
Page 253 Especially, if, as shown in figure 9.26, the DMA bus cycle is a full access to DRAM or if a refresh request is generated, sampling of DREQ takes place before DACK is output as mentioned above. This phenomenon is found when one of the following transfers is made with DREQ set to level detection in DMA cycle-steal mode, in a system which employs DRAM (refresh enabled).
Page 254: Section 10 16-Bit Integrated Timer Pulse Unit (Itu)
Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.1 Overview The SuperH microcomputer has an on-chip 16-bit integrated timer pulse unit (ITU) with five 16- bit timer channels. 10.1.1 Features ITU features are listed below: • Can process a maximum of twelve different pulse outputs and ten different pulse inputs. •...
Page 255 • Fifteen interrupt sources: Ten compare match/input capture interrupts (2 sources per channel) and five overflow interrupts are vectored independently for a total of 15 sources. • Can activate DMAC: The compare match/input capture interrupts of channels 0–3 can start the DMAC (one for each of four channels).
Page 256 Table 10.1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal: φ, φ/2, φ/4, φ/8 Counter clocks External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD General registers GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 (output compare/ input capture dual registers)
Page 257: Block Diagram
10.1.2 Block Diagram ITU Block Diagram (Overall Diagram): Figure 10.1 shows a block diagram of the ITU. IMIA0–IMIA4 TCLKA–TCLKD Clock Control IMIB0–IMIB4 selection logic OVI0–OVI4 φ, φ/2, φ/4, φ/8 Counter control and TOCXA4, TOCXB4 pulse I/O control unit TIOCA0–TIOCA4 TIOCB0–TIOCB4 TOCR TSTR TSNC...
Page 258 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2 shows a block diagram of channels 0 and 1. TCLKA– TIOCAn TCLKD TIOCBn Clock selection φ, φ/2, φ/4, φ/8 IMIAn Comparator Control logic IMIBn OVIn Module data bus...
Page 259 Block Diagram of Channel 2: Figure 10.3 shows a block diagram of channel 2. Channel 2 is capable of 0 output/1 output only. TCLKA– TIOCA2 TCLKD TIOCB2 Clock selection φ, φ/2, φ/4, φ/8 IMIA2 Comparator Control logic IMIB2 OVI2 Module data bus TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2, B2 (input capture/output compare dual use) (16 bits ×...
Page 260 Block Diagrams of Channels 3 and 4: Figure 10.4 shows a block diagram of channel 3; figure 10.5 shows a block diagram of channel 4. TCLKA– TCLKD Clock selection TIOCA3 φ, φ/2, TIOCB3 φ/4, φ/8 IMIA3 Comparator Control logic IMIB3 OVI3 Module data bus TCNT3: Timer counter 3 (16 bits)
Page 261 TOCXA4 TCLKA– TOCXB4 TCLKD Clock selection φ, φ/2, TIOCA4 φ/4, φ/8 TIOCB4 IMIA4 Comparator Control logic IMIB4 OVI4 Module data bus TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4, B4 (input capture/output compare dual use) (16 bits × 2) BRA4, BRB4: Buffer registers A4, B4 (input capture/output compare dual use) (16 bits ×...
Page 262: Input/Output Pins
10.1.3 Input/Output Pins Table 10.2 summarizes the ITU pins. External pin functions should be set with the pin function controller to match to the ITU setting. See section 15, Pin Function Controller, for details. ITU pins need to be set using the pin function controller (PFC) after the chip is set to ITU mode. Table 10.2 Pin Configuration Channel Name Pin Name I/O Function...
Page 263: Register Configuration
10.1.4 Register Configuration Table 10.3 summarizes the ITU register configuration. Table 10.3 Register Configuration Abbrevi- Initial Access Address * Channel Name ation Value Size Shared Timer start register TSTR H'E0/H'60 H'5FFFF00 Timer synchro register TSNC H'E0/H'60 H'5FFFF01 Timer mode register TMDR H'80/H'00 H'5FFFF02 Timer function control register...
Page 264 Table 10.3 Register Configuration (cont) Abbrevi- Initial Access Address * Channel Name ation Value Size Timer control register 2 TCR2 H'80/H'00 H'5FFFF18 Timer I/O control register 2 TIOR2 H'88/H'08 H'5FFFF19 Timer interrupt enable register 2 TIER2 H'F8/H'78 H'5FFFF1A R/(W) * Timer status register 2 TSR2 H'F8/H'78...
Page 265: Itu Register Descriptions
Table 10.3 Register Configuration (cont) Abbrevi- Initial Access Address * Channel Name ation Value Size 4 (cont) Timer counter 4 TCNT4 H'00 H'5FFFF36 8, 16 H'5FFFF37 8, 16 General register A4 GRA4 H'FF H'5FFFF38 8, 16, 32 H'5FFFF39 8, 16, 32 General register B4 GRB4 H'FF...
Page 266 • Bits 7–5 (Reserved): Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1.
Page 267: Timer Synchro Register (Tsnc)
10.2.2 Timer Synchro Register (TSNC) The timer synchro register (TSNC) is an eight-bit read/write register that selects timer synchronizing modes for channels 0–4. Channels for which 1 is set in the corresponding bit will be synchronized. TSNC is initialized to H'E0 or H'60 by a reset and in standby mode. Bit: Bit name: —...
Page 268: Timer Mode Register (Tmdr)
• Bit 1 (Timer Synchro 1 (SYNC1)): SYNC1 selects synchronizing mode for channel 1. Bit 1: SYNC1 Description The timer counter for channel 1 (TCNT1) operates independently (Preset/clear of TCNT1 is independent of other channels) (Initial value) Channel 1 operates synchronously. Synchronized preset/clear of TNCT1 enabled.
Page 269 When the MDF bit is set to 1 to select phase counting mode, the timer counter (TCNT2) becomes an up/down-counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with increment/decrement chosen as follows: Count Direction...
Page 270 • Bit 3 (PWM Mode 3 (PWM3)): PWM3 selects the PWM mode for channel 3. When the PWM3 bit is set to 1 and PWM mode is entered, the TIOCA3 pin becomes a PWM output pin. 1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare match of general register B3 (GRB3).
Page 271: Timer Function Control Register (Tfcr)
10.2.4 Timer Function Control Register (TFCR) The timer function control register (TFCR) is an 8-bit read/write register that selects complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation. TFCR is initialized to H'C0 or H'40 by a reset and in standby mode. Bit: Bit name: —...
Page 272 • Bit 3 (Buffer Mode B4 (BFB4)): BFB4 selects buffer mode for GRB4 and BRB4 in channel 4. Bit 3: BFB4 Description GRB4 operates normally in channel 4 (Initial value) GRB4 and BRB4 operate in buffer mode in channel 4 •...
Page 273: Timer Output Control Register (Tocr)
10.2.5 Timer Output Control Register (TOCR) The timer output control register (TOCR) is an eight-bit read/write register that inverts the output level in complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4 is valid only in complementary PWM mode and reset-synchronized PWM mode. In other output situations, these bits are ignored.
Page 274: Timer Counters (Tcnt)
10.2.6 Timer Counters (TCNT) The ITU has five 16-bit timer counters (TCNT), one for each channel. Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock source is selected by timer prescaler bits 2–0 (TPSC2–TPSC0) in the timer control register (TCR). TCNT0 and TCNT 1 are strictly up-counters.
Page 275: General Registers A And B (Gra And Grb)
10.2.7 General Registers A and B (GRA and GRB) Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers. Each GR is a 16-bit read/write register that can function as either an output compare register or an input capture register.
Page 276: Buffer Registers A And B (Bra, Brb)
10.2.8 Buffer Registers A and B (BRA, BRB) Each buffer register is a 16-bit read/write register that is used in buffer mode. The ITU has four buffer registers, two each for channels 3 and 4. Buffer operation can be set independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3.
Page 277: Timer Control Register (Tcr)
10.2.9 Timer Control Register (TCR) The ITU has five 8-bit timer control registers (TCR), one for each channel. TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external clock source, and the counter clear source. TCR is initialized to H'80 or H'00 by a reset and in standby mode.
Page 278 • Bits 6 and 5 (Counter Clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the counter clear source. Bit 6: Bit 5: CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by general register A (GRA) compare match or input capture * TCNT is cleared by general register B (GRB) compare match or input capture *...
Page 279: Timer I/O Control Register (Tior)
Bit 2: Bit 1: Bit 0: Counter Clock (and Cycle when φ = 10 MHz) TPSC2 TPSC1 TPSC0 Internal clock φ (Initial value) Internal clock φ/2 Internal clock φ/4 Internal clock φ/8 External clock A (TCLKA) External clock B (TCLKB) External clock C (TCLKC) External clock D (TCLKD) 10.2.10 Timer I/O Control Register (TIOR)
Page 280 • Bits 6–4 (I/O Control B2–B0 (IOB2–IOB0)): IOB2–IOB0 selects the GRB function. Bit 6: Bit 5: Bit 4: IOB2 IOB1 IOB0 Function GRB is an Compare match with pin output disabled (Initial value) output 0 output at GRB compare match * compare 1 output at GRB compare match * register...
Page 281: Timer Status Register (Tsr)
10.2.11 Timer Status Register (TSR) The timer status register (TSR) is an eight-bit read/write register containing flags that indicate timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER), an interrupt request is sent to the CPU.
Page 282: Timer Interrupt Enable Register (Tier)
• Bit 1 (Input Capture/Compare Match B (IMFB)): IMFB indicates a GRB compare match or input capture. Bit 1: IMFB Description Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB (Initial value) Setting conditions: • GRB is functioning as an output compare register and TCNT = •...
Page 283 Table 10.10 Timer Interrupt Enable Register (TIER) Channel Abbreviation Function TIER0 TIER controls interrupt enabling/disabling TIER1 TIER2 TIER3 TIER4 Bit: Bit name: — — — — — OVIE IMIEB IMIEA Initial value: R/W: — — — — — Note: * Undefined •...
Page 284: Cpu Interface
10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B (BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a 16-bit data bus.
Page 285 Internal data bus Module interface data bus TCNTH TCNTL Figure 10.9 TCNT Access (CPU to TCNT (Lower Byte)) Internal data bus Module interface data bus TCNTH TCNTL Figure 10.10 TCNT Access (TCNT to CPU (Upper Byte)) Internal data bus Module interface data bus TCNTH...
Page 286: 8-Bit Accessible Registers
10.3.2 8-Bit Accessible Registers All registers other than the TCNT register, general registers, and buffer registers are 8-bit registers. These are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and writing in byte units with the timer control register (TCR). These registers must be accessed by byte access.
Page 287: Operation
10.4 Operation 10.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The TCNT is an up-counter and can also operate as a free-running counter, periodic counter, or external event counter. General registers A and B (GRA and GRB) can be used as output compare registers or input capture registers.
Page 288: Basic Functions
• When GR is an input capture register: The TCNT value is transferred to GR when an input capture occurs and simultaneously the value previously stored in GR is transferred to BR. • Complementary PWM mode: When TCNT3 and TCNT4 change count directions, the BR value is transferred to GR.
Page 289 Counting mode selection Select counter clock Counting? Free-running counter Periodic counter Select counter clear source Select output compare register Set period Start counting Start counting Periodic counter Free-running counter Figure 10.14 Procedure for Selecting the Counting Mode • Free-running count and periodic count A reset of the counters for channels 0–4 leaves them all in free-running mode.
Page 290 TCNT value H'FFFF H'0000 Time STR0–STR4 Figure 10.15 Free-Running Counter Operation Counter cleared by TCNT value GR compare match H'0000 Time STR0–STR4 Figure 10.16 Periodic Counter Operation • TCNT counter timing Internal clock source: Bits TPSC2–TPSC0 in TCR select the system clock (CK) or one of three internal clock sources (φ/2, φ/4, φ/8) obtained by prescaling the system clock.
Page 291 Internal clock TCNT input clock N – 1 N + 1 TCNT value Figure 10.17 Count Timing for Internal Clock Sources External clock input pin TCNT input clock N – 1 N + 1 TCNT Figure 10.18 Count Timing for External Clock Sources (Both-Edge Detection) Compare-Match Waveform Output Function: For ITU channels 0, 1, 3, and 4, the output from the corresponding TIOCA and TIOCB pins upon compare matches A and B can be in three modes: 0-level output, 1-level output, or toggle.
Page 292 Output selection Select waveform output mode Select output timing Start counting Waveform output Figure 10.19 Procedure for Selecting Compare Match Waveform Output Mode • Waveform output operation Figure 10.20 illustrates 0 output/1 output. In the example, TCNT is a free-running counter, 0 is output upon compare match A, and 1 is output upon compare match B.
Page 293 Counter cleared at TCNT value GRB compare match Time Toggle TIOCB output Toggle TIOCA output Figure 10.21 Example of Toggle Output • Compare match output timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value).
Page 294 Input Capture Mode: In input capture mode, the counter value is captured into a general register when the input edge is detected at an input capture/output compare pin (TIOCA, TIOCB). Detection can take place on the rising edge, falling edge, or both edges. The pulse width and cycle can be measured by using the input capture function.
Page 295 • Input capture operation Figure 10.24 illustrates input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture edges. In the example, TCNT is set to clear at GRB input capture. TCNT Counter cleared value by TIOCB input (falling edge)
Page 296 • Input capture timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 297: Synchronizing Mode
10.4.3 Synchronizing Mode In synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR settings (synchronized clear). Synchronizing mode enables the general registers to be incremented with a single time base.
Page 298 Synchronized Operation: Figure 10.27 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM output. Channel 0 is set for a counter clear upon compare match with GRB0. Channels 1 and 2 are set for counter clears by synchronizing clears.
Page 299: Pwm Mode
10.4.4 PWM Mode PWM mode is controlled using both GRA and GRB in pairs. The PWM waveform is output from the TIOCA output pin. The PWM waveform’s 1 output timing is set in GRA and the 0 output timing is set in GRB. A PWM waveform with a duty cycle between 0% and 100% can be output from the TIOCA pin by selecting either compare match GRA or GRB as the counter clear source for the timer counter.
Page 300 PWM mode Select counter clock Select counter clear source Set GRA Set GRB Select PWM mode Start counting PWM mode Figure 10.28 Procedure for Selecting PWM Mode PWM Mode Operation: Figure 10.29 illustrates PWM mode operation. When PWM mode is set, the TIOCA pin becomes the output pin.
Page 301 TCNT value Counter cleared by GRA compare match Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by GRB compare match Time TIOCA b. Counter cleared by GRB Figure 10.29 PWM Mode Operation Example 1...
Page 302 TCNT value Counter cleared on compare match B Time H'0000 TIOCA GRA write GRA write a. 0% duty TCNT value Counter cleared on compare match A Time H'0000 TIOCA GRB write GRB write b. 100% duty Figure 10.30 PWM Mode Operation Example 2...
Page 303: Reset-Synchronized Pwm Mode
10.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode, three pairs of complementary positive and negative PWM waveforms that share a common wave turning point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins become PWM output pins and TCNT3 becomes an up-counter.
Page 304 6. GRA3 is the waveform period register. Set the waveform period value in GRA3. Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3. X ≤ GRA3 (X: set value) 7.
Page 305 Reset-Synchronized PWM Mode Operation: Figure 10.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter that is cleared to H'0000 at compare match with GRA3. TCNT4 runs independently and is isolated from GRA4 and GRB4. The PWM waveform outputs toggle at each compare match (GRB3, GRA3, and GRB4 with TCNT3) and when the counter is cleared.
Page 306: Complementary Pwm Mode
10.4.6 Complementary PWM Mode In complementary PWM mode, three pairs of complementary, non-overlapping, positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins become PWM output pins and TCNT3 and TCNT4 become up-counters.
Page 307 4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and TCNT4 to the same value. 5. GRA3 is the waveform period register. Set the upper limit of TCNT3–1 * . Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4.
Page 308 Complementary PWM Mode Operation: Figure 10.34 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match of TCNT3 and GRA3 and counting up when TCNT4 underflows. PWM waveforms are output by repeated compare matches with GRB3, GRA4, and GRB4 in the sequence TCNT3, TCNT4, TCNT4, TCNT3 (in this mode, TCNT3 starts out at a higher value than TCNT4).
Page 309 TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 0% duty (a) With 0% duty TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 100% duty (b) With 100% duty Figure 10.35 Complementary PWM Mode Operation Example 2 At the point where the up-count/down-count changes in complementary PWM mode, TCNT3 and TCNT4 will overshoot and undershoot, respectively.
Page 310 TCNT3 N–1 N + 1 N–1 GRA3 Flag not set IMFA Set to 1 Buffer transfer signal (BR to GR) Buffer transfer performed Buffer transfer not performed Figure 10.36 Overshoot Timing Underflow Overflow TCNT4 H' 0001 H' 0000 H' FFFF H' 0000 Flag not set Set to 1...
Page 311 GR Setting in Complementary PWM Mode: Note the following when setting the general registers in complementary PWM mode and when making changes during operation. • Initial values: Settings from H'0000 to T–1 (T: TCNT3 initial setting) are prohibited. After counting starts, this setting is allowed from the point when the first A3 compare match occurs. •...
Page 312 TCNT3 TCNT4 T – 1 Changes prohibited H' 0000 H' FFFF Figure 10.40 Caution on Changing GR Settings with Buffer Operation (2) When GR Settings are Outside the Count Range (H'0000–GRA3): Waveforms with a duty cycle of 0% and 100% can be output by setting GR outside the count area. Be sure to make the direction of the count (increment/decrement) when writing a setting from outside the count area into the buffer register (BR) the same as the count direction when writing the setting that returns to within the count area in BR.
Page 313: Phase Counting Mode
10.4.7 Phase Counting Mode Phase counting mode detects the phase differential of two external clock inputs (TCLKA and TCLKB) and increments or decrements TCNT2. When phase counting mode is set, the TCLKA and TCLKB pins become external clock input pins, regardless of the settings of the TPSC2– TPSC0 bits in TCR2 or the CKEG1 and CKEG0 bits.
Page 314 TCNT2 value Increment Decrement TCNT2 Time TCLKB TCLKA Figure 10.43 Phase Counting Mode Operation Table 10.16 Up/Down-Counting Conditions Counting Direction Increment Decrement TCLKB Rising High Falling Rising High Falling TCLKA Rising High Falling High Falling Rising Phase Phase Pulse Pulse differential differential width...
Page 315: Buffer Mode
10.4.8 Buffer Mode In buffer mode, the buffer operation functions differ depending on whether the general registers are set to output compare or input capture, reset-synchronized PWM mode, or complementary PWM mode. Buffer mode is a function of channels 3 and 4 only. Buffer operations set this way function as follows.
Page 316 Reset-Synchronized PWM Mode: The BR value is transferred to GR upon a GRA3 compare match. Procedure for Selecting Buffer Mode (Figure 10.47): 1. Set TIOR to select the output compare or input capture function of GR. 2. Set bits BFA3, BFB3 and BFB4 in TFCR to select buffer mode for GR. 3.
Page 317 Counter cleared by compare match B TCNT value H' 0250 H' 0200 H' 0100 H' 0000 Time H' 0200 H' 0100 H' 0200 H' 0250 H' 0200 H' 0100 H' 0200 Toggle output TIOCB TIOCA Toggle output Compare match A Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register) n + 1 TCNT...
Page 318 TCNT value Counter cleared at input capture B H' 0180 H' 0160 H' 0005 Time TIOCB TIOCA H' 0005 H' 0160 H' 0005 H' 0160 H' 0180 Input capture A Figure 10.50 Buffer Mode Operation Example 2 (Input Capture Register) TIOC pin Input capture signal...
Page 319 An example of buffer operation in complementary PWM mode between GRB3 and BRB3 is shown in figure 10.52. By making GRB3 larger than GRA3 using buffer operation, a PWM waveform with a duty cycle of 0% is generated. The transfer from BRB to GRB occurs upon TCNT3 and GRA compare match and TCNT4 underflow.
Page 320: Itu Output Timing
10.4.9 ITU Output Timing ITU outputs in channels 3 and 4 can be inverted with TOCR. Output Inversion Timing with TOCR: Output levels can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR in complementary PWM mode and reset- synchronized PWM mode.
Page 321: Interrupts
10.5 Interrupts The ITU has two interrupt sources: input capture/compare match and overflow. 10.5.1 Timing of Setting Status Flags Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits in TSR are set to 1 by a compare match signal generated when TCNT matches a general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count).
Page 322 Timing of Setting IMFA, IMFB for Input Capture: IMFA and IMFB are set to 1 by an input capture signal. At this time, the TCNT contents are transferred to GR. Figure 10.55 shows the timing. Input capture signal TCNT Figure 10.55 Timing of Setting IMFA and IMFB for Input Capture Timing of Setting Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF.
Page 323: Status Flag Clear Timing
10.5.2 Status Flag Clear Timing The status flags are cleared by being read by the CPU when set to 1, then being written with 0. This timing is shown in figure 10.57. TSR write cycle TSR address Address IMF, OVF Figure 10.57 Timing of Status Flag Clearing...
Page 324: Interrupt Sources And Dmac Activation
10.5.3 Interrupt Sources and DMAC Activation The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are allocated their own independently vectored addresses. When the interrupt's interrupt request flag is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested.
Page 325: Notes And Precautions
10.6 Notes and Precautions This section describes contention and other matters requiring special attention during ITU operation. 10.6.1 Contention between TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes priority and the write is not performed.
Page 326: Contention Between Tcnt Word Write And Increment
10.6.2 Contention between TCNT Word Write and Increment If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. The timing is shown in figure 10.59. TCNT word write cycle by CPU TCNT address Address Internal write signal...
Page 327: Contention Between Tcnt Byte Write And Increment
10.6.3 Contention between TCNT Byte Write and Increment If an increment pulse occurs in the T2 state or T3 state of a TCNT byte write cycle, counter writing takes priority and the byte data on the side that was previously written is not incremented. The TCNT byte data that was not written is also not incremented and retains its previous value.
Page 328: Contention Between Gr Write And Compare Match
10.6.4 Contention between GR Write and Compare Match If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes priority and the compare match signal is inhibited. The timing is shown in figure 10.61. GR write cycle Address GR address...
Page 329: Contention Between Tcnt Write And Overflow/Underflow
10.6.5 Contention between TCNT Write and Overflow/Underflow If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter incrementing. OVF is set to 1. The same applies to underflows. The timing is shown in figure 10.62.
Page 330: Contention Between General Register Read And Input Capture
10.6.6 Contention between General Register Read and Input Capture If an input capture signal is generated during the T3 state of a general register read cycle, the value before input capture is read. The timing is shown in figure 10.63. GR read cycle GR address Address...
Page 331: Contention Between Counter Clearing By Input Capture And Counter Increment
10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, the counter is cleared by the input capture signal. The counter is not incremented by the increment signal. The TCNT value before the counter is cleared is transferred to the general register.
Page 332: Contention Between General Register Write And Input Capture
10.6.8 Contention between General Register Write and Input Capture If an input capture signal is generated during the T3 state of a general register write cycle, the input capture transfer takes priority and the write to GR is not performed. The timing is shown in figure 10.65.
Page 333: 10.6.10 Contention Between Br Write And Input Capture
10.6.10 Contention between BR Write and Input Capture When a buffer register (BR) is being used as an input capture register and an input capture signal is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write. The timing is shown in figure 10.66.
Page 334: 10.6.11 Note On Writing In Synchronizing Mode
10.6.11 Note on Writing in Synchronizing Mode After synchronizing mode is selected, if TCNT is written by byte access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are synchronized Write A to upper byte of channel 2...
Page 335: 10.6.13 Clearing Complementary Pwm Mode
10.6.13 Clearing Complementary PWM Mode Figure 10.69 shows the procedure for clearing complementary PWM mode. First, reset combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to either 00 or 01. The mode will switch from complementary PWM mode to normal operating mode.
Page 336: 10.6.15 Itu Operating Modes
10.6.15 ITU Operating Modes Table 10.18 ITU Operating Modes (Channel 0) Register Setting TSNC TMDR TFCR TOCR TIOR0 TCR0 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ √ √...
Page 337 Table 10.19 ITU Operating Modes (Channel 1) Register Setting TSNC TMDR TFCR TOCR TIOR1 TCR1 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ √ √ √ √ Synch- SYNC1 —...
Page 338 Table 10.20 ITU Operating Modes (Channel 2) Register Setting TSNC TMDR TFCR TOCR TIOR2 TCR2 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ √ √ √ √ Synch- SYNC2 —...
Page 339 Table 10.21 ITU Operating Modes (Channel 3) Register Setting TSNC TMDR TFCR TOCR TIOR3 TCR3 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ √ * √ √ √ √...
Page 340 Table 10.21 ITU Operating Modes (Channel 3) (cont) Register Setting TSNC TMDR TFCR TOCR TIOR3 TCR3 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ * √ √ √ * Comple- —...
Page 341 Table 10.22 ITU Operating Modes (Channel 4) Register Setting TSNC TMDR TFCR TOCR TIOR4 TCR4 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ √ * √ √ √ √...
Page 342 Table 10.22 ITU Operating Modes (Channel 4) (cont) Register Setting TSNC TMDR TFCR TOCR TIOR4 TCR4 Reset Output Operating Comp Sync Level Clear Clock Mode Sync MDF FDIR PWM PWM Buffer Select IOA Select Select √ * √ √ √ * Comple- —...
Page 344: Section 11 Programmable Timing Pattern Controller (Tpc)
Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The SuperH microcomputer has an on-chip programmable timing pattern controller (TPC). The TPC can provide pulse outputs by using the 16-bit integrated timer pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups 3–0. These can operate simultaneously or independently.
Page 345: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. ITU compare match signal PBCR1 PBCR2 NDERA NDERB Control logic TPMR TPCR TP15 Internal TP14 Pulse output data TP13 pin group 3 TP12 NDRB TP11 TP10 Pulse output pin group 2 PBDR Pulse output...
Page 346: Input/Output Pins
11.1.3 Input/Output Pins Table 11.1 summarizes the TPC input/output pins. Table 11.1 TPC Pins Name Symbol Input/Output Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 347: Registers
11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Initial Access Address * Name Abbreviation Value Size Port B control register 1 PBCR1 H'0000 H'5FFFFCC 8, 16 Port B control register 2 PBCR2 H'0000 H'5FFFFCE 8, 16 R/(W) * Port B data register PBDR...
Page 348: Register Descriptions
11.2 Register Descriptions 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2) Port B control registers 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the functions of port B pins. Port B consists of the dual-use pins TP15–TP0. Bits corresponding to the pins to be used for TPC output must be set to 11.
Page 349: Port B Data Register (Pbdr)
11.2.2 Port B Data Register (PBDR) The port B data register (PBDR) is a 16-bit read/write register that stores output data for groups 0– 3 when TPC output is used. For details of PBDR, see section 16, I/O Ports. Bit: Bit name: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/(W) *...
Page 350 Bit: Bit name: NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value: R/W: Address H'5FFFFF7: • Bits 7–0 (Reserved): These bits are always read as 1. The write value should always be 1. Bit: Bit name: — — — —...
Page 351: Next Data Register B (Ndrb)
Bit: Bit name: — — — — NDR3 NDR2 NDR1 NDR0 Initial value: R/W: — — — — 11.2.4 Next Data Register B (NDRB) NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3 and 2 (TP15–TP8).
Page 352 Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — — Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4 and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6.
Page 353: Next Data Enable Register A (Ndera)
11.2.5 Next Data Enable Register A (NDERA) NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7–TP0) on a bit-by-bit basis. When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the TPC output control register, the value of the next data register A (NDRA) is automatically transferred to the corresponding PBDR bits and the output value is updated.
Page 354: Tpc Output Control Register (Tpcr)
• Bits 7–0 (Next Data Enable 15–8 (NDER15–NDER8)): NDER15–NDER8 select enabling/disabling for TPC output groups 3 and 2 (TP15–TP8) in bit units. Bit 7–0: NDER15–NDER8 Description Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8 is disabled) (Initial value) Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8 is enabled) 11.2.7 TPC Output Control Register (TPCR)
Page 355 • Bits 5 and 4 (Group 2 Compare Match Select 1 and 0 (G2CMS1 and G2CMS0)): G2CMS1 and G2CMS0 select the ITU channel that triggers TPC output group 2 (TP11–TP8). Bit 5: G2CMS1 Bit 4: G2CMS0 Description TPC output group 2 (TP11–TP18) output is triggered by compare match in ITU channel 0 TPC output group 2 (TP11–TP18) output is triggered by compare match in ITU channel 1...
Page 356: Tpc Output Mode Register (Tpmr)
11.2.8 TPC Output Mode Register (TPMR) TPMR is an eight-bit read/write register that selects between the TPC’s ordinary output and non- overlap output modes in group units. During non-overlap operation, the output waveform cycle is set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in general register A (GRA).
Page 357: Operation
• Bit 1 (Group 1 Non-Overlap Mode (G1NOV)): G1NOV selects ordinary or non-overlap mode for TPC output group 1 (TP7–TP4). Bit 1: G1NOV Description TPC output group 1 operates normally (output value updated according to compare match A of the ITU channel selected by TPCR) (Initial value) TPC output group 1 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare match...
Page 358: Output Timing
NDER Output trigger signal Port function Internal select data bus output pin Figure 11.2 TPC Output Operation If new data is written in next data registers A and B before the next compare match occurs, a maximum 16 bits of data can be output at each successive compare match. See section 11.3.4, TPC Output Non-Overlap Operation, for details on non-overlap operation.
Page 359: Examples Of Use Of Ordinary Tpc Output
TCNT N + 1 Compare match A signal NDRB PBDR TP15–TP8 Figure 11.3 Transfer and Output Timing for NDRB Data (Example) 11.3.3 Examples of Use of Ordinary TPC Output Settings for Ordinary TPC Output (Figure 11.4): 1. Select GRA as the output compare register (output disable) with the timer I/O control register (TIOR).
Page 360 Ordinary TPC output operation Select GR function Set GRA ITU setting Set count operation Select interrupt request Set initial output value Set port output Port and Set TPC output enable setting Select TPC output trigger Set next TPC output value Start count ITU setting (10)
Page 361 Five-Phase Pulse Output (Figure 11.5): Figure 11.5 shows an example of 5-phase pulse output generated at regular intervals using TPC output. 1. Set the GRA register of the ITU that serves as output trigger as the output compare register. Set the cycle time in GRA of the ITU and select counter clearing upon compare match A. Set the IMIEA bit in TIER to 1 to enable the compare match A interrupt.
Page 362: Tpc Output Non-Overlap Operation
11.3.4 TPC Output Non-Overlap Operation Setting Procedures for TPC Output Non-Overlap Operation (Figure 11.6): 1. Select GRA and GRB as output compare registers (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle in GRB and the non-overlap cycle in GRA. 3.
Page 363 TPC output non- overlap operation Select GR function Set GRA ITU setting Set count operation Select interrupt request Set initial output value Set TPC output Set TPC transfer enable Port and setting Select TPC output trigger Select non-overlap group (10) Set next TPC output value ITU setting Start count...
Page 364 TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output) (Figure 11.7): 1. Set the GRA and GRB registers of the ITU that serves as output triggers as output compare registers. Set the cycle in GRB and the non-overlap cycle time in GRA and select counter clearing upon compare match B.
Page 365 TCNT value TCNT Time H'0000 NDRB PBDR Non-overlap cycle TP15 TP14 TP13 TP12 TP11 TP10 Figure 11.7 Non-Overlap Output Example (Four-Phase Complementary Output)
Page 366: Tpc Output By Input Capture
11.3.5 TPC Output by Input Capture TPC can also be output by using input capture rather than ITU compare matches. The general register A (GRA) of the ITU selected by TPCR functions as an input capture register and TPC output occurs in response to an input capture signal. Figure 11.8 shows the timing. TIOC pin Input capture...
Page 367: Usage Notes
11.4 Usage Notes 11.4.1 Non-Overlap Operation During non-overlap operation, transfers from NDR to data registers (DR) occur as follows. 1. NDR contents are always transferred to DR on compare match A. 2. The contents of bits transferred from NDR are only transferred on compare match B when they are 0.
Page 368 When a compare match B occurs before the compare match A, the 0 data transfer can be performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases, be sure not to change the NDR contents until the compare match A after the compare match B occurs (non-overlap period).
Page 370: Section 12 Watchdog Timer (Wdt)
Section 12 Watchdog Timer (WDT) 12.1 Overview The SuperH microcomputer has a one-channel watchdog timer (WDT) for monitoring system operations. If the system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip.
Page 371: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. φ/2 Overflow φ/64 Interrupt (interrupt control φ/128 signal) φ/256 Clock Clock φ/512 select φ/1024 φ/4096 WDTOVF Reset φ/8192 Internal control reset signal * Internal clock sources RSTCSR TCNT TCSR interface Module bus...
Page 372: Register Configuration
12.1.4 Register Configuration Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 12.2 WDT Registers Address * Initial Write * Read * Name Abbreviation R/W Value R/(W) * Timer control/status register...
Page 373: Timer Control/Status Register (Tcsr)
12.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an eight-bit read/write register. TCSR differs from other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a reset and in standby mode.
Page 374: Reset Control/Status Register (Rstcsr)
• Bits 4 and 3 (Reserved): These bits are always read as 1. The write value should always be 1. • Bits 2–0 (Clock Select 2–0 (CKS2–CKS0)): CKS2–CKS0 select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ).
Page 375: Notes On Register Access
• Bit 7 (Watchdog Timer Overflow (WOVF)): WOVF indicates that TCNT has overflowed (from H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode. Bit 7: WOVF Description No TCNT overflow in watchdog timer mode (Initial value) Cleared when software reads WOVF, then writes 0 in WOVF Set by TCNT overflow in watchdog timer mode...
Page 376 Writing to TCNT Address: H'5FFFFB8 H'5A Write data Writing to TCSR Address: H'5FFFFB8 H'A5 Write data Figure 12.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'5FFFFFBA. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 12.3.
Page 377: Operation
12.3 Operation 12.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs.
Page 378 TCNT value Overflow H'FF H'00 Time WT/IT = 1 H'00 written WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128 φ clocks Internal reset signal* 512 φ...
Page 379: Operation In Interval Timer Mode
12.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 12.5).
Page 380: Timing Of Overflow Flag (Ovf) Setting
12.3.4 Timing of Overflow Flag (OVF) Setting In interval timer mode, when TCNT overflows the OVF flag in TCSR is set to 1 and an interval timer interrupt is requested (figure 12.6). H'FF H'00 TCNT Overflow signal (internal signal) Figure 12.6 Timing of OVF Setting 12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting When TCNT overflows the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output.
Page 381: Usage Notes
12.4 Usage Notes 12.4.1 TCNT Write and Increment Contention If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 12.8). TCNT write cycle Address TCNT address...
Page 382: System Reset With Wdtovf
System Reset With WDTOVF 12.4.4 If a WDTOVF signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 12.9.
Page 384: Section 13 Serial Communication Interface (Sci)
Section 13 Serial Communication Interface (SCI) 13.1 Overview The SuperH microcomputer has a serial communication interface (SCI) with two independent channels. Both channels are functionally identical. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors.
Page 385: Block Diagram
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Internal Module data bus data bus...
Page 386: Input/Output Pins
13.1.3 Input/Output Pins Table 13.1 summarizes the SCI pins by channel. Table 13.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function Serial clock pin SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output...
Page 387: Register Descriptions
Table 13.2 Registers Initial Access Address * Channel Name Abbreviation Value size H'05FFFEC0 Serial mode register SMR0 H'00 8, 16 H'05FFFEC1 Bit rate register BRR0 H'FF 8, 16 H'05FFFEC2 Serial control register SCR0 H'00 8, 16 H'05FFFEC3 Transmit data register TDR0 H'FF 8, 16 R/(W) *...
Page 388: Transmit Shift Register
The CPU can read but not write to RDR. RDR is initialized to H'00 by a reset and in standby mode. Bit: Bit name: Initial value: R/W: 13.2.3 Transmit Shift Register The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 389: Serial Mode Register
13.2.5 Serial Mode Register The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SMR. SMR is initialized to H'00 by a reset and in standby mode.
Page 390 • Bit 4 (Parity Mode (O/E): O/E selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled.
Page 391: Serial Control Register
• Bits 1 and 0 (Clock Select 1 and 0 (CKS1 and CKS0)): CKS1 and CKS0 select the internal clock source of the on-chip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.8, Bit Rate Register (BRR).
Page 392 • Bit 6 (Receive Interrupt Enable (RIE)): RIE enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 due to transfer of serial receive data from RSR to RDR. Also enables or disables receive-error interrupt (ERI) requests.
Page 393 Bit 3: MPIE Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) MPE is cleared to 0 when: 1. MPIE is cleared to 0, or 2. Multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled: Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until the multiprocessor bit is set to 1.
Page 394: Serial Status Register
Bit 1: Bit 0: Description * CKE1 CKE0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined) * (Initial value) Internal clock, SCK pin used for serial clock output * Synchronous mode (Initial value) Internal clock, SCK pin used for clock output *...
Page 395 Bit 7: TDRE Description TDR contains valid transmit data TDRE is cleared to 0 when: • Software reads TDRE after it has been set to 1, then writes 0 in TDRE • The DMAC writes data in TDR TDR does not contain valid transmit data (Initial value) TDRE is set to 1 when: •...
Page 396 Bit 5: ORER Description Receiving is in progress or has ended normally * (Initial value) ORER is cleared to 0 when: • The chip is reset or enters standby mode • Software reads ORER after it has been set to 1, then writes 0 in ORER A receive overrun error occurred * ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 Notes: *1 Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which...
Page 397 Bit 3: PER Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. PER is cleared to 0 when: •...
Page 398: Bit Rate Register (Brr)
• Bit 0 (Multiprocessor Bit Transfer (MPBT)): MPBT stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting.
Page 399 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) 2.097152 Bit Rate Error (%) Error (%) (bits/s) 0.03 –0.04 0.16 0.21 0.16 0.21 0.16 0.21 1200 0.16 –0.70 2400 0.16 1.14 4800 0.16 –2.48 9600 — — —...
Page 400 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 4.9152 Bit Rate(bits/s) n Error (%) n Error (%) Error (%) 0.03 0.31 –0.25 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00...
Page 401 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 9.8304 Bit Rate Error Error Error Error (bits/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 1200 0.16 0.00 0.16 0.16 2400...
Page 402 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 17.2032 19.6608 Bit Rate Error Error Error Error (bits/s) 0.48 –0.12 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16...
Page 403 Table 13.4 Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — — — — — — — — — 2.5k 100k 250k 500k —...
Page 404 SMR Settings Clock Source CKS1 CKS0 φ φ/4 φ/16 φ/64 The bit rate error for asynchronous mode is given by the following formula: Error (%) = {(φ × 10 )/[(N + 1) × B × 64 × 2 ] – 1 } × 100 2n –...
Page 405 Table 13.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 13.6 and 13.7 show the maximum rates for external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ...
Page 406 Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 407: Operation
Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 13.3 Operation...
Page 408 Synchronous Mode: • The communication format has a fixed eight-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.
Page 409: Operation In Asynchronous Mode
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SCR Settings SCI Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Mode CKE1 CKE0 Clock Source SCK Pin Function* Asynchronous Internal SCI does not use the SCK pin mode Outputs a clock with frequency matching the bit rate External...
Page 410 Idle (mark) state (LSB) (MSB) Serial data Start Parity Stop Transmit/receive data 7 or 8 bits 1 bit 1 or 1 or no bit 2 bits One unit of communication (character or frame) Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and Two Stop Bits)
Page 411 Transmit/Receive Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Bits CHR PE STOP START 8-bit data STOP...
Page 412 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
Page 413 Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR Set value in BRR Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) Wait 1-bit interval elapsed? Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary Figure 13.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for...
Page 414 Initialize Start transmitting Read TDRE bit in SSR TDRE = 1? Write transmit data in TDR and clear TDRE bit to 0 in SSR All data transmitted? Read TEND bit in SSR TEND = 1? Output break signal? Set DR = 0 Clear TE bit of SCR to 0;...
Page 415 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR).
Page 416 Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDRE TEND TXI interrupt request handler writes request TEI request data in TDR and clears TDRE to 0 1 frame Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data.
Page 417 Initialization Start receiving Read the ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Error handling Read the RDRF bit in SSR RDRF = 1? Read the RDR's receive data and clear the RDRF bit in SSR to 0 Total count received? Clear the RE bit in SCR to 0 Reception ends...
Page 418 Start of error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER to 0 in SSR Figure 13.7 Sample Flowchart for Receiving Serial Data (cont)
Page 419 In receiving, the SCI operates as follows: 1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3.
Page 420: Multiprocessor Communication
Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDRE RXI request RXI interrupt handler Framing error, 1 frame reads data in RDR ERI request and clears RDRF to 0 Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial...
Page 421 Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID-sending cycle: Data-sending cycle: receiving processor address data sent to receiving...
Page 422 Initialize Start transmitting Read TDRE bit in SSR TDRE = 1? Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? Read TEND bit in SSR TEND = 1? Output break signal? Set DR = 0 Clear TE bit to 0 in SCR;...
Page 423 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR).
Page 424 Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. ID receive cycle: set the MPIE bit in the serial control register (SCR) to 1. 3.
Page 425 Initialization Start receiving Set the MPIE bit in SCR to 1 Read the ORER and FER bits in SSR FER = 1 or ORER = 1? Read the RDRF bit in SSR RDRF = 1? Read the receive data in RDR Own ID? Read the ORER and FER bits in SSR...
Page 426 Start of error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER to 0 in SSR Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Page 427 Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Stop Start Data 1 Data ID1 Serial Idle (mark) data state MPIE RDRF value RXI request, RXI interrupt Not own ID, No RXI (multiprocessor handler reads data so MPIE is interrupt, interrupt) MPIE = 0...
Page 428: Synchronous Operation
Start Stop Stop Start Data 2 Data ID2 Serial Idle (mark) data state MPIE RDRF Data2 value RXI request, RXI interrupt Own ID, so receving MPIE (multiprocessor handler reads data continues, with data bit is again interrupt) in RDR and clears received at each RXI set to 1 MPIE = 0...
Page 429 Transfer direction One unit (character or frame) of serial data Serial clock Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next.
Page 430 If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3.
Page 431 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0.
Page 432 Transmitting Serial Data (Synchronous Mode): Figure 13.17 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 3.
Page 433 Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
Page 434 Initialization Start receiving Read ORER bit in SSR ORER = 1? Error handling Read RDRF bit in SSR RDRF = 1? Read receive data in RDR and clear RDRF bit in SSR to 0 Total count received? Clear RE bit in SCR to 0 Reception ends Figure 13.18 Sample Flowchart for Serial Receiving...
Page 435 Error handling ORER = 1? Overrun error handling Clear ORER bit in SSR to 0 Figure 13.18 Sample Flowchart for Serial Receiving (cont) Receive direction Serial clock Serial Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data RDRF...
Page 436 to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during reception. When restarting reception, be sure to clear the error flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI).
Page 437 Initialization Start transmitting and receiving Read TDRE bit in SSR TDRE = 1? Write transmit data to TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR ORER = 1? Error handling Read RDRF bit in SSR RDRF = 1? Read receive data in RDR and clear RDRF bit...
Page 438: Sci Interrupt Sources And The Dmac
13.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR).
Page 439 Table 13.13 SSR Status Flags and Transfer of Receive Data Receive Data SSR Status Flags Transfer RSR → RDR Receive Error Status RDRF ORER Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error...
Page 440 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Internal base clock –7.5 clocks +7.5 clocks Receive Start bit data (RxD)
Page 441 Constraints on DMAC Use: • When using an external clock source for the serial clock, update TDR with the DMAC, and then input the transmit clock after the elapse of five system clocks or more. If a transmit clock is input in the first four system clocks after TDR is written, an error may occur (figure 13.22). •...
Page 442: Section 14 A/D Converter
Section 14 A/D Converter 14.1 Overview The SuperH microcomputer includes an analog-to-digital converter module which can be programmed for input of analog signals up to eight channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 14.1.1 Features •...
Page 443: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit φ/8 – Analog φ/16 Control circuit multi- Comparator plexer Sample-and- hold circuit interrupt signal ADTRG A/D converter ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B...
Page 444: Configuration Of Input Pins
14.1.3 Configuration of Input Pins Table 14.1 lists input pins for the A/D converter. The eight analog input pins are grouped into two sets. Group 0 comprises analog input pins 0–3 (AN –AN ) and group 1 comprises pins 4–7 (AN –...
Page 445: Configuration Of A/D Registers
14.1.4 Configuration of A/D Registers The A/D converter includes the registers listed in table 14.2. Table 14.2 A/D Registers Address * Register Name Abbreviation R/W Initial Value Access Size A/D data register A (high) ADDRAH H'00 H'05FFFEE0 8, 16 A/D data register A (low) ADDRAL H'00 H'05FFFEE1...
Page 446: A/D Control/Status Register (Adcsr)
Bit: ADDRn: Initial value: R/W: Bit: ADDRn: — — — — — — Initial value: R/W: n = A–D Table 14.3 Assignment of Data Registers to Analog Input Channels Analog Input Channel Group 0 Group 1 A/D Data Register ADDRA ADDRB ADDRC ADDRD...
Page 447 • Bit 7 (A/D End Flag (ADF)): ADF indicates that A/D conversion is completed. Bit 7 (ADF) Description Cleared to 0 under the following conditions: (Initial value) • The CPU reads the ADF bit while the bit is set to 1, then writes 0 in the bit •...
Page 448: A/D Control Register (Adcr)
• Bit 3 (Clock Select (CKS)): CKS selects the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to 0. Bit 3 (CKS) Description Conversion time = 266 states (maximum) (Initial value) Conversion time = 134 states (maximum) •...
Page 449: Cpu Interface
• Bit 7 (Trigger Enable (TRGE)): TRGE selects whether or not to start A/D conversion when an external trigger is input. Bit 7 (TRGE) Description When an external trigger is input, A/D conversion does not start (Initial value) A/D conversion starts at the falling edge of an input signal from the external trigger pin (ADTRG).
Page 450 Upper byte read Module internal data bus receives interface data H'AA TEMP [H'40] ADDRn H ADDRn L n = A to D [H'AA] [H'40] Lower byte read Module internal data bus receives interface data H'40 TEMP [H'40] ADDRn H ADDRn L n = A to D [H'AA] [H'40]...
Page 451: Operation
14.4 Operation The A/D converter operates by successive approximations with a 10-bit resolution. Its two modes, single mode and scan mode, are described below. 14.4.1 Single Mode (SCAN = 0) In single mode, A/D conversion is performed on a single channel. A/D conversion starts when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or an external trigger input.
Page 452 Note: * Downward arrows (↓) indicate instruction execution. Figure 14.3 A/D Operation in Single Mode (Channel 1 Selected)
Page 453: Scan Mode (Scan = 1)
14.4.2 Scan Mode (SCAN = 1) Scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts with the first channel (AN0 when CH2 = 0, AN4 when CH2 = 1) in the group.
Page 454 Notes: *1 Downward arrow indicates instruction executed by software. *2 Data being converted is ignored. Figure 14.4 A/D Operation in Scan Mode (Channels 0–2 Selected)
Page 455: Input Sampling Time And A/D Conversion Time
14.4.3 Input Sampling Time and A/D Conversion Time With a built-in sample-and-hold circuit, the A/D converter performs input sampling at time t after control/status register (ADSCR) access is started. See figure 14.5 for A/D conversion timing and table 14.4 for A/D conversion times. The total conversion time includes t and the input sampling time, as shown in figure 14.5.
Page 456: A/D Conversion Start By External Trigger Input
Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol A/D start delay — — Input sampling time — — — — Total A/D conversion time — — CONV Note: Values are the number of states (tcyc). 14.4.4 A/D Conversion Start by External Trigger Input The A/D converter can be started when an external trigger is input.
Page 457: Definitions Of A/D Conversion Accuracy
14.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: •...
Page 458: A/D Converter Usage Notes
14.7 A/D Converter Usage Notes When using the A/D converter, note the points listed in section 14.7.1 below. 14.7.1 Setting Analog Input Voltage • Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input ≤ ANn ≤ AV pins ANn should be in the range AV •...
Page 459: Switchover Between Analog Input And General Port Functions
1.0 kΩ AN0–AN7 20 pF 1 MΩ Analog multiplexer A/D converter Note: All figures are reference values. Figure 14.9 Analog Input Pin Equivalent Circuit Table 14.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ...
Page 460: Section 15 Pin Function Controller (Pfc)
Section 15 Pin Function Controller (PFC) 15.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 15.1 lists the multiplexed pins.
Page 461 Table 15.1 List of Multiplexed Pins (cont) Function 1 Function 2 Function 3 Function 4 Pin No. Pin No. Port (Related Module) (Related Module) (Related Module) (Related Module) (FP-112) (TFP-120) IRQ7 input (INTC) PB15 I/O (port) — TP15 output (TPC) IRQ6 input (INTC) PB14 I/O (port) —...
Page 462: Register Configuration
SCI: Serial communication interface TPC: Programmable timing pattern controller Port: I/O port Notes: *1 The bus control register of the bus state controller handles switching between the two functions. *2 The function of port C pins automatically changes to analog input (AN0–AN7) when the A/D converter begins to operate.
Page 463: Port A Control Registers (Pacr1 And Pacr2)
Bit: Bit name: PA15 PA14 PA13 PA12 PA11 PA10 Initial value: R/W: Bit: Bit name: Initial value: R/W: 15.3.2 Port A Control Registers (PACR1 and PACR2) PACR1 and PACR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port A.
Page 464 Bit 15: Bit 14: PA15MD1 PA15MD0 Function Input/output (PA15) (Initial value) Interrupt request input (IRQ3) Reserved DMA transfer request input (DREQ1) • Bits 13 and 12 (PA14 Mode (PA14MD1 and PA14MD0)): PA14MD1 and PA14MD0 select the function of the PA14/IRQ2/DACK1 pin. Bit 13: Bit 12: PA14MD1...
Page 465 • Bits 7 and 6 (PA11 Mode (PA11MD1 and PA11MD0)): PA11MD1 and PA11MD0 select the function of the PA11/DPH/TIOCB1 pin. Bit 7: Bit 6: PA11MD1 PA11MD0 Function Input/output (PA11) (Initial value) Upper data bus parity input/output (DPH) ITU input capture/output compare (TIOCB1) Reserved •...
Page 466 PACR2: Bit: Bit name: — PA7MD — PA6MD — PA5MD — PA4MD Initial value: R/W: — — — — Bit: Bit name: PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value: R/W: • Bit 15 (Reserved): This bit is always read as 1. The write value should always be 1. •...
Page 467 • Bit 8 (PA4 Mode (PA4MD)): PA4MD selects the function of the PA4/WRL (WR) pin. Bit 8: PA4MD Function Input/output (PA4) Lower write output (WRL) or write output (WR) (Initial value) • Bits 7 and 6 (PA3 Mode (PA3MD1 and PA3MD0)): PA3MD1 and PA3MD0 select the function of the PA3/CS7/WAIT pin.
Page 468: Port B I/O Register (Pbior)
• Bits 1 and 0 (PA0 Mode (PA0MD1 and PA0MD0)): PA0MD1 and PA0MD0 select the function of the PA0/CS4/TIOCA0 pin. Bit 1: PA0MD1 Bit 0: PA0MD0 Function Input/output (PA0) Chip select output (CS4) (Initial value) ITU input capture/output compare (TIOCA0) Reserved 15.3.3 Port B I/O Register (PBIOR)
Page 469: Port B Control Registers (Pbcr1 And Pbcr2)
15.3.4 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port B. PBCR1 selects the function of the upper eight bits of port B; PBCR2 selects the function of the lower eight bits of port B.
Page 470 • Bits 11 and 10 (PB13 Mode (PB13MD1 and PB13MD0)): PB13MD1 and PB13MD0 select the function of the PB13/TP13/IRQ5/SCK1 pin. Bit 11: PB13MD1 Bit 10: PB13MD0 Function Input/output (PB13) (Initial value) Interrupt request input (IRQ5) Serial clock input/output (SCK1) Timing pattern output (TP13) •...
Page 471 • Bits 3 and 2 (PB9 Mode (PB9MD1 and PB9MD0)): PB9MD1 and PB9MD0 select the function of the PB9/TP9/TxD0 pin. Bit 3: PB9MD1 Bit 2: PB9MD0 Function Input/output (PB9) (Initial value) Reserved Transmit data output (TxD0) Timing pattern output (TP9) •...
Page 472 • Bits 15 and 14 (PB7 Mode (PB7MD1 and PB7MD0)): PB7MD1 and PB7MD0 select the function of the PB7/TP7/TOCXB4/TCLKD pin. Bit 15: Bit 14: PB7MD1 PB7MD0 Function Input/output (PB7) (Initial value) ITU timer clock input (TCLKD) ITU output compare (TOCXB4) Timing pattern output (TP7) •...
Page 473 • Bits 7 and 6 (PB3 Mode (PB3MD1 and PB3MD0)): PB3MD1 and PB3MD0 select the function of the PB3/TP3/TIOCB3 pin. Bit 7: PB3MD1 Bit 6: PB3MD0 Function Input/output (PB3) (Initial value) Reserved ITU input capture/output compare (TIOCB3) Timing pattern output (TP3) •...
Page 474: Column Address Strobe Pin Control Register (Cascr)
15.3.5 Column Address Strobe Pin Control Register (CASCR) CASCR is a 16-bit read/write register that allows selection between column address strobe and chip select pin functions. CASCR is initialized to H'5FFF by a power-on reset, but is not initialized by a manual reset, or in standby mode or sleep mode. Bit: Bit name: CASH...
Page 476: Section 16 I/O Ports (I/O)
Section 16 I/O Ports (I/O) 16.1 Overview There are three ports, A, B, and C. Ports A and B are 16-bit I/O ports, while port C is an 8-bit input port. The pins of the ports are all multiplexed for use as general-purpose I/Os (or inputs in the case of port C) or for other functions.
Page 477: Port A Data Register (Padr)
Table 16.1 Port A Register Name Abbreviation Initial Value Address* Access Size Port A data register PADR H'0000 H'5FFFFC0 8, 16, 32 Note: Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 16.2.2 Port A Data Register (PADR) PADR is a 16-bit read/write register that stores data for port A.
Page 478: Port B
16.3 Port B Port B is a 16-bit input/output port as shown in figure 16.2. (Input/output)/TP (Output)/IRQ7 (Input) (Input/output)/TP (Output)/IRQ6 (Input) (Input/output)/TP (Output)/IRQ5 (Input)/SCK1 (Input/output) (Input/output)/TP (Output)/IRQ4 (Input)/SCK0 (Input/output) (Input/output)/TP (Output)/TxD1 (Output) (Input/output)/TP (Output)/RxD1 (Input) (Input/output)/TP (Output)/TxD0 (Output) (Input/output)/TP (Output)/RxD0 (Input) Port B (Input/output)/TP (Output)/TOCXB4 (Output)/TCLKD (Input)
Page 479: Port B Data Register (Pbdr)
16.3.2 Port B Data Register (PBDR) PBDR is a 16-bit read/write register that stores data for port B. Bits PB15DR–PB0DR correspond to the PB15/TP15/IRQ7–PB0/TP0/TIOCA2 pins. When the pins are used as ordinary outputs, they will output whatever value is written in PBDR; when PBDR is read, the register value will be output regardless of the pin status.
Page 480: Port C
16.4 Port C Port C is an eight-bit input port as shown in figure 16.3. PC7 (Input)/AN7 (Input) PC6 (Input)/AN6 (Input) PC5 (Input)/AN5 (Input) PC4 (Input)/AN4 (Input) Port C PC3 (Input)/AN3 (Input) PC2 (Input)/AN2 (Input) PC1 (Input)/AN1 (Input) PC0 (Input)/AN0 (Input) Figure 16.3 Port C Configuration 16.4.1 Register Configuration...
Page 481: Port C Data Register (Pcdr)
16.4.2 Port C Data Register (PCDR) PCDR is an 16-bit read-only register that stores data for port C (writes to bits 15–8 are ignored, and the read value is always undefined). Bits PC7DR–PC0DR correspond to the PC7/AN7– PC0/AN0 pins respectively. Any values written to these bits will be ignored and will not affect the pin status.
Page 482: Section 17 Rom
Section 17 ROM 17.1 Overview The SH7034 microcomputer has 64 kbytes of on-chip ROM (mask ROM or PROM). The on-chip ROM is connected to the CPU and the direct memory access controller (DMAC) through a 32-bit data bus (figure 17.1). The CPU can access the on-chip ROM in 8-, 16- and 32-bit widths and the DMAC can access the ROM in 8- and 16-bit widths.
Page 483: Prom Mode
Table 17.1 Operating Modes and ROM Mode Setting Pins Operating Mode Area 0 Mode 0 (MCU mode 0) On-chip ROM disabled, external 8-bit space Mode 1 (MCU mode 1) On-chip ROM disabled, external 16-bit space Mode 2 (MCU mode 2) On-chip ROM enabled Mode 7 (PROM mode) —...
Page 484 SH7034 EPROM Socket HN27C101 Adapter Pin Name Pin Number Pin Number Pin Name I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A0/HBS PA2/CS6/TIOCB0 PA3/CS7/WAIT 15, 43, 70, 75, 83, 84, 99 • : PROM program power adapter (12.5 V) • A16–A0: Address input •...
Page 485: Prom Programming
Addresses in MCU Addresses in modes 0, 1, and 2 * PROM mode H'0000000 H'0000 On-chip ROM space (area 0) H'000FFFF H'FFFF Note: * Addresses in the figure are the uppermost shadow addresses of the on-chip ROM space. Figure 17.3 Memory Map of On-chip ROM 17.3 PROM Programming The write/verify specifications in PROM mode are the same as for the standard EPROM...
Page 486: Write/Verify And Electrical Characteristics
Table 17.2 Selecting PROM Programming Mode Mode I/O7–I/O0 A16–A0 Write Data input Address input Verify Data output Program inhibit High impedance Legend: 0: Low 1: High level level 17.3.2 Write/Verify and Electrical Characteristics Write/Verify: Write/verify can be accomplished by an efficient high-speed, high-reliability programming method.
Page 487 Start Set EPROM programmer to write/verify mode = 6.0 V ± 0.25 V, = 12.5 V ± 0.3 V) Address = 0 n = 0 n + 1 → n Data write = 0.2 ms ± 5%) n = 25? Address + 1 →...
Page 488 Electrical Characteristics: Tables 17.3 and 17.4 show the electrical characteristics of programming. Figure 17.5 shows the timing. Table 17.3 DC Characteristics (V = 6.0 V ± 0.25 V, V = 12.5 ± 0.3 V, V = 0 V, Ta = 25 ± 5˚C) Item Pins Symbol...
Page 489 Table 17.4 AC Characteristics (V = 6.0 V ± 0.25 V, V = 12.5 ± 0.3 V, V = 0 V, Ta = 25 ± 5˚C) Test Item Symbol Unit Conditions Figure 17.5 * Address setup time — — µs OE setup time —...
Page 490: Notes On Writing
1. Always write using the prescribed voltage and timing. The write voltage (programming voltage) V is 12.5 V (when the EPROM programmer is set to the Hitachi specifications for HN27C101, V is 12.5 V.) Applying a voltage in excess of the rated voltage may damage the device.
Page 491: Reliability After Writing
= 5.0 V) Mount on board Figure 17.6 Screening Flow If abnormalities are found when the program is written and verified or the program is read and checked after writing/verification or letting the chip stand at high temperature, contact Hitachi's engineering department.
Page 492: Section 18 Ram
18.1 Overview The SH7032 microcomputer has 8-kbytes of on-chip RAM; the SH7034 has 4 kbytes. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 18.1). The CPU can access data in the on-chip RAM in byte, word, or longword units. The DMAC can access byte or word data.
Page 493: Operation
(SH7034) are directed to the on-chip RAM. Memory area 7 (H'F000000–H'FFFFFFF) is divided into shadows in 8 kbyte units for the SH7032 and 4-kbyte units for the SH7034. All shadow accesses are on-chip RAM accesses. For more information on shadows, see section 8, Bus State...
Page 494: Section 19 Power-Down State
Section 19 Power-Down State 19.1 Overview In the power-down state, all CPU functions are halted. This lowers power consumption of the SH microprocessor dramatically. 19.1.1 Power-Down Modes The power-down state includes the following two modes: 1. Sleep mode 2. Standby mode Sleep mode and standby mode are entered from the program execution state according to the transition conditions given in table 19.1.
Page 495: Register
19.1.2 Register Table 19.2 summarizes the register related to the power-down state. Table 19.2 Standby Control Register (SBYCR) Name Abbreviation Initial Value Address* Access size Standby control register SBYCR H'1F H'5FFFFBC 8, 16, 32 Note: Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions.
Page 496: Sleep Mode
19.3 Sleep Mode 19.3.1 Transition to Sleep Mode Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register (SBYCR) is cleared to 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged.
Page 497 or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the states of these pins, see appendix B, Pin States. Table 19.3 Register States in Standby Mode Module Registers Initialized Registers That Hold Data Interrupt controller (INTC) —...
Page 498: Exiting Standby Mode
19.4.2 Exiting Standby Mode Standby mode is exited by an NMI interrupt, a power-on reset, or a manual reset. Exit by NMI: When a rising edge or falling edge (as selected by the NMIE bit in the interrupt control register (ICR) of the interrupt controller (INTC)) is detected at the NMI pin, the clock oscillator begins operating.
Page 499 Oscillator NMIE SSBY Clock setting time Exception Standby Oscillation Time exception handling mode start exception handling routine time handling SBY = 1 SLEEP instruction Figure 19.1 NMI Timing for Standby Mode (Example)
Page 500: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics 20.1 SH7032 and SH7034 Electrical Characteristics 20.1.1 Absolute Maximum Ratings Table 20.1 shows the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage –0.3 to +7.0 Program voltage –0.3 to +13.5 Input voltage (except port C) –0.3 to V...
Page 501 Table 20.2 DC Characteristics Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, AV ±10%, AV = 4.5 V to = 0 V, φ = 20 MHz, Ta = –20 to +75°C * ) = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Min Unit...
Page 502 Reference During A/D — = 5.0 V power supply conversion current While A/D — 0.01 µA converter is waiting RAM standby — — voltage Notes: *1 50 µA for the SH7032. *2 300 µA for the SH7032.
Page 503 Table 20.2 DC Characteristics (cont) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * ) = AV Note: * Regular-specification products;...
Page 504 During A/D — = 3.0 V power supply conversion — = 5.0 V current While A/D — 0.01 µA converter is waiting RAM standby — — voltage Notes: *1 50 µA for the SH7032. *2 300 µA for the SH7032.
Page 505 Usage Notes: 1. If the A/D converter is not used, do not leave the AV , and AV pins open. Connect and AV to V , and connect AV to V 2. Current dissipation values are for V min = V - 0.5 V and V max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state.
Page 506 Table 20.3 Permitted Output Current Values Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, Ta = –20 to +75°C * ) = AV Case B: V = 5.0 V ±10%, AV = 5.0 V ±10%, AV...
Page 507: Ac Characteristics
20.1.3 AC Characteristics The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. (1) Clock Timing Table 20.4 Clock Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV...
Page 508 1/2 V EXTAL Figure 20.1 EXTAL Input Timing Figure 20.2 System Clock Timing OSC2 OSC1 Figure 20.3 Oscillation Settling Time...
Page 509: Control Signal Timing
(2) Control Signal Timing Table 20.5 Control Signal Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, Ta = –20 to +75°C * ) = AV Case B: V = 5.0 V ±10%, AV...
Page 510 RESS RESS NMIRS RESW NMIRH Figure 20.4 Reset Input Timing NMIS NMIH IRQES IRQEH IRQ edge IRQLS IRQ level Figure 20.5 Interrupt Signal Input Timing IRQOD IRQOD IRQOUT Figure 20.6 Interrupt Signal Output Timing...
Page 511 BRQS BREQ BRQS (Input) BACD2 BACD1 BACK (Output) WR, RAS, CAS, CSn A21–A0 Figure 20.7 Bus Release Timing...
Page 512: Bus Timing
(3) Bus Timing Tables 20.6 to 20.8 show the bus timing. Table 20.6 Bus Timing (1) Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, AV ±10%, AV = 4.5 V to = 0 V, φ = 20 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products;...
Page 513 Table 20.6 Bus Timing (1) (cont) Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%,AV ±10%, AV = 4.5 V to = 0 V, φ = 20 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Unit...
Page 514 Table 20.6 Bus Timing (1) (cont) Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, AV ±10%, AV = 4.5 V to = 0 V, φ = 20 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Unit...
Page 515 A21–A0 HBS, LBS CSD2 CSD1 RDAC1 RD (Read) ACC1 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 × 0.65 – 20 (for 35% duty) or t × 0.5 – 20 (for 50% duty) instead Notes: *1 For t , use t RDAC1 of t –...
Page 516 A21–A0 HBS, LBS CSD2 CSD1 RDAC2 RD (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) × (n + 1.65) – 20 (for 35% duty) or t ×...
Page 517 A21–A0 HBS, LBS RDAC2 (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15–AD0 DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n+1.65) – 20 (for 35% duty) or t × (n+1.5) – 20 (for 50% duty) Notes: *1 For t , use t RDAC2...
Page 518 Column A21–A0 RASD1 RASD2 CASD1 RD(Read) WRH, WRL, WR(Read) DACD1 DACD2 DACK0 DACK1 (Read) CAC1 ACC1 RAC1 AD15–AD0 DPH, DPL (Read) RD(Write) WSD3 WSD4 WRH, WRL, WR(Write) WDD2 AD15–AD0 (Write) WPDH WPDD2 DPH, DPL (Write) DACD4 DACD5 DACK0 DACK1 (Write) ×...
Page 519 A21–A0 Row address Column address Column address Column address Column address RASD2 RASD1 RD(Read) WRH, WRL , WR (Read) CAC1 AD15–AD0 ACC1 RAC1 DPH, DPL (Read) DACD1 DACK0 DACD2 DACK1 (Read) × 0.65 – 19 (for 35% duty) or t Notes: *1 For t , use t x 0.5 –...
Page 520 Silent cycle A21–A0 Row address Column address Column address RASD2 RASD1 RD (Write) WSD3 WSD4 WRH, WRL , WR (Write) WDD2 AD15–AD0 DPH, DPL (Write) WPDD2 WPDH DPH, DPL (Write) DACD4 DACD5 DACD5 DACK0 DACK1 (Write) Figure 20.12 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode.
Page 521 Column A21–A0 RASD1 RASD2 CASD3 CASD2 RD(Read) WRH, WRL, WR(Read) CAC2 AD15–AD0 ACC2 RAC2 DPH, DPL (Read) DACD2 DACD1 DACK0 DACK1 (Read) RD(Write) WSD1 WSD2 WRH, WRL, WR(Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) ×...
Page 522 Column Column A21–A0 RASD1 RASD2 CASD2 CASD3 CASD3 RD(Read) WRH, WRL, WR (Read) CAC2 ACC2 AD15–AD0 RAC2 DPH, DPL (Read) DACD1 DACD2 DACD1 DACD2 DACK0 DACK1 (Read) RD(Write) WSD1 WSD2 WSD1 WSD2 WRH, WRL, WR(Write) WDD1 WDD1 AD15–AD0 (Write) WPDD1 WPDH WPDD1 WPDH...
Page 523 Column A21–A0 RD(Read) WRH, WRL, WR(Read) CAC2 ACC2 RAC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15–AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n + 1) – 25 instead of t × (n + 1) – t Notes: *1 For t , use t –...
Page 524 RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.16 CAS-before-RAS Refresh (Short-Pitch) RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.17 CAS-before-RAS Refresh (Long-Pitch)
Page 525 RASD2 RASD1 CASD3 CASD2 Figure 20.18 Self-Refresh...
Page 526 A21–A0 HBS, LBS CSD3 CSD4 AHD1 AHD2 (Read) RDAC3 AD15–AD0 Address Data (Read) (input) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 Data (output) Address (Write) DACD3 DACD3 DACK0 DACK1 (Write) WAIT Figure 20.19 Address/Data Multiplex I/O Bus Cycle...
Page 527 A21–A0 HBS, LBS CSD2 CSD1 WSD1 WSD4 WRH, WRL, WR (Write) DACD1 DACD2 DACK0 DACK1 (Write) Figure 20.20 DMA Single Transfer/One-State Access Write...
Page 528 Table 20.7 Bus Timing (2) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products;...
Page 529 Table 20.7 Bus Timing (2) (cont) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products;...
Page 530 Table 20.7 Bus Timing (2) (cont) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = AV ±10%, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products;...
Page 531 A21–A0 HBS, LBS CSD2 CSD1 RDAC1 RD (Read) ACC1 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 × 0.65 – 35 (for 35% duty) or t × 0.5 – 35 (for 50% duty) instead Notes: *1 For t , use t RDAC1 of t –...
Page 532 A21–A0 HBS, LBS CSD2 CSD1 RDAC2 RD (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) × (n + 1.65) – 35 (for 35% duty) or t ×...
Page 533 A21–A0 HBS, LBS RDAC2 (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15–AD0 DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n + 1.65) – 35 (for 35% duty) or t × (n + 1.5) – 35 (for Notes: *1 For t , use t RDAC2...
Page 534 Column A21–A0 RASD2 RASD1 CASD1 RD(Read) WRH, WRL, WR(Read) DACD1 DACD2 DACK0 DACK1 (Read) CAC1 ACC1 RAC1 AD15–AD0 DPH, DPL (Read) RD(Write) WSD3 WSD4 WRH, WRL, WR(Write) WDD2 AD15–AD0 (Write) WPDH WPDD2 DPH, DPL (Write) DACD4 DACD5 DACK0 DACK1 (Write) ×...
Page 535 A21–A0 Row address Column address Column address Column address Column address RASD2 RASD1 RD(Read) WRH, WRL , WR (Read) CAC1 AD15–AD0 ACC1 RAC1 DPH, DPL (Read) DACD1 DACK0 DACD2 DACK1 (Read) × 0.65 – 35 (for 35% duty) or t ×...
Page 536 Silent cycle A21–A0 Row address Column address Column address RASD2 RASD1 RD (Write) WSD3 WSD4 WRH, WRL , WR (Write) WDD2 AD15–AD0 DPH, DPL (Write) WPDD2 WPDH DPH, DPL (Write) DACD4 DACD5 DACD5 DACK0 DACK1 (Write) Figure 20.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode.
Page 537 Column A21–A0 RASD2 RASD1 CASD2 CASD3 RD(Read) WRH, WRL, WR(Read) CAC2 ACC2 AD15–AD0 RAC2 DPH, DPL (Read) DACD2 DACK0 DACD1 DACK1 (Read) RD(Write) WSD1 WSD2 WRH, WRL, WR(Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) ×...
Page 538 Column Column A21–A0 RASD1 RASD2 CASD2 CASD3 CASD3 RD(Read) WRH, WRL, WR(Read) CAC2 ACC2 AD15–AD0 RAC2 DPH, DPL (Read) DACD1 DACD2 DACD1 DACD2 DACK0 DACK1 (Read) RD(Write) WSD1 WSD2 WSD1 WSD2 WRH, WRL, WR(Write) WDD1 WDD1 AD15–AD0 (Write) WPDD1 WPDH WPDD1 WPDH DPH, DPL...
Page 539 A21–A0 Column RD(Read) WRH, WRL, WR(Read) CAC2 ACC2 RAC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15–AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n + 1) – 35 instead of t × (n + 1) – t Notes: *1 For t , use t –...
Page 540 RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.29 CAS-before-RAS Refresh (Short-Pitch) RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.30 CAS-before-RAS Refresh (Long-Pitch) RASD2 RASD1 CASD3 CASD2 Figure 20.31 Self-Refresh...
Page 541 A21–A0 HBS, LBS CSD3 CSD4 AHD1 AHD2 (Read) RDAC3 AD15–AD0 Address Data (Read) (input) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 Data (output) Address (Write) DACD3 DACD3 DACK0 DACK1 (Write) WAIT Figure 20.32 Address/Data Multiplex I/O Bus Cycle...
Page 542: Dmac Timing
A21–A0 HBS, LBS CSD2 CSD1 WSD1 WSD4 WRH, WRL, WR (Write) DACD1 DACD2 DACK0 DACK1 (Write) Figure 20.33 DMA Single Transfer/One-State Access Write (4) DMAC Timing Table 20.8 DMAC Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, Ta = –20 to +75°C *...
Page 543 DRQS DREQ0, DREQ1 level DRQS DRQH DREQ0, DREQ1 edge DRQS DREQ0, DREQ1 level release Figure 20.34 DREQ0, DREQ1 Input Timing (1) DREQ0, DREQ1 edge DRQW Figure 20.35 DREQ0, DREQ1 Input Timing (2)
Page 544: 16-Bit Integrated Timer Pulse Unit Timing
(5) 16-bit Integrated Timer Pulse Unit Timing Table 20.9 16-bit Integrated Timer Pulse Unit Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, Ta = –20 to +75°C * = AV Case B: V = 5.0 V ±10%, AV...
Page 545: Programmable Timing Pattern Controller And I/O Port Timing
TCKS TCKS TCLKA– TCLKD TCKWL TCKWH Figure 20.37 ITU Clock Input Timing (6) Programmable Timing Pattern Controller and I/O Port Timing Table 20.10 Programmable Timing Pattern Controller and I/O Port Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV...
Page 546: Watchdog Timer Timing
Ports A–C (Read) Ports A–C (Write) Figure 20.38 Programmable Timing Pattern Controller Output Timing (7) Watchdog Timer Timing Table 20.11 Watchdog Timer Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, φ...
Page 547: Serial Communication Interface Timing
(8) Serial Communication Interface Timing Table 20.12 Serial Communication Interface Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Case B: V = 5.0 V ±10%, AV...
Page 548: A/D Converter Timing
scyc SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 20.41 SCI I/O Timing (Synchronous Mode) (9) A/D Converter Timing Table 20.13 A/D Converter Timing Case A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, AV ±10%, AV = 3.0 V to AV = 0 V, φ...
Page 549 1 state ADTRG input TRGW TRGS TRGW ADST Figure 20.42 External Trigger Input Timing CONV Max. 14 states 3 states Address Analog input sampling signal Figure 20.43 Analog Conversion Timing...
Page 550: (10) Ac Characteristics Test Conditions
(10) AC Characteristics Test Conditions Microcomputer Device under output pin test output is set as follows for each pin. 30pF: CK, CASH, CASL, CS0–CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21–A0, AD15–AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and supporting module output pins other than the above.
Page 551: A/D Converter Characteristics
20.1.4 A/D Converter Characteristics Table 20.14 A/D Converter Characteristics Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, AV ±10%, AV = 4.5 V to = 0 V, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C 12.5 MHz 20 MHz Item...
Page 552: Sh7034B 3.3 V 12.5 Mhz Version And 20 Mhz Version Electrical Characteristics
SH7034B 3.3 V 12.5 MHz Version and 20 MHz Version * 20.2 Electrical Characteristics 20.2.1 Absolute Maximum Ratings Table 20.15 shows the absolute maximum ratings. Table 20.15 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage –0.3 to +4.6 Input voltage (except port C) –0.3 to V + 0.3...
Page 553 Table 20.16 DC Characteristics Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 to 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products only for 20 MHz version *2 Regular-specification products;...
Page 554 Table 20.16 DC Characteristics (cont) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 to 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products only for 20 MHz version *2 Regular-specification products;...
Page 555 Usage Notes: 1. If the A/D converter is not used, do not leave the AV , and AV pins open. Connect and AV to V , and connect AV to V 2. Current dissipation values are for V min = V - 0.5 V and V max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state.
Page 556 Table 20.17 Permitted Output Current Values Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C 12.5 MHz 20 MHz Item...
Page 557: Ac Characteristics
20.2.3 AC Characteristics The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. (1) Clock Timing Table 20.18 Clock Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C *...
Page 558 1/2 V EXTAL Figure 20.45 EXTAL Input Timing Figure 20.46 System Clock Timing OSC2 OSC1 Figure 20.47 Oscillation Settling Time...
Page 559: Control Signal Timing
(2) Control Signal Timing Table 20.19 Control Signal Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C 12.5 MHz 20 MHz Item...
Page 560 RESS RESS NMIRS RESW NMIRH Figure 20.48 Reset Input Timing NMIS NMIH IRQES IRQEH IRQ edge IRQLS IRQ level Figure 20.49 Interrupt Signal Input Timing IRQOD IRQOD IRQOUT Figure 20.50 Interrupt Signal Output Timing...
Page 561 BRQS BREQ BRQS (Input) BACD2 BACD1 BACK (Output) WR, RAS, CAS, CSn A21–A0 Figure 20.51 Bus Release Timing...
Page 562: Bus Timing
(3) Bus Timing Tables 20.20 show the bus timing. Table 20.20 Bus Timing (1) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products...
Page 563 Table 20.20 Bus Timing (1) (cont) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products *2 Regular-specification products;...
Page 564 Table 20.20 Bus Timing (1) (cont) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products *2 Regular-specification products;...
Page 565 Table 20.20 Bus Timing (2) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Unit...
Page 566 Table 20.20 Bus Timing (2) (cont) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Unit...
Page 567 Table 20.20 Bus Timing (2) (cont) Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C * = AV Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C Item Symbol Unit...
Page 568 A21–A0 HBS, LBS CSD2 CSD1 RDAC1 RD (Read) ACC1 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 × 0.65 – 20 (for 35% duty) or t × 0.5 – 20 (for 50% duty) instead Notes: *1 For t , use t RDAC1 of t –...
Page 569 A21–A0 HBS, LBS CSD2 CSD1 RDAC2 RD (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) × (n + 1.65) – 20 (for 35% duty) or t ×...
Page 570 A21–A0 HBS, LBS RDAC2 (Read) ACC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15–AD0 DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n+1.65) – 20 (for 35% duty) or t × (n+1.5) – 20 (for 50% duty) Notes: *1 For t , use t RDAC2...
Page 571 Column A21–A0 RASD1 RASD2 CASD1 RD(Read) WRH, WRL, WR(Read) DACD1 DACD2 DACK0 DACK1 (Read) CAC1 ACC1 RAC1 AD15–AD0 DPH, DPL (Read) RD(Write) WSD3 WSD4 WRH, WRL, WR(Write) WDD2 AD15–AD0 (Write) WPDH WPDD2 DPH, DPL (Write) DACD4 DACD5 DACK0 DACK1 (Write) ×...
Page 572 A21–A0 Row address Column address Column address Column address Column address RASD2 RASD1 RD(Read) WRH, WRL , WR (Read) CAC1 AD15–AD0 ACC1 RAC1 DPH, DPL (Read) DACD1 DACK0 DACD2 DACK1 (Read) × 0.65 – 19 (for 35% duty) or t Notes: *1 For t , use t x 0.5 –...
Page 573 Silent cycle A21–A0 Row address Column address Column address RASD2 RASD1 RD (Write) WSD3 WSD4 WRH, WRL , WR (Write) WDD2 AD15–AD0 DPH, DPL (Write) WPDD2 WPDH DPH, DPL (Write) DACD4 DACD5 DACD5 DACK0 DACK1 (Write) Figure 20.56 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode.
Page 574 Column A21–A0 RASD1 RASD2 CASD3 CASD2 RD(Read) WRH, WRL, WR(Read) CAC2 AD15–AD0 ACC2 RAC2 DPH, DPL (Read) DACD2 DACD1 DACK0 DACK1 (Read) RD(Write) WSD1 WSD2 WRH, WRL, WR(Write) WDD1 AD15–AD0 (Write) WPDH WPDD1 DPH, DPL (Write) DACD3 DACD3 DACK0 DACK1 (Write) ×...
Page 575 Column Column A21–A0 RASD1 RASD2 CASD2 CASD3 CASD3 RD(Read) WRH, WRL, WR (Read) CAC2 ACC2 AD15–AD0 RAC2 DPH, DPL (Read) DACD1 DACD2 DACD1 DACD2 DACK0 DACK1 (Read) RD(Write) WSD1 WSD2 WSD1 WSD2 WRH, WRL, WR(Write) WDD1 WDD1 AD15–AD0 (Write) WPDD1 WPDH WPDD1 WPDH...
Page 576 Column A21–A0 RD(Read) WRH, WRL, WR(Read) CAC2 ACC2 RAC2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15–AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) WAIT × (n + 1) – 25 instead of t × (n + 1) – t Notes: *1 For t , use t –...
Page 577 RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.60 CAS-before-RAS Refresh (Short-Pitch) RASD1 RASD2 CASD3 CASD2 WRH, WRL, Figure 20.61 CAS-before-RAS Refresh (Long-Pitch)
Page 578 RASD2 RASD1 CASD3 CASD2 Figure 20.62 Self-Refresh...
Page 579 A21–A0 HBS, LBS CSD3 CSD4 AHD1 AHD2 (Read) RDAC3 AD15–AD0 Address Data (Read) (input) DACD1 DACD2 DACK0 DACK1 (Read) WSD1 WSD2 WRH, WRL, WR (Write) WDD1 AD15–AD0 Data (output) Address (Write) DACD3 DACD3 DACK0 DACK1 (Write) WAIT Figure 20.63 Address/Data Multiplex I/O Bus Cycle...
Page 580 A21–A0 HBS, LBS CSD2 CSD1 WSD1 WSD4 WRH, WRL, WR (Write) DACD1 DACD2 DACK0 DACK1 (Write) Figure 20.64 DMA Single Transfer/One-State Access Write...
Page 581: Dmac Timing
(4) DMAC Timing Table 20.21 DMAC Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C * = AV Notes: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C 12.5 MHz 20 MHz Item...
Page 582: 16-Bit Integrated Timer Pulse Unit Timing
DREQ0, DREQ1 edge DRQW Figure 20.66 DREQ0, DREQ1 Input Timing (2) (5) 16-bit Integrated Timer Pulse Unit Timing Table 20.22 16-bit Integrated Timer Pulse Unit Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C * = AV...
Page 583: Programmable Timing Pattern Controller And I/O Port Timing
TCKS TCKS TCLKA– TCLKD TCKWL TCKWH Figure 20.68 ITU Clock Input Timing (6) Programmable Timing Pattern Controller and I/O Port Timing Table 20.23 Programmable Timing Pattern Controller and I/O Port Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ...
Page 584: Watchdog Timer Timing
(7) Watchdog Timer Timing Table 20.24 Watchdog Timer Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 to 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products only for 20 MHz version *2 Regular-specification products;...
Page 585: Serial Communication Interface Timing
(8) Serial Communication Interface Timing Table 20.25 Serial Communication Interface Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ = 12.5 to 20 MHz * , Ta = –20 to +75°C * = AV Notes: *1 ROMless products only for 20 MHz version *2 Regular-specification products;...
Page 586: A/D Converter Timing
scyc SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 20.72 SCI I/O Timing (Synchronous Mode) (9) A/D Converter Timing Table 20.26 A/D Converter Timing Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, φ...
Page 587 1 state ADTRG input TRGW TRGS TRGW ADST Figure 20.73 External Trigger Input Timing CONV Max. 14 states 3 states Address Analog input sampling signal Figure 20.74 Analog Conversion Timing...
Page 588: (10) Ac Characteristics Test Conditions
(10) AC Characteristics Test Conditions Microcomputer Device under output pin test output is set as follows for each pin. 30pF: CK, CASH, CASL, CS0–CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21–A0, AD15–AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and supporting module output pins other than the above.
Page 589: A/D Converter Characteristics
20.2.4 A/D Converter Characteristics Table 20.27 A/D Converter Characteristics Conditions: V = 3.3 V ±0.3V, AV = 3.3 V ±0.3V, AV ±0.3V, AV = 3.0 V to = 0 V, Ta = –20 to +75°C * = AV Notes: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C 12.5 MHz 20 MHz Item...
Page 590: Appendix A On-Chip Supporting Module Registers
Appendix A On-Chip Supporting Module Registers List of Registers The addresses and bit names of the on-chip supporting module registers are listed below. 16- and 32-bit registers are shown as two or four levels of 8 bits each.
Page 591 Table A.1 8-Bit Access Space (8-Bit and 16-Bit Accessible, 32-Bit Access Disabled) Bit Name Address Register 7 Module H'5FFFE00– — — — — — — — — — — H'5FFFEBF H'5FFFEC0 SMR0 STOP MP CKS1 CKS0 SCI (channel 0) H'5FFFEC1 BRR0 H'5FFFEC2 SCR0...
Page 592 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) Bit Name Address Register 7 Module H'5FFFF00 TSTR * — — — STR4 STR3 STR2 STR1 STR0 (chan- H'5FFFF01 TSNC * — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 nels 0–4 H'5FFFF02 TMDR * —...
Page 593 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register 7 Module H'5FFFF22 TCR3 * — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chan- nel 3) H'5FFFF23 TIOR3 * — IOB2 IOB1 IOB0 —...
Page 594 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register 7 Module H'5FFFF40 SAR0 * DMAC channel 0 H'5FFFF41 H'5FFFF42 H'5FFFF43 H'5FFFF44 DAR0 * H'5FFFF45 H'5FFFF46 H'5FFFF47 H'5FFFF48 DMAOR * — — — —...
Page 595 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register 7 Module H'5FFFF60 SAR2 * DMAC channel 2 H'5FFFF61 H'5FFFF62 H'5FFFF63 H'5FFFF64 DAR2 * H'5FFFF65 H'5FFFF66 H'5FFFF67 H'5FFFF68 — — — — — —...
Page 596 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register 7 Module H'5FFFF80– — — — — — — — — — INTC H'5FFFF83 H'5FFFF84 IPRA H'5FFFF85 H'5FFFF86 IPRB H'5FFFF87 H'5FFFF88 IPRC H'5FFFF89 H'5FFFF8A IPRD H'5FFFF8B H'5FFFF8C IPRE...
Page 597 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register Module H'5FFFFA0 BCR DRAME IOE WARP RDDTY BAS — — — H'5FFFFA1 — — — — — — — — H'5FFFFA2 WCR1 H'5FFFFA3 —...
Page 598 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) (cont) Bit Name Address Register Module H'5FFFFC0 PADR PA15 PA14 PA13 PA12 PA11 PA10 Port A H'5FFFFC1 H'5FFFFC2 PBDR PB15 PB14 PB13 PB12 PB11 PB10 Port B H'5FFFFC3 H'5FFFFC4 PAIOR PA15 PA14...
Page 599 Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-bit Accessible) (cont) Bit Name Address Register Module H'5FFFFD2– — — — — — — — — — H'5FFFFED H'5FFFFEE CASCR CASH CASH CASL CASL — — — — H'5FFFFEF —...
Page 600: Register Tables
Register Tables A.2.1 Serial Mode Register (SMR) • Start Address: H'5FFFEC0 (channel 0), H'5FFFEC8 (channel 1) • Bus Width: 8/16 Register Overview: Bit: Bit name: STOP CKS1 CKS0 Initial value: R/W: Table A.3 SMR Bit Functions Bit name Value* Description Communication mode (C/A) Asynchronous mode (Initial value)
Page 601: Bit Rate Register (Brr) Sci
A.2.2 Bit Rate Register (BRR) • Start Address: H'5FFFEC1 (channel 0), H'5FFFEC9 (channel 1) • Bus Width: 8/16 Register Overview: Bit: Bit name: Initial value: R/W: Table A.4 BBR Bit Functions Bit name Description 7–0 (Bit rate setting) Set serial transmission/reception bit rate A.2.3 Serial Control Register (SCR) •...
Page 602 Table A.5 SCR Bit Functions Bit Bit Name Value Description Transmit interrupt Transmit data-empty interrupt request (TXI) disabled enable (TIE) (Initial value) Transmit data-empty interrupt request (TXI) enabled Receive interrupt Receive-data-full interrupt request (RXI) and receive-error enable (RIE) interrupt request (ERI) disabled (Initial value) Receive-data-full interrupt request (RXI) and receive-error interrupt request (ERI)
Page 603: Transmit Data Register (Tdr) Sci
A.2.4 Transmit Data Register (TDR) • Start Address: H'5FFFEC3 (channel 0), H'5FFFECB (channel 1) • Bus Width: 8/16 Register Overview: Bit: Bit name: Initial value: R/W: Table A.6 TDR Bit Functions Bit name Description 7–0 (Transmit data storage) Store data for serial transmission A.2.5 Serial Status Register (SSR) •...
Page 604 Table A.7 SSR Bit Functions Bit name Value Description Transmit data Indicates that valid transmit data has been written to TDR register Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1; (2) empty Data written to TDR by DMAC (TDRE) Indicates that there is no valid transmit data in TDR (Initial value)
Page 605: Receive Data Register (Rdr) Sci
Table A.11 SSR Bit Functions (cont) Bit name Value Description Transmit end Indicates that transmission is in progress (TEND) Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1; (2) Data written to TDR by DMAC Indicates that transmission has ended (Initial value) Set Conditions: (1) Reset or standby mode;...
Page 606: A/D Data Register Ah-Dl (Addrah-Addrl) A/D
A.2.7 A/D Data Register AH–DL (ADDRAH–ADDRL) • Start Address: H'5FFFEE0, H'5FFFEE1, H'5FFFEE2, H'5FFFEE3, H'5FFFEE4, H'5FFFEE5, H'5FFFEE6, H'5FFFEE7 • Bus Width: 8/16 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: — — — — — — Initial value: R/W: Table A.8 ADDRAH–ADDRL Bit Functions...
Page 607 Table A.9 ADCSR Bit Functions Bit name Value Description A/D end flag (ADF) Clear conditions: (1) 0 written in ADF after reading ADF = 1; (2) DMAC started by ADI interrupt and A/D converter register is accessed (Initial value) Set Conditions: (1) Single mode: A/D conversion ends; (2) Scan mode: A/D conversion of all channels set has ended A/D interrupt enable...
Page 608: A/D Control Register (Adcr) A/D
A.2.9 A/D Control Register (ADCR) • Start Address: H'5FFFEE9 • Bus Width: 8/16 Register Overview: Bit: Bit name: TRGE — — — — — — — Initial value: R/W: — — — — — — — Table A.10 ADCR Bit Functions Bit name Value Description...
Page 609: Timer Synchronization Register (Tsnc) Itu
Table A.11 TSTR Bit Functions Bit name Value Description Counter start 4 (STR4) Count operation of TCNT4 stops (Initial value) TCNT4 counts Counter start 3 (STR3) Count operation of TCNT 3 stops (Initial value) TCNT3 counts Counter start 2 (STR2) Count operation of TCNT 2 stops (Initial value) TCNT2 counts...
Page 610 Table A.12 TSNC Bit Functions Bit name Value Description Timer sync 4 (SYNC4) Independent operation of channel 4 timer counter (TCNT4) (Initial value) (Preset/clear of TCNT4 is unrelated to other channels) Channel 4 operation is synchronous. TCNT4 sync preset/sync clear enabled. Timer sync 3 (SYNC3) Independent operation of channel 3 timer counter (TCNT3)
Page 611: Timer Mode Register (Tmdr) Itu
A.2.12 Timer Mode Register (TMDR) • Start Address: H'5FFFF02 • Bus Width: 8 Register Overview: Bit: Bit name: — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value: R/W: — Note: * Undetermined Table A.13 TMDR Bit Functions Bit name Value Description Phase counting mode (MDF) Channel 2 operates normally...
Page 612: Timer Function Control Register (Tfcr) Itu
A.2.13 Timer Function Control Register (TFCR) • Start Address: H'5FFFF03 • Bus Width: 8 Register Overview: Bit: Bit name: — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value: R/W: — — Note: * Undetermined Table A.14 TFCR Bit Functions Bit name Value Description...
Page 613: Timer Control Registers 0-4 (Tcr0-Tcr4) Itu
A.2.14 Timer Control Registers 0–4 (TCR0–TCR4) • Start Address: H'5FFFF04 (channel 0), H'5FFFF0E (channel 1), H'5FFFF18 (channel 2), H'5FFFF22 (channel 3), H'5FFFF32 (channel 4) • Bus Width: 8 Register Overview: Bit: Bit name: — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W:...
Page 614: Timer I/O Control Registers 0-4 (Tior0-Tior4) Itu
A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4) • Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2), H'5FFFF23 (channel 3), H'5FFFF33 (channel 4) • Bus Width: 8 Register Overview: Bit: Bit name: — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value:...
Page 615: Timer Interrupt Enable Registers 0-4 (Tier0-Tier4) Itu
A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4) • Start Address: H'5FFFF06 (channel 0), H'5FFFF10 (channel 1), H'5FFFF1A (channel 2), H'5FFFF24 (channel 3), H'5FFFF34 (channel 4), • Bus Width: 8 Register Overview: Bit: Bit name: — — — — — OVIE IMIEB IMIEA Initial value:...
Page 616: Timer Status Registers 0-4 (Tsr0-Tsr4) Itu
A.2.17 Timer Status Registers 0–4 (TSR0–TSR4) • Start Address: H'5FFFF07 (channel 0), H'5FFFF11 (channel 1), H'5FFFF1B (channel 2), H'5FFFF25 (channel 3), H'5FFFF35 (channel 4), • Bus Width: 8 Register Overview: Bit: Bit name: — — — — — IMFB IMFA Initial value: R/(W) * R/(W) *...
Page 617: Timer Counter 0-4 (Tcnt0-Tcnt4) Itu
A.2.18 Timer Counter 0–4 (TCNT0–TCNT4) • Start Address: H'5FFFF08 (channel 0), H'5FFFF12 (channel 1), H'5FFFF1C (channel 2), H'5FFFF26 (channel 3), H'5FFFF36 (channel 4) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.19 TCNT0–TCNT4 Bit Functions Bit name...
Page 618: General Registers A0-4 (Gra0-Gra4) Itu
A.2.19 General Registers A0–4 (GRA0–GRA4) • Start Address: H'5FFFF0A (channel 0), H'5FFFF14 (channel 1), H'5FFFF1E (channel 2), H'5FFFF28 (channel 3), H'5FFFF38 (channel 4) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.20 GRA0–GRA4 Bit Functions Bit name...
Page 619: General Registers B0-4 (Grb0-Grb4) Itu
A.2.20 General Registers B0–4 (GRB0–GRB4) • Start Address: H'5FFFF0C (channel 0), H'5FFFF16 (channel 1), H'5FFFF20 (channel 2), H'5FFFF2A (channel 3), H'5FFFF3A (channel 4) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.21 GRB0–GRB4 Bit Functions Bit name...
Page 620: Buffer Registers A3, 4 (Bra3, Bra4) Itu
A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) • Start Address: H'5FFFF2C (channel 3), H'5FFFF3C (channel 4) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.22 BRA3, BRA4 Bit Functions Bit name Description 15–0...
Page 621: Buffer Registers B3, 4 (Brb3, Brb4) Itu
A.2.22 Buffer Registers B3, 4 (BRB3, BRB4) • Start Address: H'5FFFF2E (channel 3), H'5FFFF3E (channel 4) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.23 BRB3, BRB4 Bit Functions Bit name Description 15–0...
Page 622: Timer Output Control Register (Tocr) Itu
A.2.23 Timer Output Control Register (TOCR) • Start Address: H'5FFFF31 • Bus Width: 8 Register Overview: Bit: Bit name: — — — — — — OLS4 OLS3 Initial value: R/W: — — — — — — Note: * Undetermined Table A.24 TOCR Bit Functions Bit name Value Description...
Page 623: Dma Source Address Registers 0-3 (Sar0-Sar3) Dmac
A.2.24 DMA Source Address Registers 0–3 (SAR0–SAR3) DMAC • Start Address: H'5FFFF40 (channel 0), H'5FFFF50 (channel 1), H'5FFFF60 (channel 2), H'5FFFF70 (channel 3) • Bus Width: 16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name:...
Page 624: Dma Destination Address Registers 0-3 (Dar0-Dar3) Dmac
A.2.25 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMAC • Start Address: H'5FFFF44 (channel 0), H'5FFFF54 (channel 1), H'5FFFF64 (channel 2), H'5FFFF74 (channel 3) • Bus Width: 16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Bit: Bit name:...
Page 625: Dma Transfer Count Registers 0-3 (Tcr0-Tcr3) Dmac
A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMAC • Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2), H'5FFFF7A (channel 3) • Bus Width: 16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Note: * Undetermined Table A.27 TCR0–TCR3 Bit Functions...
Page 626: Dma Channel Control Registers 0-3 (Chcr0-Chcr3) Dmac
A.2.27 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMAC • Start Address: H'5FFFF4E (channel 0), H'5FFFF5E (channel 1), H'5FFFF6E (channel 2), H'5FFFF7E (channel 3) • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W * R/W * R/W *...
Page 627 Table A.28 CHCR0–CHCR3 Bit Functions Bit name Value Description 15,14 Destination address Destination address is fixed (Initial value) mode bits 1, 0 (DM1, Destination address incremented (+1 for byte transfer; DM0) +2 for word transfer) Destination address decremented (–1 for byte transfer;...
Page 628 Table A.28 CHCR0–CHCR3 Bit Functions (cont) Bit name Value Description 11–8 Resource select bits 1 0 1 1 IMIA3 (input capture A/compare match A interrupt request of on-chip ITU3) * 3–0 (RS3–RS0) (cont) 1 1 0 0 Auto request (transfer request automatically generated within DMAC) * 1 1 0 1 ADI (A/D conversion end interrupt request of on-chip A/D converter)
Page 629: Dma Operation Registers (Dmaor) Dmac
A.2.28 DMA Operation Registers (DMAOR) DMAC • Start Address: H'5FFFF48 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: — — — — — — Initial value: R/W: — — — — — — Bit: Bit name: — — — —...
Page 630: Interrupt Priority Setting Register A (Ipra) Intc
A.2.29 Interrupt Priority Setting Register A (IPRA) INTC • Start Address: H'5FFFF84 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.30 IPRA Bit Functions Bit name Description 15–12 (Set IRQ0 priority level) Sets the IRQ0 priority level value 11–8 (Set IRQ1 priority level)
Page 631: Interrupt Priority Setting Register B (Iprb) Intc
A.2.30 Interrupt Priority Setting Register B (IPRB) INTC • Start Address: H'5FFFF86 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.31 IPRB Bit Functions Bit name Description 15–12 (Set IRQ4 priority level) Sets the IRQ4 priority level value 11–8 (Set IRQ5 priority level)
Page 632: Interrupt Priority Setting Register C (Iprc) Intc
A.2.31 Interrupt Priority Setting Register C (IPRC) INTC • Start Address: H'5FFFF88 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.32 IPRC Bit Functions Bit name Description 15–12 (Set DMAC0 and DMAC1 priority Sets the DMAC0 and DMAC1 priority level values levels) 11–8...
Page 633: Interrupt Priority Setting Register D (Iprd) Intc
A.2.32 Interrupt Priority Setting Register D (IPRD) INTC • Start Address: H'5FFFF8A • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.33 IPRD Bit Functions Bit name Description 15–12 (Set ITU2 priority level) Sets the ITU2 priority level value 11–8 (Set ITU3 priority level)
Page 634: Interrupt Priority Setting Register E (Ipre) Intc
A.2.33 Interrupt Priority Setting Register E (IPRE) INTC • Start Address: H'5FFFF8C • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: — — — — Initial value: R/W: — — — — Table A.34 IPRE Bit Functions Bit name Description 15–12...
Page 635: Interrupt Control Register (Icr) Intc
A.2.34 Interrupt Control Register (ICR) INTC • Start Address: H'5FFFF8E • Bus Width: 8/16/32 Register Overview: Bit: Bit name: NMIL — — — — — — NMIE Initial value: R/W: — — — — — — Bit: Bit name: IRQ0S IRQ1S IRQ2S IRQ3S...
Page 636: Break Address Register H (Barh) Ubc
A.2.35 Break Address Register H (BARH) • Start Address: H'5FFFF90 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 Initial value: R/W: Bit: Bit name: BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Initial value: R/W:...
Page 637: Break Address Register L (Barl) Ubc
A.2.36 Break Address Register L (BARL) • Start Address: H'5FFFF92 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: BA15 BA14 BA13 BA12 BA11 BA10 Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.37 BARL Bit Functions Bit name Description 15–0 Set break address bits 15–0...
Page 638: Break Address Mask Register H (Bamrh) Ubc
A.2.37 Break Address Mask Register H (BAMRH) • Start Address: H'5FFFF94 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 Initial value: R/W: Bit: Bit name: BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value:...
Page 639: Break Address Mask Register L (Bamrl) Ubc
A.2.38 Break Address Mask Register L (BAMRL) • Start Address: H'5FFFF96 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 Initial value: R/W: Bit: Bit name: BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Initial value:...
Page 640: Break Bus Cycle Register (Bbr) Ubc
A.2.39 Break Bus Cycle Register (BBR) • Start Address: H'5FFFF98 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — — Bit: Bit name: Initial value: R/W: Table A.40 BBR Bit Functions...
Page 641: Bus Control Register (Bcr) Bsc
A.2.40 Bus Control Register (BCR) • Start Address: H'5FFFFA0 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: DRAME WARP RDDTY — — — Initial value: R/W: — — — Bit: Bit name: — — — — — — — —...
Page 642: Wait State Control Register 1 (Wcr1) Bsc
A.2.41 Wait State Control Register 1 (WCR1) • Start Address: H'5FFFFA2 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: Initial value: R/W: Bit: Bit name: — — — — — — — Initial value: R/W * R/W: — — —...
Page 643: Wait State Control Register 2 (Wcr2) Bsc
Table A.42 Bit Functions (cont) Description DRAM Space Area 1 External Memory Space Bit Name Value (BCRDRAME = 1) (BCRDRAME = 1) Write wait Column address cycle: 1 cycle Setting prohibited state control (short-pitch) (WW1) Wait state is 2 cycles + WAIT Column address cycle: Wait state is 2 cycles + WAIT (long-pitch) (Initial value)
Page 644 Table A.43 WCR2 Bit Functions Description Number of Single Mode DMA External Space Cycle States WAIT Pin External DRAM Multiplex Bit Name Value Signal Input Memory Space Space • Areas 1, 3–5, 7: 15–8 Single mode Not sampled Column Wait state is 4 fixed at 1 cycle DMA memory during single...
Page 645: Wait State Control Register 3 (Wcr3) Bsc
A.2.43 Wait State Control Register 3 (WCR3) • Start Address: H'5FFFFA6 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: A02LW1 A02LW0 A6LW1 A6LW0 — — — Initial value: R/W: — — — Bit: Bit name: — — — — —...
Page 646: Dram Area Control Register (Dcr) Bsc
A.2.44 DRAM Area Control Register (DCR) • Start Address: H'5FFFFA8 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: RASD CDTY MXC1 MXC0 Initial value: R/W: Bit: Bit name: — — — — — — — — Initial value: R/W: —...
Page 647 Table A.45 DCR Bit Functions Bit Name Value Description 2-CAS system: CASH, CASL, and WRL signals are 2-CAS system/2-WE system (CW2) valid (Initial value) 2-WE system: CASL, WRH, and WRL signals are valid RAS up mode: Returns RAS signal to high and waits RAS down (RASD) for next DRAM access (Initial value)
Page 648: Parity Control Register (Pcr) Bsc
A.2.45 Parity Control Register (PCR) • Start Address: H'5FFFFAA • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PFRC PCHK1 PCHK0 — — — Initial value: R/W: — — — Bit: Bit name: — — — — — — — —...
Page 649: Refresh Control Register (Rcr) Bsc
A.2.46 Refresh Control Register (RCR) • Start Address: H'5FFFFAC • Bus Width: 8/16/32 (read), 16 (write) Register Overview: Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — — Bit: Bit name: RFSHE RMODE...
Page 650: Refresh Timer Control/Status Register (Rtcsr) Bsc
A.2.47 Refresh Timer Control/Status Register (RTCSR) • Start Address: H'5FFFFAE • Bus Width: 8/16/32 (read), 16 (write) Register Overview: Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — —...
Page 651: Refresh Timer Counter (Rtcnt) Bsc
A.2.48 Refresh Timer Counter (RTCNT) • Start Address: H'5FFFFB0 • Bus Width: 8/16/32 (read), 16 (write) Register Overview: Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — — Bit: Bit name: Initial value:...
Page 652: Refresh Timer Constant Register (Rtcor) Bsc
A.2.49 Refresh Timer Constant Register (RTCOR) • Start Address: H'5FFFFB2 • Bus Width: 8/16/32 (read), 16 (write) Register Overview: Bit: Bit name: — — — — — — — — Initial value: R/W: — — — — — — — —...
Page 653 Table A.51 TCSR Bit Functions Bit Name Value Description Overflow flag (OVF) No TCNT overflow in interval timer mode (Initial value) Clear Condition: OVF read, then 0 written in OVF TCNT overflow generated in interval timer mode Timer mode select (WT/IT) Interval timer mode: When TCNT overflows, interval timer interrupt (ITI) request sent to CPU (Initial value) Watchdog timer mode: When TCNT overflows,...
Page 654: Timer Counter (Tcnt) Wdt
A.2.51 Timer Counter (TCNT) • Start Address: H'5FFFFB9 (read), H'5FFFFB8 (write) • Bus Width: 8 (read), 16 (write) Register Overview: Bit: Bit name: Initial value: R/W: Table A.52 TCNT Bit Functions Bit Name Description 7–0 Count value Input clock count value A.2.52 Reset Control/Status Register (RSTCSR) •...
Page 655: Standby Control Register (Sbycr) Power-Down State
Table A.53 RSTCSR Bit Functions Bit Name Value Description Watchdog timer overflow flag No TCNT overflow in watchdog timer mode (WOVF) (Initial value) Clear Condition: WOVF read, then 0 written in WOVF TCNT overflow generated in watchdog timer mode No internal reset when TCNT overflows * Reset enable (RSTE) (Initial value) Internal reset when TCNT overflows...
Page 656: Port A Data Register (Padr) Port A
A.2.54 Port A Data Register (PADR) Port A • Start Address: H'5FFFFC0 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR Initial value: R/W: Bit: Bit name: PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value:...
Page 657: Port B Data Register (Pbdr) Port B
A.2.55 Port B Data Register (PBDR) Port B • Start Address: H'5FFFFC2 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/W: Bit: Bit name: PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value:...
Page 658: Port C Data Register (Pcdr) Port C
A.2.56 Port C Data Register (PCDR) Port C • Start Address: H'5FFFFD0 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: — — — — — — — — Initial value: — — — — — — — — R/W: Bit: Bit name: PC7DR...
Page 659: Port A I/O Register (Paior) Pfc
A.2.57 Port A I/O Register (PAIOR) • Start Address: H'5FFFFC4 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PA15 PA14 PA13 PA12 PA11 PA10 Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.58 PAIOR Bit Functions Bit Name Value Description 15–0...
Page 660: Port B I/O Register (Pbior) Pfc
A.2.58 Port B I/O Register (PBIOR) • Start Address: H'5FFFFC6 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PB15 PB14 PB13 PB12 PB11 PB10 Initial value: R/W: Bit: Bit name: Initial value: R/W: Table A.59 PBIOR Bit Functions Bit Name Value Description 15–0...
Page 661: Port A Control Register 1 (Pacr1) Pfc
A.2.59 Port A Control Register 1 (PACR1) • Start Address: H'5FFFFC8 • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PA15 PA15 PA14 PA14 PA13 PA13 PA12 PA12 Initial value: R/W: Bit: Bit name: PA11 PA11 PA10 PA10 — Initial value: R/W: —...
Page 662 Table A.60 PACR1 Bit Functions Bit Name Value Description 15,14 PA15 mode bits 1,0 General-purpose input/output (PA15) (Initial value) (PA15MD1, PA15MD0) Interrupt request input (IRQ3) Reserved DMA transfer request input (DREQ1) 13,12 PA14 mode bits 1,0 General-purpose input/output (PA14) (PA14MD1, PA14MD0) Interrupt request input (IRQ2) Reserved DMA transfer request acknowledge output (DACK1)
Page 663: Port A Control Register 2 (Pacr2) Pfc
A.2.60 Port A Control Register 2 (PACR2) • Start Address: H'5FFFFCA • Bus Width: 8/16/32 Register Overview: Bit: Bit name: — PA7MD — PA6MD — PA5MD — PA4MD Initial value: R/W: — — — — Bit: Bit name: PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value: R/W:...
Page 664 Table A.61 PACR2 Bit Functions Bit Name Value Description PA7 mode bit (PA7MD) General-purpose input/output (PA7) Bus request acknowledge output (BACK) (Initial value) PA6 mode bit (PA6MD) General-purpose input/output (PA6) Read output (RD) (Initial value) PA5 mode bit (PA5MD) General-purpose input/output (PA5) High write output (WRH) or low byte strobe output (LBS) (Initial value) PA4 mode bit (PA4MD)
Page 665: Port B Control Register 1 (Pbcr1) Pfc
A.2.61 Port B Control Register 1 (PBCR1) • Start Address: H'5FFFFCC • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PB15 PB15 PB14 PB14 PB13 PB13 PB12 PB12 Initial value: R/W: Bit: Bit name: PB11 PB11 PB10 PB10 Initial value: R/W:...
Page 666 Table A.62 PBCR1 Bit Functions Bit Name Value Description 15,14 PB15 mode bits 1,0 General-purpose input/output (PB15) (Initial value) (PB15MD1, PB15MD0) Interrupt request input (IRQ7) Reserved Timing pattern output (TP15) 13,12 PB14 mode bits 1,0 General-purpose input/output (PB14) (Initial value) (PB14MD1, PB14MD0) Interrupt request input (IRQ6) Reserved...
Page 667: Port B Control Register 2 (Pbcr2) Pfc
A.2.62 Port B Control Register 2 (PBCR2) • Start Address: H'5FFFFCE • Bus Width: 8/16/32 Register Overview: Bit: Bit name: PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: Bit name: PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value: R/W:...
Page 668 Table A.63 PBCR2 Bit Functions Bit Name Value Description 15,14 PB7 mode bits 1,0 General-purpose input/output (PB7) (Initial value) (PB7MD1, PB7MD0) ITU timer clock input (TCLKD) ITU output compare output (TOCXB4) Timing pattern output (TP7) 13,12 PB6 mode bits 1,0 General-purpose input/output (PB6) (Initial value) (PB6MD1, PB6MD0)
Page 669: Column Address Strobe Pin Control Register (Cascr) Pfc
A.2.63 Column Address Strobe Pin Control Register (CASCR) • Start Address: H'5FFFFEE • Bus Width: 8/16/32 Register Overview: Bit: Bit name: CASH CASH CASL CASL — — — — Initial value: R/W: — — — — Bit: Bit name: — —...
Page 670: Tpc Output Mode Register (Tpmr) Tpc
A.2.64 TPC Output Mode Register (TPMR) • Start Address: H'5FFFFF0 • Bus Width: 8/16 Register Overview: Bit: Bit name: — — — — G3NOV G2NOV G1NOV G0NOV Initial value: R/W: — — — — Table A.65 TPMR Bit Functions Bit Name Value Description Group 3 non- TPC output group 3 operates normally (the output value is...
Page 671: Tpc Output Control Register (Tpcr) Tpc
A.2.65 TPC Output Control Register (TPCR) • Start Address: H'5FFFFF1 • Bus Width: 8/16 Register Overview: Bit: Bit name: G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value: R/W:...
Page 672 Table A.66 TPCR Bit Functions Bit Bit Name Value Description 7,6 Group 3 compare match sel- The output trigger of TPC output group 3 (pins TP15– ect 1, 0 (G3CMS1, G3CMS0) TP12) is the ITU channel 0 compare match The output trigger of TPC output group 3 (pins TP15– TP12) is the ITU channel 1 compare match The output trigger of TPC output group 3 (pins TP15–...
Page 673: Next Data Enable Register A (Ndera) Tpc
A.2.66 Next Data Enable Register A (NDERA) • Start Address: H'5FFFFF3 • Bus Width: 8/16 Register Overview: Bit: Bit name: NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value: R/W: Table A.67 NDERA Bit Functions Bit Name Value Description 7–0 Next data enable 7–0 Disable TPC output TP7–TP0 disabled (Initial value)
Page 674: Next Data Register A (Ndra) Tpc
A.2.68 Next Data Register A (NDRA) (When the Output Triggers of TPC Output Groups 0 and 1 are the Same) • Start Address: H'5FFFFF5 • Bus Width: 8/16 Register Overview: Bit: Bit name: NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value: R/W:...
Page 675: (When The Output Triggers Of Tpc Output Groups 0 And 1 Are Different)
A.2.70 Next Data Register A (NDRA) (When the Output Triggers of TPC Output Groups 0 and 1 are Different) • Start Address: H'5FFFFF5 • Bus Width: 8/16 Register Overview: Bit: Bit name: NDR7 NDR6 NDR5 NDR4 — — — — Initial value: R/W: —...
Page 676: (When The Output Triggers Of Tpc Output Groups 2 And 3 Are The Same)
A.2.72 Next Data Register B (NDRB) (When the Output Triggers of TPC Output Groups 2 and 3 are the Same) • Start Address: H'5FFFFF4 • Bus Width: 8/16 Register Overview: Bit: Bit name: NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value: R/W:...
Page 677: Next Data Register B (Ndrb) Tpc
A.2.74 Next Data Register B (NDRB) (When the Output Triggers of TPC Output Groups 2 and 3 are Different) • Start Address: H'5FFFFF4 • Bus Width: 8/16 Register Overview: Bit: Bit name: NDR15 NDR14 NDR13 NDR12 — — — — Initial value: R/W: —...
Page 678: Register Status In Reset And Power-Down States
Register Status in Reset and Power-Down States Table A.77 Register Status in Reset and Power-Down States Reset State Power-Down State Category Abbreviation Power On Manual Standby Sleep R0–R15 Initialized Initialized Held Held MACH,MACL Interrupt controller (INTC) IPRA–IPRE Initialized Initialized Held Held User break controller (UBC) BARH,BARL Initialized...
Page 679 Table A.77 Register Status in Reset and Power-Down States (cont) Reset State Power-Down State Category Abbreviation Power On Manual Standby Sleep 16-bit integrated timer pulse TSTR Initialized Initialized Initialized Held unit (ITU) TSNC TMDA, TMDB TCNT0–TCNT4 GRA0–GRA4, GRB0–GRB4 BRA3, BRA4. BRB3, BRB4 TCR0–TCR4 TIOR0–TIOR4...
Page 680 Table A.78 Register Status in Reset and Power-Down States (cont) Reset State Power-Down State Category Abbreviation Power On Manual Standby Sleep A/D converter ADDRA– Initialized Initialized Initialized Held ADDRD ADCSR ADCR Pin function controller PAIOR,PBIOR Initialized Held Held Held (PFC) PACR1,PACR2, PBCR1,PBCR2 CASCR...
Page 681: Appendix B Pin States
Appendix B Pin States Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State Pin State Reset Power-Down Category Power-On Manual Standby Sleep Released Clock System control WDTOVF BREQ — BACK Interrupt IRQ7–IRQ0 — IRQOUT — Address bus A21–A0 Data bus AD15–AD0 DPH,DPL...
Page 682 Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State (cont) Pin State Reset Power-Down Category Power-On Manual Standby Sleep Released Serial communication TxD0–TxD1 — interface (SCI) RxD0,RxD1 — SCK0,SCK1 — A/D converter AN7–AN0 ADTRG — I/O ports PA14, PA12, —...
Page 683 The following table shows the states of bus control pins and external bus pins in accesses of various address spaces. Table B.2 Pin States in Address Space Accesses On-Chip Peripheral Modules 16-Bit Space On-Chip On-Chip 8-Bit Upper Lower Pin Name ROM Space RAM Space Space...
Page 684 Table B.2 Pin States in Address Space Accesses (cont) Address/Data Multiplex I/O Space 16-Bit Space WRH, WRL, A0 System WR, HBS, LBS System 8-Bit Upper Lower Upper Lower Pin Name Space Byte Byte Word Byte Byte Word CS7, CS5– High High High High...
Page 685 Table B.2 Pin States in Address Space Accesses (cont) DRAM Space 16-Bit Space 2-CAS System 2-WE System 8-Bit Upper Lower Upper Lower Pin Name Space Byte Byte Word Byte Byte Word CS7–CS2, High High High High High High High — —...
Page 686 Table B.2 Pin States in Address Space Accesses (cont) External Memory Space 16-Bit Space WRH, WRL, A0 System WR, HBS, LBS System 8-Bit Upper Lower Upper Lower Pin Name Space Byte Byte Word Byte Byte Word CS7–CS0 Valid Valid Valid Valid Valid Valid...
Page 687: Appendix C Package Dimensions
Unit: mm 23.2 ± 0.3 0.32 ± 0.08 0.13 M 0.30 ± 0.06 1.23 0° – 8° 0.8 ± 0.3 0.10 Hitachi Code FP-112 JEDEC — * Dimension including the plating thickness JEITA Conforms Mass (reference value) 2.4 g Base material dimension...
Page 688 Unit: mm 16.0 ± 0.2 * 0.17 ± 0.05 0.07 0.15 ± 0.04 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code TFP-120 JEDEC — JEITA Conforms Dimension including the plating thickness Base material dimension Mass (reference value) 0.5 g...
Page 690 Publication Date: 1st Edition, September 1994 6th Edition, September 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1994. All rights reserved. Printed in Japan.

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Hitachi SH7032 Hardware Manual

Table of Contents

Overview

Section 2 CPU

Section 3 Operating Modes

Section 4 Exception Handling

Interrupt Controller (INTC)

User Break Controller (UBC)

Clock Pulse Generator (CPG)

Bus State Controller (BSC)

Direct Memory Access Controller (DMAC)

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)

Section 11 Programmable Timing Pattern Controller (TPC)

Section 12 Watchdog Timer (WDT)

Section 13 Serial Communication Interface (SCI)

Section 14 A/D Converter

Section 15 Pin Function Controller (PFC)

Section 16 I/O Ports (I/O)

Section 17 ROM

Section 18 RAM

Section 19 Power-Down State

Section 20 Electrical Characteristics

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Summary of Contents for Hitachi SH7032