Timer Status Register (Tsr) - Hitachi SH7032 Hardware Manual

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10.2.11 Timer Status Register (TSR)

The timer status register (TSR) is an eight-bit read/write register containing flags that indicate

timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or

input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit

in the timer interrupt enable register (TIER), an interrupt request is sent to the CPU. TSR is

initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU channel has one TSR.

Table 10.9 Timer Status Register (TSR)

Initial value:

Notes: *1 Undefined

*2 Only 0 can be written, to clear the flag.

• Bits 7–3 (Reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value

to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.

• Bit 2 (Overflow Flag (OVF)): OVF indicates that a TCNT overflow/underflow has occurred.

Note: A TCNT underflow occurs when the TCNT up/down-counter is functioning. It may occur in

the following cases: (1) When channel 2 is set to phase counting mode (MDF bit in TMDR is

1), or (2) when channel 3 and 4 are set to complementary PWM mode (CMD1 bit in TFCR

is 1 and CMD0 bit is 0).

Abbreviation

Clearing condition: Read OVF when OVF = 1, then write 0 in OVF

Setting condition: TCNT overflow from H'FFFF to H'0000 or underflow

from H'0000 to H'FFFF

TSR indicates input capture, compare match and

overflow status.

(Initial value)

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