Hitachi HD6417032 Manuals

Manuals and User Guides for Hitachi HD6417032. We have 1 Hitachi HD6417032 manual available for free PDF download: Hardware Manual

Hitachi HD6417032 Hardware Manual (690 pages)

SuperH RISC Engine

Brand: Hitachi | Category: Computer Hardware | Size: 2.58 MB

Table of Contents

22
- Overview
  
  36
  - Superh Microcomputer Features
    36
    
    Operating
    38
    
    Modes Internal
    39
    
    Clock
    40
  - Block Diagram
    43
    
    Timers
    43
  - Pin Descriptions
    44
    
    Pin Arrangement
    44
    
    Pin Functions
    46
    
    Data
    48
    
    Pin Layout by Mode
    50
    
    Pins
    50
- Section 2 CPU
  
  52
  - Register Configuration
    52
    
    General Registers (Rn)
    52
    
    Control Registers
    53
    
    Initial Values of Registers
    54
    
    System Registers
    54
  - Data Formats
    55
    
    Data Format in Memory
    55
    
    Data Format in Registers
    55
    
    Immediate Data Format
    56
  - Instruction Features
    56
    
    RISC-Type Instruction Set
    56
    
    Addressing Modes
    59
    
    Instruction Formats
    62
  - Instruction Set
    66
    
    Instruction Set by Classification
    66
    
    Operation Code Map
    77
  - CPU State
    80
    
    State Transitions
    80
    
    Power-Down State
    83
- Section 3 Operating Modes
  
  84
  - Types of Operating Modes and Their Selection
    84
  - Operating Mode Descriptions
    84
    
    Mode 0 (MCU Mode 0)
    84
    
    Mode 1 (MCU Mode 1)
    84
    
    Mode 2 (MCU Mode 2)
    84
    
    Mode 7 (PROM Mode)
    84
- Section 4 Exception Handling
  
  86
  - Overview
    86
    
    Exception Handling Types and Priorities
    86
    
    Exception Handling Operation
    88
    
    Exception Vector Table
    89
  - Resets
    91
    
    Reset Types
    91
    
    Manual Reset
    92
    
    Power-On Reset
    92
  - Address Errors
    93
    
    Address Error Exception Handling
    93
    
    Address Error Sources
    93
  - Interrupts
    94
    
    Interrupt Priority Rankings
    94
    
    Interrupt Sources
    94
    
    Interrupt Exception Handling
    95
  - Instruction Exceptions
    96
    
    Trap Instruction
    96
    
    Types of Instruction Exceptions
    96
    
    General Illegal Instructions
    97
    
    Illegal Slot Instruction
    97
  - Cases in Which Exceptions Are Not Accepted
    98
    
    Immediately after Delayed Branch Instruction
    98
    
    Immediately after Interrupt-Disabling Instruction
    98
  - Stack Status after Exception Handling
    99
  - Notes
    100
    
    Address Errors Caused by Stacking During Address Error Exception Handling
    100
    
    Value of the Stack Pointer (SP)
    100
    
    Value of the Vector Base Register (VBR)
    100
- Interrupt Controller (INTC)
  
  102
  - Overview
    102
    
    Block Diagram
    102
    
    Features
    102
    
    Pin Configuration
    104
    
    Registers
    104
  - Interrupt Sources
    105
    
    IRQ Interrupts
    105
    
    NMI Interrupts
    105
    
    User Break Interrupt
    105
    
    Interrupt Exception Vectors and Priority Rankings
    106
    
    On-Chip Interrupts
    106
  - Register Descriptions
    109
    
    Interrupt Priority Registers A-E (IPRA-IPRE)
    109
    
    Interrupt Control Register (ICR)
    110
  - Interrupt Operation
    111
    
    Interrupt Sequence
    111
    
    Stack after Interrupt Exception Handling
    113
  - Interrupt Response Time
    114
  - Usage Notes
    115
- User Break Controller (UBC)
  
  116
  - Overview
    116
    
    Features
    116
    
    Block Diagram
    117
    
    Register Configuration
    118
  - Register Descriptions
    119
    
    Break Address Registers (BAR)
    119
    
    Break Address Mask Register (BAMR)
    120
    
    Break Bus Cycle Register (BBR)
    121
  - Operation
    123
    
    Flow of User Break Operation
    123
    
    Break on Instruction Fetch Cycles to On-Chip Memory
    125
    
    Program Counter (PC) Value Saved in User Break Interrupt Exception Processing
    125
  - Setting User Break Conditions
    126
  - Notes
    127
    
    Instruction Fetch at Branches
    127
    
    On-Chip Memory Instruction Fetch
    127
    
    Instruction Fetch Break
    128
- Clock Pulse Generator (CPG)
  
  130
  - Overview
    130
  - Clock Source
    130
    
    Connecting a Crystal Resonator
    130
    
    External Clock Input
    132
  - Usage Notes
    133
- Bus State Controller (BSC)
  
  136
  - Overview
    136
    
    Features
    136
    
    Block Diagram
    137
    
    Pin Configuration
    138
    
    Register Configuration
    139
    
    Overview of Areas
    140
  - Register Descriptions
    142
    
    Bus Control Register (BCR)
    142
    
    Wait State Control Register 1 (WCR1)
    144
    
    Wait State Control Register 2 (WCR2)
    146
    
    Wait State Control Register 3 (WCR3)
    148
    
    DRAM Area Control Register (DCR)
    149
    
    Refresh Control Register (RCR)
    152
    
    Refresh Timer Control/Status Register (RTCSR)
    153
    
    Refresh Time Constant Register (RTCOR)
    155
    
    Refresh Timer Counter (RTCNT)
    155
    
    Parity Control Register (PCR)
    156
    
    Notes on Register Access
    158
  - Address Space Subdivision
    159
    
    Address Spaces and Areas
    159
    
    Bus Width
    161
    
    Chip Select Signals (CS0-CS7)
    161
    
    Shadows
    162
    
    Area Descriptions
    164
  - Accessing External Memory Space
    171
    
    Basic Timing
    171
    
    Wait State Control
    173
    
    Byte Access Control
    176
  - DRAM Interface Operation
    177
    
    DRAM Address Multiplexing
    177
    
    Basic Timing
    179
    
    Wait State Control
    181
    
    Byte Access Control
    183
    
    DRAM Burst Mode
    185
    
    Refresh Control
    190
  - Address/Data Multiplexed I/O Space Access
    194
    
    Basic Timing
    194
    
    Byte Access Control
    195
    
    Wait State Control
    195
  - Parity Check and Generation
    196
  - Warp Mode
    197
  - Wait State Control
    198
  - Bus Arbitration
    201
    
    Operation of Bus Arbitration
    202
    
    BACK Operation
    203
  - Usage Notes
    204
    
    Usage Notes on Manual Reset
    204
    
    Maximum Number of States from BREQ Input to Bus Release
    207
    
    Usage Notes on Parity Data Pins DPH and DPL
    207
- Direct Memory Access Controller (DMAC)
  
  210
  - Overview
    210
    
    Features
    210
    
    Block Diagram
    211
    
    Pin Configuration
    213
    
    Register Configuration
    214
  - Register Descriptions
    215
    
    DMA Destination Address Registers 0-3 (DAR0-DAR3)
    215
    
    DMA Source Address Registers 0-3 (SAR0-SAR3)
    215
    
    DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
    216
    
    DMA Transfer Count Registers 0-3 (TCR0-TCR3)
    216
    
    DMA Operation Register (DMAOR)
    221
  - Operation
    223
    
    DMA Transfer Flow
    223
    
    DMA Transfer Requests
    225
    
    Channel Priority
    227
    
    DMA Transfer Types
    232
    
    Number of Bus Cycle States and DREQ Pin Sample Timing
    239
    
    DMA Transfer Ending Conditions
    247
  - Examples of Use
    248
    
    DMA Transfer between On-Chip RAM and Memory-Mapped External Device
    248
    
    Example of DMA Transfer between On-Chip SCI and External Memory
    249
    
    Example of DMA Transfer between On-Chip A/D Converter and External Memory
    250
  - Usage Notes
    251
- Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
  
  254
  - Overview
    254
    
    Features
    254
    
    Block Diagram
    257
    
    Input/Output Pins
    262
    
    Register Configuration
    263
  - ITU Register Descriptions
    265
    
    Timer Start Register (TSTR)
    265
    
    Timer Synchro Register (TSNC)
    267
    
    Timer Mode Register (TMDR)
    268
    
    Timer Function Control Register (TFCR)
    271
    
    Timer Output Control Register (TOCR)
    273
    
    Timer Counters (TCNT)
    274
    
    General Registers a and B (GRA and GRB)
    275
    
    Buffer Registers a and B (BRA, BRB)
    276
    
    Timer Control Register (TCR)
    277
    
    Timer I/O Control Register (TIOR)
    279
    
    Timer Status Register (TSR)
    281
    
    Timer Interrupt Enable Register (TIER)
    282
  - CPU Interface
    284
    
    16-Bit Accessible Registers
    284
    
    8-Bit Accessible Registers
    286
  - Operation
    287
    
    Overview
    287
    
    Basic Functions
    288
    
    Synchronizing Mode
    297
    
    PWM Mode
    299
    
    Reset-Synchronized PWM Mode
    303
    
    Complementary PWM Mode
    306
    
    Phase Counting Mode
    313
    
    Buffer Mode
    315
    
    ITU Output Timing
    320
  - Interrupts
    321
    
    Timing of Setting Status Flags
    321
    
    Status Flag Clear Timing
    323
    
    Interrupt Sources and DMAC Activation
    324
  - Notes and Precautions
    325
    
    Contention between TCNT Write and Clear
    325
    
    Contention between TCNT Word Write and Increment
    326
    
    Contention between TCNT Byte Write and Increment
    327
    
    Contention between GR Write and Compare Match
    328
    
    Contention between TCNT Write and Overflow/Underflow
    329
    
    Contention between General Register Read and Input Capture
    330
    
    Contention between Counter Clearing by Input Capture and Counter Increment
    331
    
    Contention between General Register Write and Input Capture
    332
    
    Note on Waveform Cycle Setting
    332
    
    10.6.10 Contention between BR Write and Input Capture
    333
    
    10.6.11 Note on Writing in Synchronizing Mode
    334
    
    10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode
    334
    
    10.6.13 Clearing Complementary PWM Mode
    335
    
    10.6.14 Note on Counter Clearing by Input Capture
    335
    
    10.6.15 ITU Operating Modes
    336
- Section 11 Programmable Timing Pattern Controller (TPC)
  
  344
  - Overview
    344
    
    Features
    344
    
    Block Diagram
    345
    
    Input/Output Pins
    346
    
    Registers
    347
  - Register Descriptions
    348
    
    Port B Control Registers 1 and 2 (PBCR1, PCBR2)
    348
    
    Next Data Register a (NDRA)
    349
    
    Port B Data Register (PBDR)
    349
    
    Next Data Register B (NDRB)
    351
    
    Next Data Enable Register a (NDERA)
    353
    
    Next Data Enable Register B (NDERB)
    353
    
    TPC Output Control Register (TPCR)
    354
    
    TPC Output Mode Register (TPMR)
    356
  - Operation
    357
    
    Overview
    357
    
    Output Timing
    358
    
    Examples of Use of Ordinary TPC Output
    359
    
    TPC Output Non-Overlap Operation
    362
    
    TPC Output by Input Capture
    366
  - Usage Notes
    367
    
    Non-Overlap Operation
    367
- Section 12 Watchdog Timer (WDT)
  
  370
  - Overview
    370
    
    Features
    370
    
    Block Diagram
    371
    
    Pin Configuration
    371
    
    Register Configuration
    372
  - Register Descriptions
    372
    
    Timer Counter (TCNT)
    372
    
    Timer Control/Status Register (TCSR)
    373
    
    Reset Control/Status Register (RSTCSR)
    374
    
    Notes on Register Access
    375
  - Operation
    377
    
    Operation in Watchdog Timer Mode
    377
    
    Operation in Interval Timer Mode
    379
    
    Operation in Standby Mode
    379
    
    Timing of Overflow Flag (OVF) Setting
    380
    
    Timing of Watchdog Timer Overflow Flag (WOVF) Setting
    380
  - Usage Notes
    381
    
    Changing CKS2-CKS0 Bit Values
    381
    
    Changing Watchdog Timer/Interval Timer Modes
    381
    
    TCNT Write and Increment Contention
    381
    
    Internal Reset with Watchdog Timer
    382
    
    System Reset with WDTOVF
    382
- Section 13 Serial Communication Interface (SCI)
  
  384
  - Overview
    384
    
    Features
    384
    
    Block Diagram
    385
    
    Input/Output Pins
    386
    
    Register Configuration
    386
  - Register Descriptions
    387
    
    Receive Data Register
    387
    
    Receive Shift Register
    387
    
    Transmit Data Register
    388
    
    Transmit Shift Register
    388
    
    Serial Mode Register
    389
    
    Serial Control Register
    391
    
    Serial Status Register
    394
    
    Bit Rate Register (BRR)
    398
  - Operation
    407
    
    Overview
    407
    
    Operation in Asynchronous Mode
    409
    
    Multiprocessor Communication
    420
    
    Synchronous Operation
    428
  - SCI Interrupt Sources and the DMAC
    438
  - Usage Notes
    438
- Section 14 A/D Converter
  
  442
  - Overview
    442
    
    Features
    442
    
    Block Diagram
    443
    
    Configuration of Input Pins
    444
    
    Configuration of A/D Registers
    445
  - Register Descriptions
    445
    
    A/D Data Registers A-D (ADDRA-ADDRD)
    445
    
    A/D Control/Status Register (ADCSR)
    446
    
    A/D Control Register (ADCR)
    448
  - CPU Interface
    449
  - Operation
    451
    
    Single Mode (SCAN = 0)
    451
    
    Scan Mode (SCAN = 1)
    453
    
    Input Sampling Time and A/D Conversion Time
    455
    
    A/D Conversion Start by External Trigger Input
    456
  - Interrupts and DMA Transfer Requests
    456
  - Definitions of A/D Conversion Accuracy
    457
  - A/D Converter Usage Notes
    458
    
    Handling of Analog Input Pins
    458
    
    Setting Analog Input Voltage
    458
    
    Switchover between Analog Input and General Port Functions
    459
- Section 15 Pin Function Controller (PFC)
  
  460
  - Overview
    460
  - Register Configuration
    462
  - Register Descriptions
    462
    
    Port a I/O Register (PAIOR)
    462
    
    Port a Control Registers (PACR1 and PACR2)
    463
    
    Port B I/O Register (PBIOR)
    468
    
    Port B Control Registers (PBCR1 and PBCR2)
    469
    
    Column Address Strobe Pin Control Register (CASCR)
    474
- Section 16 I/O Ports (I/O)
  
  476
  - Overview
    476
  - Port a
    476
    
    Register Configuration
    476
    
    Port a Data Register (PADR)
    477
  - Port B
    478
    
    Register Configuration
    478
    
    Port B Data Register (PBDR)
    479
  - Port C
    480
    
    Register Configuration
    480
    
    Port C Data Register (PCDR)
    481
- Section 17 ROM
  
  482
  - Overview
    482
  - PROM Mode
    483
    
    Setting PROM Mode
    483
    
    Socket Adapter Pin Correspondence and Memory Map
    483
  - PROM Programming
    485
    
    Selecting the Programming Mode
    485
    
    Write/Verify and Electrical Characteristics
    486
    
    Notes on Writing
    490
    
    Reliability after Writing
    491
- Section 18 RAM
  
  492
  - Overview
    492
  - Operation
    493
- Section 19 Power-Down State
  
  494
  - Overview
    494
    
    Power-Down Modes
    494
    
    Register
    495
  - Standby Control Register (SBYCR)
    495
  - Sleep Mode
    496
    
    Exiting Sleep Mode
    496
    
    Transition to Sleep Mode
    496
  - Standby Mode
    496
    
    Transition to Standby Mode
    496
    
    Exiting Standby Mode
    498
    
    Standby Mode Application
    498
- Section 20 Electrical Characteristics
  
  500
  - SH7032 and SH7034 Electrical Characteristics
    500
    
    Absolute Maximum Ratings
    500
    
    DC Characteristics
    500
AC Characteristics/Clock Timing

507

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Hitachi HD6417032 Manuals

Hitachi HD6417032 Hardware Manual (690 pages)

Table of Contents

Table of Contents

Overview

Section 2 CPU

Section 3 Operating Modes

Section 4 Exception Handling

Interrupt Controller (INTC)

User Break Controller (UBC)

Clock Pulse Generator (CPG)

Bus State Controller (BSC)

Direct Memory Access Controller (DMAC)

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)

Section 11 Programmable Timing Pattern Controller (TPC)

Section 12 Watchdog Timer (WDT)

Section 13 Serial Communication Interface (SCI)

Section 14 A/D Converter

Section 15 Pin Function Controller (PFC)

Section 16 I/O Ports (I/O)

Section 17 ROM

Section 18 RAM

Section 19 Power-Down State

Section 20 Electrical Characteristics

AC Characteristics/Clock Timing

AC Characteristics

Clock Timing

Appendix A On-Chip Supporting Module Registers

Appendix B Pin States

Appendix C Package Dimensions

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