Usage Notes; Usage Notes On Manual Reset - Hitachi SH7032 Hardware Manual

Superh risc engine

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Note that delay of the BACK signal increases in units of approximately 0.1 ns/pF. (When a

capacitance of 220 pF is added, the delay increases by approximately 22 ns.)

c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may or may not

be successful due to the narrow pulse width of the spike. Implement a circuit configuration

which will cause no problems when latching BACK or using BACK as a trigger signal.

When splitting the BACK signal into two signals and latching each of them using a flip-

flop or triggering the flip-flop, the flip-flop may operate for one signal but not for the other.

To capture the BACK signal using a flip-flop, receive the BACK signal using a single flip-

flop then distribute the signal (see figure below).

Usage Notes

Condition: When DRAM (long-pitch mode) is used and a manual reset is performed.

The low width of RAS output may be shorter than usual in a reset (2.5 tcyc → 1.5 tcyc),

preventing the specified value (t

Microcomputer

Circuit with capacitor for eliminating spikes

) of DRAM from being satisfied.

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