Hitachi SH7032 Hardware Manual page 421

Superh risc engine

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Transmitting

MPB: multiprocessor bit

Figure 13.9 Example of Communication between Processors Using Multiprocessor Format

Communication Formats: Four formats are available. Parity-bit settings are ignored when a

multiprocessor format is selected. For details see table 13.8.

Clock: See the description in the asynchronous mode section.

Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for

transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is

listed below.

1. SCI initialization: select the TxD pin function with the PFC.

2. SCI status check and transmit data write: read the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT

(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.

3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1);

if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-

empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared

automatically.

4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port

Serial communication line

ID-sending cycle:

receiving processor address

(Sending Data H'AA to Receiving Processor A)

Data-sending cycle:

data sent to receiving

processor specified by ID

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