Table of Contents
Advertisement
CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Notes: *1 For t
CAC2
*2 For t
ACC2
*3 For t
RAC2
is measured from A21–A0, CAS, or RAS, whichever is negated first.
*4 t
RDH
Figure 20.26 DRAM Bus Cycle: (Long-Pitch, Normal Mode)
502
T
p
t
AD
t
RASD1
× (n + 1) – 35 instead of t
, use t
cyc
× (n + 2) – 44 instead of t
, use t
cyc
× (n + 2.5) – 35 instead of t
, use t
cyc
T
Tc
r
1
t
AD
Row
t
RAH
t
CASD2
t
RDD
t
WCH
t
ACC2
t
RAC2
t
DACD1
t
WSD1
t
WDD1
t
WPDD1
t
DACD3
× (n + 1) – t
cyc
× (n + 2) – t
cyc
× (n + 2.5) – t
cyc
Tc
2
Column
t
RASD2
t
DS
t
RSD
t
*1
CAC2
*2
*3
t
RDS
t
DACD2
t
WSD2
t
WDH
t
WPDH
t
DACD3
– t
.
CASD2
RDS
– t
.
AD
RDS
– t
RASD1
RDS
t
CASD3
t
*4
RDH
.
- Quick Links:
- Table of Contents
- Overview
Hide quick links:
Advertisement
Chapters
Table of Contents
