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CK
A21–A0
HBS, LBS
CSn
RD
(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
WRH, WRL,
WR (Write)
AD15–AD0
DPH, DPL
(Write)
DACK0
DACK1
(Write)
WAIT
Notes: *1 For t
RDAC2
instead of t
*2 For t
ACC2
Figure 20.10 Basic Bus Cycle: Two States + Wait State
482
T
1
t
WTS
× (n+1.65) – 20 (for 35% duty) or t
, use t
cyc
× (n+2) – t
– t
cyc
RDD
× (n+2) – 30 instead of t
, use t
cyc
T
W
*1
t
RDAC2
*2
t
ACC2
t
t
t
WTH
WTS
WTH
.
RDS
× (n+2) – t
cyc
T
2
× (n+1.5) – 20 (for 50% duty)
cyc
(or t
) – t
AD
CSD1
RDS
.
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