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7.2.5
Refresh Timer Control/Status Register (RTCSR)
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
•
Bits 15–8—Reserved bits: These bits always read 0. The write value should always be 0.
•
Bit 7—Compare Match Flag (CMF): This status flag, which indicates that the values of
RTCNT and RTCOR match, is set/cleared under the following conditions:
Bit 7 (CMF)
0
1
•
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request
caused by the CMF bit of the RTSCR when CMF is set to 1.
Bit 6 (CMIE)
0
1
134 Hitachi
15
14
—
—
0
0
R
R
7
6
CMF
CMIE
CKS2
0
0
R/W
R/W
Description
RTCNT and RTCOR match
Clear condition: After RTCSR is read when CMF is 1, 0 is written in
CMF
RTCNT and RTCOR do not match
Set condition: RTCNT = RTCOR
Description
Disables an interrupt request caused by CMF (Initial value)
Enables an interrupt request caused by CMF
13
12
—
—
0
0
R
R
5
4
CKS1
CKS0
0
0
R/W
R/W
R/W
11
10
—
—
0
0
R
R
3
2
—
0
0
R
9
8
—
—
0
0
R
R
1
0
—
—
0
0
R
R
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