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Figure 7.27 Synchronous DRAM Mode Write Timing
7.5.9
Phase Shift by PLL
The signals for synchronous DRAM interfaces change in the SH7095 with the rising edge of the
internal clock. Read data is fetched on the falling edge of an internal clock. Sampling of the
signals input by the synchronous DRAM and output of the read data, however, starts with the
rising edge of the external clock (figure 7.28).
When the internal clock of the SH7095 and external clock are synchronized, signal transmission
from the SH7095 to the synchronous DRAM has a 1 cycle margin. The transmission of read data
from the synchronous DRAM to the SH7095, however, is much tighter: only 1/2 cycle, including
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