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3.
When the channel 1 transfer ends, channel 1 becomes the lower priority.
4.
The channel 0 transfer begins.
5.
When the channel 0 transfer ends, channel 0 becomes the lower priority.
6.
A channel 0 transfer is requested.
7.
The channel 0 transfer begins.
8.
When the channel 0 transfer ends, channel 0 is already the lowest priority, so the order
remains the same.
9.3.4
DMA Transfer Types
The DMAC supports all the transfers shown in table 9.7. It can operate in single address mode or
dual address mode, as defined by how many bus cycles the DMAC takes to access the transfer
source and transfer destination. The actual transfer operation timing varies with the DMAC bus
mode used: cycle-steal mode or burst mode.
Figure 9.5 Channel Priority in Round-Robin Mode
Hitachi 241
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