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(1) Upper byte read
CPU reads
data H'AA
(2) Lower byte read
CPU reads
data H'55
Figure 6-4 (b). Read Access to FRC (when FRC Contains H'AA55)
6.4 Operation
6.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR.
Internal Clock: The internal clock sources (Ø/2, Ø/8, Ø/32) are created from the system clock (Ø)
by a prescaler. The FRC increments on a pulse generated from the falling edge of the prescaler
output. See figure 6-5.
Bus interface
Bus interface
130
Module data bus
TEMP
[H'55]
FRC H
FRC L
[H'AA]
[H'55]
Module data bus
TEMP
[H'55]
FRC H
FRC L
[
]
[
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