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Table A-1. Instruction Set (cont.)
Mnemonic
JSR @Rn
JSR @aa:16
JSR @@aa:8
RTS
RTE
SLEEP
LDC #xx:8,CCR
LDC Rs,CCR
STC CCR,Rd
ANDC #xx:8,CCR
ORC #xx:8,CCR
XORC #xx:8,CCR
NOP
Notes: The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory.
Set to "1" when there is a carry or borrow from bit 11; otherwise cleared to "0."
≠
If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to "0."
Set to "1" if decimal adjustment produces a carry; otherwise cleared to "0."
The number of states required for execution is 4n+8 (n = value of R4L)
∞
These instructions are not supported by the H8/329 Series.
±
Set to "1" if the divisor is negative; otherwise cleared to "0."
≤
Set to "1" if the divisor is zero; otherwise cleared to "0."
Operation
SP–2 → SP
–
PC → @SP
PC ← Rn16
SP–2 → SP
–
PC → @SP
PC ← aa:16
SP–2 → SP
PC → @SP
PC ← @aa:8
PC ← @SP
–
SP+2 → SP
CCR ← @SP
–
SP+2 → SP
PC ← @SP
SP+2 → SP
–
Transit to sleep mode.
#xx:8 → CCR
B
Rs8 → CCR
B
CCR → Rd8
B
CCR∧#xx:8 → CCR
B
CCR∨#xx:8 → CCR
B
CCR⊕#xx:8 → CCR
B
PC ← PC+2
–
Addressing mode/
instruction length
2
4
2
2
2
2
2
2
277
Condition code
I H N Z V C
–
–
–
–
–
– 6
–
–
–
–
–
– 8
2
–
–
–
–
–
– 8
2
–
–
–
–
–
– 8
◊
◊
◊
◊
◊
◊ 10
2
2
–
–
–
–
–
– 2
◊
◊
◊
◊
◊
◊ 2
◊
◊
◊
◊
◊
◊ 2
–
–
–
–
–
– 2
◊
◊
◊
◊
◊
◊ 2
◊
◊
◊
◊
◊
◊ 2
◊
◊
◊
◊
◊
◊ 2
2
–
–
–
–
–
– 2
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