Hitachi H8/3064F-ZTAT Microcontroller Manuals

Manuals and User Guides for Hitachi H8/3064F-ZTAT Microcontroller. We have 1 Hitachi H8/3064F-ZTAT Microcontroller manual available for free PDF download: Hardware Manual

Hitachi H8/3064F-ZTAT Hardware Manual (939 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.98 MB

Table of Contents
11
Section 1 Overview

26
Cpu

52
- Overview
  52
  - Features
    52
  - Differences from H8/300 CPU
    53
- CPU Operating Modes
  53
- Address Space
  54
- Register Configuration
  55
  - Overview
    55
  - 2.4.2 General Registers
    56
  - Control Registers
    57
  - Initial CPU Register Values
    58
- Data Formats
  59
  - General Register Data Formats
    59
  - Memory Data Formats
    60
- Instruction Set
  62
- Addressing Modes and Effective Address Calculation
  76
  - Addressing Modes
    76
  - Effective Address Calculation
    78
- Processing States
  82
  - Overview
    82
  - Program Execution State
    82
  - Exception-Handling State
    83
  - Exception Handling Operation
    84
  - Bus-Released State
    85
  - Reset State
    85
  - Power-Down State
    86
- Basic Operational Timing
  86
MCU Operating Modes

89
- Overview
  89
  - Operating Mode Selection
    89
  - Register Configuration
    90
- Mode Control Register (MDCR)
  90
- System Control Register (SYSCR)
  91
- Operating Mode Descriptions
  93
  - Mode 1
    93
  - Mode 2
    93
  - Mode 3
    94
  - Mode 4
    94
  - Mode 5
    94
  - Mode 7
    94
- Pin Functions in each Operating Mode
  95
- Memory Map in each Operating Mode
  96
  - Comparison of H8/3062 Series Memory Maps
    96
  - Reserved Areas
    97
Exception Handling

106
- Overview
  106
  - Exception Handling Types and Priority
    106
  - Exception Handling Operation
    106
  - Exception Vector Table
    107
- Reset
  109
  - Reset Sequence
    109
  - Interrupts after Reset
    112
- Interrupts
  113
- Trap Instruction
  113
- Stack Status after Exception Handling
  114
- Notes on Stack Usage
  115
  - Overview
    117
Interrupt Controller

117
- Features
  117
- Block Diagram
  118
- Pin Configuration
  119
- Register Configuration
  119
- Register Descriptions
  119
- Interrupt Sources
  128
  - External Interrupts
    128
  - Internal Interrupts
    129
  - Interrupt Exception Handling Vector Table
    129
- Interrupt Operation
  133
  - Interrupt Handling Process
    133
  - Interrupt Exception Handling Sequence
    138
  - Interrupt Response Time
    139
- Usage Notes
  140
Bus Controller

142
- Overview
  142
  - Features
    142
  - Block Diagram
    143
  - Pin Configuration
    144
  - Register Configuration
    145
- Register Descriptions
  145
- Operation
  156
  - Area Division
    156
  - Bus Specifications
    159
  - Memory Interfaces
    160
  - Address Output Method
    161
- Basic Bus Interface
  163
  - Overview
    163
  - Data Size and Data Alignment
    163
  - Valid Strobes
    164
  - Memory Areas
    165
  - Basic Bus Control Signal Timing
    166
  - Wait Control
    173
- Idle Cycle
  175
  - Operation
    175
  - Pin States in Idle Cycle
    177
- Bus Arbiter
  177
  - Operation
    178
- Register and Pin Input Timing
  180
  - Register Write Timing
    180
  - BREQ Pin Input Timing
    181
I/O Ports

182
- Overview
  182
- Port 1
  186
  - Overview
    186
  - Register Descriptions
    186
- Port 2
  189
  - Overview
    189
  - Register Descriptions
    190
- Port 3
  193
  - Overview
    195
  - Register Descriptions
    199
- Port 4
  201
  - Overview
    201
- Port 5
  201
  - Overview
    205
- Port 6
  205
- Port 7
  205
  - Register Description
    206
- Port 8
  207
  - Overview
    207
  - Register Descriptions
    213
  - Overview
    217
- Port a
  217
  - Register Descriptions
    219
- Port B
  229
  - Overview
    229
  - Register Descriptions
    231
16-Bit Timer

237
- Overview
  237
  - Features
    237
  - Block Diagrams
    239
  - Pin Configuration
    242
  - Register Configuration
    243
- Register Descriptions
  244
- CPU Interface
  264
  - 16-Bit Accessible Registers
    264
  - 8-Bit Accessible Registers
    266
- Operation
  267
  - Overview
    267
  - Basic Functions
    267
  - Synchronization
    275
  - PWM Mode
    277
  - Phase Counting Mode
    281
  - 16-Bit Timer Output Timing
    283
- Interrupts
  284
  - Setting of Status Flags
    284
  - Timing of Clearing of Status Flags
    286
  - Usage Notes
    288
8-Bit Timers

300
- Overview
  300
  - Features
    300
  - Block Diagram
    302
  - Pin Configuration
    303
  - Register Configuration
    304
- Register Descriptions
  305
  - Timer Counters (8TCNT)
    305
  - Time Constant Registers a (TCORA)
    306
  - Time Constant Registers B (TCORB)
    307
  - Timer Control Register (8TCR)
    308
  - Timer Control/Status Registers (8TCSR)
    311
- CPU Interface
  316
  - 8-Bit Registers
    316
- Operation
  318
  - 8TCNT Count Timing
    318
  - Compare Match Timing
    319
  - Input Capture Signal Timing
    320
  - Timing of Status Flag Setting
    321
  - Operation with Cascaded Connection
    322
  - Input Capture Setting
    325
- Interrupt
  326
  - Interrupt Sources
    326
  - A/D Converter Activation
    327
- 8-Bit Timer Application Example
  327
- Usage Notes
  328
Section 10 Programmable Timing Pattern Controller (TPC)

338
- Overview
  338
  - Features
    338
  - Block Diagram
    339
  - Pin Configuration
    340
  - Register Configuration
    341
- Register Descriptions
  342
  - Port a Data Direction Register (PADDR)
    342
  - Port a Data Register (PADR)
    342
  - Port B Data Direction Register (PBDDR)
    343
  - Port B Data Register (PBDR)
    343
  - Next Data Register a (NDRA)
    344
  - Next Data Register B (NDRB)
    346
  - Next Data Enable Register a (NDERA)
    348
  - Next Data Enable Register B (NDERB)
    349
  - TPC Output Control Register (TPCR)
    350
  - TPC Output Mode Register (TPMR)
    352
- Operation
  354
  - Overview
    354
  - Output Timing
    355
  - Normal TPC Output
    356
  - Non-Overlapping TPC Output
    358
  - TPC Output Triggering by Input Capture
    360
- Usage Notes
  361
  - Operation of TPC Output Pins
    361
  - Note on Non-Overlapping Output
    361
Section 11 Watchdog Timer

363
- Overview
  363
  - Features
    363
  - Block Diagram
    364
  - Pin Configuration
    364
  - Register Configuration
    365
- Register Descriptions
  365
  - Timer Counter (TCNT)
    365
  - Timer Control/Status Register (TCSR)
    366
  - Reset Control/Status Register (RSTCSR)
    368
  - Notes on Register Access
    369
- Operation
  371
- Interrupts
  374
- Usage Notes
  374
Section 12 Serial Communication Interface

375
- Overview
  375
  - Features
    375
  - Block Diagram
    377
  - Pin Configuration
    378
  - Register Configuration
    379
- Register Descriptions
  380
  - Receive Shift Register (RSR)
    380
  - Receive Data Register (RDR)
    380
  - Transmit Shift Register (TSR)
    381
  - Transmit Data Register (TDR)
    381
  - Serial Mode Register (SMR)
    382
  - Serial Control Register (SCR)
    385
  - Serial Status Register (SSR)
    389
  - Bit Rate Register (BRR)
    394
- Operation
  402
  - Overview
    402
  - Operation in Asynchronous Mode
    405
  - Multiprocessor Communication
    414
  - Synchronous Operation
    421
- SCI Interrupts
  429
- Usage Notes
  430
  - Notes on Use of SCI
    430
Section 13 Smart Card Interface

435
- Overview
  435
  - Features
    435
  - Block Diagram
    436
  - Pin Configuration
    436
  - Register Configuration
    437
- Register Descriptions
  438
  - Smart Card Mode Register (SCMR)
    438
  - Serial Status Register (SSR)
    440
  - Serial Mode Register (SMR)
    441
  - Serial Control Register (SCR)
    442
- Operation
  443
  - Overview
    443
  - Pin Connections
    443
  - Data Format
    444
  - Register Settings
    446
  - Clock
    448
  - Transmitting and Receiving Data
    450
- Usage Notes
  457
Section 14 A/D Converter

460
- Overview
  460
  - Features
    460
  - Block Diagram
    461
  - Pin Configuration
    462
  - Register Configuration
    463
- Register Descriptions
  463
- CPU Interface
  467
- Operation
  469
  - Single Mode (SCAN = 0)
    469
  - Scan Mode (SCAN = 1)
    471
  - Input Sampling and A/D Conversion Time
    473
  - External Trigger Input Timing
    474
- Interrupts
  475
- Usage Notes
  475
Section 15 D/A Converter

480
- Overview
  480
  - Features
    480
  - Block Diagram
    481
  - Pin Configuration
    482
  - Register Configuration
    482
- Register Descriptions
  483
- Operation
  485
- D/A Output Control
  487
Section 16 RAM

488
- Overview
  488
  - Block Diagram
    489
  - Register Configuration
    489
- System Control Register (SYSCR)
  490
- Operation
  491
Section 17 ROM

492
- On-Chip Mask ROM Models]
  492
- Overview
  492
- Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version)
  493
  - Features
    493
  - Block Diagram
    494
  - Pin Configuration
    495
  - Register Configuration
    495
- Flash Memory Register Descriptions
  496
- On-Board Programming Mode
  554
  - Boot Mode
    555
  - User Program Mode
    560
- Flash Memory Programming/Erasing
  562
  - Program Mode
    564
  - Program-Verify Mode
    565
  - Erase Mode
    569
  - Erase-Verify Mode
    569
- Flash Memory Protection
  571
  - Hardware Protection
    571
  - Software Protection
    572
  - Error Protection
    572
  - NMI Input Disabling Conditions
    577
- Flash Memory PROM Mode
  578
  - 18.10.1 Socket Adapters and Memory Map
    578
  - 18.10.2 Notes on Use of PROM Mode
    579
- Flash Memory Programming and Erasing Precautions
  579
  - Block Diagram
    588
Section 18 Flash Memory [H8/3064F-ZTAT]

588
- Pin Configuration
  589
- Register Configuration
  589
- Flash Memory Control Register 2 (FLMCR2)
  593
- RAM Control Register (RAMCR)
  595
- Overview of Operation
  597
  - Mode Transitions
    597
  - On-Board Programming Modes
    599
  - Flash Memory Emulation in RAM
    601
  - Block Configuration
    602
- On-Board Programming Mode
  603
  - Boot Mode
    604
  - User Program Mode
    609
- Flash Memory Programming/Erasing
  611
  - Program Mode
    613
  - Program-Verify Mode
    614
  - Erase Mode
    618
  - Erase-Verify Mode
    618
- Flash Memory Protection
  620
  - Hardware Protection
    620
  - Software Protection
    621
- Flash Memory Programming and Erasing Precautions
  628
- Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
  634
Section 20 Clock Pulse Generator

635
- Overview
  635
  - Block Diagram
    635
- Oscillator Circuit
  636
  - Connecting a Crystal Resonator
    636
  - External Clock Input
    638
- Duty Adjustment Circuit
  640
- Prescalers
  640
- Frequency Divider
  640
  - Register Configuration
    641
  - Division Control Register (DIVCR)
    641
  - Usage Notes
    642
Section 21 Power-Down State

643
- Overview
  643
- Register Configuration
  645
- Sleep Mode
  650
  - Transition to Sleep Mode
    650
  - Exit from Sleep Mode
    650
- Software Standby Mode
  650
- Hardware Standby Mode
  655
- Module Standby Function
  656
  - Module Standby Timing
    656
  - Read/Write in Module Standby
    656
  - Usage Notes
    656
- System Clock Output Disabling Function
  657
Section 22 Electrical Characteristics

658
- Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version
  660
  - Absolute Maximum Ratings
    660
  - DC Characteristics
    661
  - AC Characteristics
    672
  - A/D Conversion Characteristics
    678
  - D/A Conversion Characteristics
    680
- Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
  681
  - Absolute Maximum Ratings
    681
  - DC Characteristics
    682
  - AC Characteristics
    690
  - A/D Conversion Characteristics
    696
  - D/A Conversion Characteristics
    698
  - Flash Memory Characteristics
    699
- Electrical Characteristics of H8/3064F-ZTAT
  703
  - Absolute Maximum Ratings
    703
  - DC Characteristics
    704
  - AC Characteristics
    712
  - A/D Conversion Characteristics
    718
  - D/A Conversion Characteristics
    720
  - Flash Memory Characteristics
    721
- Electrical Characteristics of H8/3062F-ZTAT A-Mask Version
  725
  - DC Characteristics
    726
  - AC Characteristics
    734
  - A/D Conversion Characteristics
    740
  - D/A Conversion Characteristics
    742
  - Flash Memory Characteristics
    743
- Operational Timing
  747
  - Clock Timing
    747
  - Control Signal Timing
    748
  - Bus Timing
    750
  - TPC and I/O Port Timing
    754
  - Timer Input/Output Timing
    754
  - SCI Input/Output Timing
    755
Appendix A Instruction Set

756
- Instruction List
  756
  - Data Transfer Instructions
    758
  - Arithmetic Instructions
    760
  - Bit Manipulation Instructions
    765
- Operation Code Maps
  771
- Number of States Required for Execution
  774
Appendix B Internal I/O Registers

783
Appendix D Pin States

919
- Port States in each Mode
  919
- Pin States at Reset
  923
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

926
Appendix F Product Code Lineup

927
Appendix G Package Dimensions

929
Appendix H Comparison of H8/300H Series Product Specifications

932
- Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002
  932
- Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)
  935

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Hitachi H8/3064F-ZTAT Microcontroller Manuals

Hitachi H8/3064F-ZTAT Hardware Manual (939 pages)

Table of Contents

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

Bus Controller

I/O Ports

16-Bit Timer

8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

Section 11 Watchdog Timer

Section 12 Serial Communication Interface

Section 13 Smart Card Interface

Section 14 A/D Converter

Section 15 D/A Converter

Section 16 RAM

Section 17 ROM

Section 18 Flash Memory [H8/3064F-ZTAT]

Section 20 Clock Pulse Generator

Section 21 Power-Down State

Section 22 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Registers

Appendix D Pin States

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Appendix F Product Code Lineup

Appendix G Package Dimensions

Appendix H Comparison of H8/300H Series Product Specifications

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