hit counter script
Asus Aaeon BOXER-8332AI User Manual
  1. Manuals
  2. Brands
  3. Asus Manuals
  4. Server
  5. Aaeon BOXER-8332AI
  6. User manual

Asus Aaeon BOXER-8332AI User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
BOXER-8332AI
Embedded AI Vision System
st
User 's Manual 1
Ed
Last Updated: October 7, 2021

Advertisement

Table of Contents
loading

Related Manuals for Asus Aaeon BOXER-8332AI

Summary of Contents for Asus Aaeon BOXER-8332AI

  • Page 1 BOXER-8332AI Embedded AI Vision System User ’s Manual 1 Last Updated: October 7, 2021...
  • Page 2 Copyright Notice This document is copyrighted, 2021. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other product name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Pentium®, Celeron®, and Xeon® are registered trademarks of Intel ⚫ Corporation Intel Core™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: I t em Quantity BOXER-8332AI-CFL ⚫ NVIDIA® Tesla® T4 ⚫ Wallmount Bracket ⚫ 3-Pin DC-In Power Connector ⚫ Screw Package ⚫ Thermal Pad Package ⚫...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Saf e ty Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situatio ns arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. C aution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 Chi na RoHS Requirements ( CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯 醚(PBDE) (Pb) (Hg) (Cd) (Cr(VI)) (PBB) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材...
  • Page 10 Chi na RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ............. . . 1 Specifications ....................
  • Page 12 2.4.14 SATA Connector (CN20, CN23, CN24, CN26) ......31 2.4.15 SATA Power Connector (CN21, CN22, CN25, CN27)....31 2.4.16 Digital IO Port (CN28) ..............32 2.4.17 COM1, COM2 Connector (RS232/RS422/RS485) (CN29) ... 33 2.4.18 COM Port 1 Wafer Box (Optional) (CN30) ........34 2.4.19 COM Port 2 Wafer Box (Optional) (CN31) ........
  • Page 13 3.4.2 CPU Config uration ................ 62 3.4.3 PCH-FW Configuration ..............64 3.4.3.1 Firmware Update Configuration ........65 3.4.3.2 PTT Configuration ............66 3.4.4 SATA Configuration ............... 67 3.4.5 USB Configuration................. 68 3.4.6 Hardware Monitor................. 69 3.4.6.1 Smart Fan Mode Configuration ........70 3.4.7 SIO Configuration .................
  • Page 14 Watchdog Timer Introduction ..............98 Watchdog Timer Initial Program ..............99 Appendix B - I/O Information ..............104 I/O Address Map..................

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    1 .1 Spe cifications System Intel® Xeon® E-2124G CP U Intel® i9-9900T Intel® i7-8700T Intel® i5-8500T Intel® i3-8100T Pentium® G5400T Celeron® G4900T N o te: Supports max. TDP 71W C246 (no H310 downward support) Chip set DDR4 SO-DIMM socket x 4 (double deck) Sys tem Memory Supports max 2666MHz up to 128GB Supports un-buffered and ECC/non-ECC type...
  • Page 17 System 1 x Full-Size Mini Card (PCIe + USB with 1 SIM Exp ansion Slot) 1 x Half-Size Mini Card (PCIe + USB, mSATA optional) 1 x M.2 2280 M-Key (PCIe [x4]) 1 x PCIe [x4] Internal: R eserved Connector 2 x SATA 1 x 8-bit DIO 4 x USB2.0...
  • Page 18 E nvironmental 32°F ~ 104°F (0°C ~ 40°C) IEC68-2 with 0.5 m/s Op erating Temperature airflow St orage Temperature -49°F ~ 176°F (-45°C ~ 80°C) St orage Humidity 5~95% at 40°C, non-condensing A nt i-Vibration with SSD: 1Grms/ 5 ~ 500Hz/ operation Sho ck With SSD: 5G at wall-mount, half-sine, 11ms Certification...

  • Page 19: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 20: Dimensions

    Di mensions Chapter 2 – Hardware Information...
  • Page 21 Chapter 2 – Hardware Information...
  • Page 22 Mai n Board Chapter 2 – Hardware Information...

  • Page 23: Jumpers And Connectors

    2.2 Jum pers and Connectors Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    2.3 Li st of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application. Lab el F unction JP 1, JP2 PCIe [x16] Bifurcation selection JP 3 CMOS Control Selection JP 4 PCIe and SATA bus selection for M.2 slot JP 5...

  • Page 25: Clear Cmos Jumper (Jp3)

    2.3.2 Cl e ar CMOS Jumper ( JP3) 1 2 3 Normal (Default) Clear CMOS 2.3.3 PCIe, SATA Selection for M.2 Slot ( JP4) SATA Bus PCIe Bus (Default) 2.3.4 PCIe, SATA Selection for Mini Card Slot ( JP5) 1 2 3 SATA Bus PCIe Bus (Default) 2.3.5...

  • Page 26: Auto Power Button Selection (Jp20)

    2.3.6 Auto Power Button Selection ( JP20) ATX (Default) Chapter 2 – Hardware Information...

  • Page 27: List Of Connectors

    2.4 Li st of Connectors Please refer to the table below for all of the system’s connectors that you can co nfigure for your application Lab el F unction CN 1 SO-DIMM Channel A0 CN 2 SO-DIMM Channel A1 CN 3 SO-DIMM Channel B0 CN 4 SO-DIMM Channel B1...
  • Page 28 Lab el F unction CN 24 SATA connector CN 25 SATA PWR connector CN 26 SATA connector CN 27 SATA PWR connector CN 28 DIO box connector CN 29 COM1+COM2 Connector RS232/RS422/RS485 CN 30 COM1 HEADER RS232/RS422/RS485 CN 31 COM2 HEADER RS232/RS422/RS485 CN 32 COM3+COM4 Connector RS232/RS422/RS485 CN 33...

  • Page 29: Pcie [X4] Slot (Cn5)

    Lab el F unction B AT1 RTC Battery Connector 2.4.1 PCIe [ x4] Slot (CN5) P in P in Name Sig nal Type Sig nal Level PRSNT1# +12V +V12S +12V +V12S PCIE_TXN5 DIFF PCIE_TXP5 DIFF PCIE_RXN5 DIFF PCIE_RXP5 DIFF +3.3V +V3.3S A 10 +3.3V...
  • Page 30 P in P in Name Sig nal Type Sig nal Level A 17 PCIE_RXN24 DIFF A 18 A 19 A 20 A 21 PCIE_RXP23 DIFF A 22 PCIE_RXN23 DIFF A 23 A 24 A 25 PCIE_RXP22 DIFF A 26 PCIE_RXP22 DIFF A 27 A 28...
  • Page 31 P in P in Name Sig nal Type Sig nal Level B 12 B 13 B 14 PCIE_TXP24 DIFF B 15 PCIE_TXN24 DIFF B 16 B 17 PRSNT B 18 B 19 PCIE_TXP23 DIFF B 20 PCIE_TXN23 DIFF B 21 B 22 B 23 PCIE_TXP22...

  • Page 32: Audio I/O Port (10P Pitch: 1.25Mm) (Cn7)

    2.4.2 Audi o I/O Port (10P Pitch: 1.25mm) (CN7) P in P in Name Sig nal Type Sig nal Level MIC_L MIC_R GND_AUDIO LINE_L_IN LINE_R_IN GND_AUDIO LEFT_OUT GND_AUDIO RIGHT_OUT +5V_AUDIO 2.4.3 Dual HDMI Port (CN8) Standard Specifications Chapter 2 – Hardware Information...

  • Page 33: Lan (Rj-45) + Dual Usb3.0 (Cn9)

    2.4.4 L AN ( RJ-45) + Dual USB3.0 ( CN9) N o te: Dual USB3.0 ports are USB3.2 Gen 2 (10 Gbps) specification. L A N (RJ-45) P in P in Name Sig nal Type Sig nal Level DIFF MDI0+ DIFF MDI0- DIFF...
  • Page 34 Dual USB3.0 (USB3.2 Gen 2) P in P in Name Sig nal Type Sig nal Level +5VSB DIFF USB1_D- DIFF USB1_D+ USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF +5VSB DIFF USB2_D- DIFF USB2_D+ USB2_SSRX− DIFF USB2_SSRX+ DIFF USB2_SSTX− DIFF USB2_SSTX+ DIFF Chapter 2 –...

  • Page 35: Lan (Rj-45) + Dual Usb3.0 (Cn10)

    2.4.5 L AN ( RJ-45) + Dual USB3.0 ( CN10) N o te: Dual USB3.0 ports are USB3.2 Gen 2 (10 Gbps) specification. L A N (RJ-45) P in P in name Sig nal Type Sig nal Level DIFF MDI0+ DIFF MDI0- DIFF...
  • Page 36 Dual USB3.0 (USB3.2 Gen 2) P in P in Name Sig nal Type Sig nal Level +5VSB DIFF USB3_D- DIFF USB3_D+ USB3_SSRX− DIFF USB3_SSRX+ DIFF USB3_SSTX− DIFF USB3_SSTX+ DIFF +5VSB DIFF USB4_D- DIFF USB4_D+ USB4_SSRX− DIFF USB4_SSRX+ DIFF USB4_SSTX− DIFF USB4_SSTX+ DIFF Chapter 2 –...

  • Page 37: Lan (Rj-45) + Dual Usb 3.0 (Cn11)

    2.4.6 L AN ( RJ-45) + Dual USB 3.0 (CN11) N o te: Dual USB3.0 ports are USB3.2 Gen 2 (10 Gbps) specification. L A N (RJ-45) P in P in Name Sig nal Type Sig nal Level DIFF MDI0+ DIFF MDI0- DIFF...
  • Page 38 Dual USB3.0 (USB3.2 Gen 2) P in P in Name Sig nal Type Sig nal Level +5VSB DIFF USB5_D- DIFF USB5_D+ USB5_SSRX− DIFF USB5_SSRX+ DIFF USB5_SSTX− DIFF USB5_SSTX+ DIFF +5VSB DIFF USB6_D- DIFF USB6_D+ USB6_SSRX− DIFF USB6_SSRX+ DIFF USB6_SSTX− DIFF USB6_SSTX+ DIFF Chapter 2 –...

  • Page 39: Cpu Fan Connector (Cn12)

    2.4.7 CPU FAN Connector (CN12) P in P in Name Sig nal Type Sig nal Level +VCC_FAN_CPU_CON FAN_TAC_CPU_CON FAN_CTL_CPU_CON 2.4.8 System FAN Connector ( CN13) P in P in Name Sig nal Type Sig nal Level +VCC_FAN_CPU_CON FANIN2 FANCTL2 Chapter 2 – Hardware Information...

  • Page 40: Connector (Cn14)

    2.4.9 M.2 Connector ( CN14) P in P in Name Sig nal Type Sig nal Level To p (Odd) PCIE_RXN16 PCIE_RXP16 PCIE_TXN16 PCIE_TXP16 PCIE_RXN15 PCIE_RXP15 PCIE_TXN15 PCIE_TXP15 PCIE_RXN14 PCIE_RXP14 Chapter 2 – Hardware Information...
  • Page 41 P in P in Name Sig nal Type Sig nal Level PCIE_TXN14 PCIE_TXP14 PCIE_RXP13/SATA0A_RXP PCIE_RXN13/SATA0A_RXN PCIE_TXN13/SATA0A_TXN PCIE_TXP13/SATA0A_TXP PCIE_M.2_CLK# PCIE_M.2_CLK M.2_SATA_PCIE_DET_C B o ttom Even +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Chapter 2 – Hardware Information...
  • Page 42 P in P in Name Sig nal Type Sig nal Level +3.3V +3.3V DEVSLP RESET# CLKREQ# WAKE# +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 43: Remote Button Connector (Cn16)

    2.4.10 Re m ote Button Connector ( CN16) P in P in Name Sig nal Type Sig nal Level PWR_BUTTON 2.4.11 PS_ON Connector P in P in Name Sig nal Type Sig nal Level PS_ON 2.4.12 SPI Fl ash Port ( CN18) P in P in Name Sig nal Type...

  • Page 44: Lpc Connector (Cn19)

    2.4.13 LPC Connector (CN19) P in P in Name Sig nal Type Sig nal Level +3.3V LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V LFRAME# +3.3V LRESET# LCLK SMCLK SMDAT +3.3V SERIRQ Chapter 2 – Hardware Information...

  • Page 45: Sata Connector (Cn20, Cn23, Cn24, Cn26)

    2.4.14 SATA Connector (CN20, CN23, CN24, CN26) P in P in Name Sig nal Type Sig nal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.4.15 SATA Power Connector ( CN21, CN22, CN25, CN27) P in P in Name Sig nal Type Sig nal Level +12V...

  • Page 46: Digital Io Port (Cn28)

    2.4.16 Di gital IO Port (CN28) P in P in Name Sig nal Type Sig nal Level DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Chapter 2 – Hardware Information...

  • Page 47: Com1, Com2 Connector (Rs232/Rs422/Rs485) (Cn29)

    2.4.17 COM1, COM2 Connector ( RS232/RS422/RS485) (CN29) P in P in Name Sig nal Type R S-422 R S-485 DCD1 RS422_TX- RS485_D- RS422_TX+ RS485_D+ RS422_RX+ DTR1 RS422_RX- DSR1 RTS1 CTS1 DCD2 RS422_TX- RS485_D- RS422_TX+ RS485_D- RS422_RX+ DTR2 RS422_RX- DSR2 RTS2 CTS2 Chapter 2 –...

  • Page 48: Com Port 1 Wafer Box (Optional) (Cn30)

    2.4.18 COM Port 1 Wafer Box ( Optional) (CN30) P in P in Name Sig nal Type R S-422 R S-485 DCD1 RS422_TX- RS485_D- DSR1 RS422_TX+ RS485_D+ RTS1 RS422_RX+ CTS1 DTR1 RS422_RX- Chapter 2 – Hardware Information...

  • Page 49: Com Port 2 Wafer Box (Optional) (Cn31)

    2.4.19 COM Port 2 Wafer Box (Optional) ( CN31) P in P in Name Sig nal Type R S-422 R S-485 DCD2 RS422_TX- RS485_D- DSR2 RS422_TX+ RS485_D+ RTS2 RS422_RX+ CTS2 DTR2 RS422_RX- Chapter 2 – Hardware Information...

  • Page 50: Com3, Com4 Connector (Rs232/Rs422/Rs485) (Cn32)

    2.4.20 COM3, COM4 Connector ( RS232/RS422/RS485) (CN32) P in P in Name Sig nal Type R S-422 R S-485 RS422_TX- RS485_D- DCD3 RS422_TX+ RS485_D+ RS422_RX+ RS422_RX- DTR3 DSR3 RTS3 CTS3 RS422_TX- RS485_D- DCD4 RS422_TX+ RS485_D- RS422_RX+ RS422_RX- DTR4 DSR4 RTS4 CTS4 Chapter 2 –...

  • Page 51: Com Port 3 Wafer Box (Optional) (Cn33)

    2.4.21 COM Port 3 Wafer Box (Optional) ( CN33) P in P in Name Sig nal Type R S-422 R S-485 DCD3 RS422_TX- RS485_D- DSR3 RS422_TX+ RS485_D+ RTS3 RS422_RX+ CTS3 DTR3 RS422_RX- Chapter 2 – Hardware Information...

  • Page 52: Com Port 4 Wafer Box (Optional) (Cn34)

    2.4.22 COM Port 4 Wafer Box (Optional) ( CN34) P in P in Name Sig nal Type R S-422 R S-485 DCD4 RS422_TX- RS485_D- DSR4 RS422_TX+ RS485_D+ RTS4 RS422_RX+ CTS4 DTR4 RS422_RX- Chapter 2 – Hardware Information...

  • Page 53: Com Port 5 Wafer Box (Optional) (Cn35)

    2.4.23 COM Port 5 Wafer Box (Optional) ( CN35) P in P in Name Sig nal Type R S-422 R S-485 DCD5 RS422_TX- RS485_D- DSR5 RS422_TX+ RS485_D+ RTS5 RS422_RX+ CTS5 DTR5 RS422_RX- Chapter 2 – Hardware Information...

  • Page 54: Com Port 6 Wafer Box (Optional) (Cn36)

    2.4.24 COM Port 6 Wafer Box (Optional) ( CN36) P in P in Name Sig nal Type R S-422 R S-485 DCD6 RS422_TX- RS485_D- DSR6 RS422_TX+ RS485_D+ RTS16 RS422_RX+ CTS6 DTR6 RS422_RX- Chapter 2 – Hardware Information...

  • Page 55: Mini Card Slot (Full-Sized) (Cn37)

    2.4.25 Mi ni Card Slot ( Full-Sized) (CN37) P in P in Name Sig nal Type Sig nal Level PCIE_WAKE# +3.3V +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RESET UIM_VPP W_DISABLE# +3.3V Chapter 2 – Hardware Information...
  • Page 56 P in P in Name Sig nal Type Sig nal Level PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 57: Sim Slot (Cn38)

    P in P in Name Sig nal Type Sig nal Level +1.5V +1.5V +3.3VSB +3.3V 2.4.26 SIM Sl ot ( CN38) P in P in Name Sig nal Type Sig nal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information...

  • Page 58: Mini Card Slot (Half-Sized) (Cn39)

    2.4.27 Mi ni Card Slot ( Half-Sized) (CN39) P in P in Name Sig nal Type Sig nal Level PCIE_WAKE# +3.3V +3.3V +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF W_DISABLE# +3.3V Chapter 2 – Hardware Information...
  • Page 59 P in P in Name Sig nal Type Sig nal Level PCIE_RST# +3.3V PCIE_RX-/SATA_RX+ DIFF +3.3VSB +3.3V PCIE_RX+/SATA_RX- DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX-/SATA_TX- DIFF SMB_DATA +3.3V PCIE_TX+/SATA_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V MINICARD_SATA_PCIE_DET Chapter 2 – Hardware Information...

  • Page 60: Usb2.0 Wafer Box (Cn40, Cn41, Cn42, Cn43)

    P in P in Name Sig nal Type Sig nal Level +1.5V +1.5V +3.3VSB +3.3V 2.4.28 USB2.0 Wafer Box ( CN40, CN41, CN42, CN43) N o te: USB2.0 Wafer Box (5P Pitch: 1.25mm) P in P in Name Sig nal Type Sig nal Level USBD- DIFF...

  • Page 61: Audio Jack Connector (Cn44)

    2.4.29 Audi o Jack Connector (CN44) P in P in Name Sig nal Type Sig nal Level MIC_R LOUT_R HP_DET2 HP_DET3 HP_DET1 LOUT_L MIC_L Chapter 2 – Hardware Information...

  • Page 62: Audio Connector Wafer Box

    2.4.30 Audi o Connector Wafer Box P in P in Name Sig nal Type Sig nal Level MIC_L MIC_R LIN_L LIN_R LOUT_L LOUT_R VDD_AUD Chapter 2 – Hardware Information...

  • Page 63: Dc-In Connector (Cn48)

    2.4.31 DC-IN Connector ( CN48) P in P in Name Sig nal Type Sig nal Level 2.4.32 G PU DC-IN Connector (CN50, CN51) P in P in Name Sig nal Type Sig nal Level +12V +12V +12V +12V +12V +12V Chapter 2 –...

  • Page 64: Rtc Battery Connector (Bat1)

    P in P in Name Sig nal Type Sig nal Level +12V +12V 2.4.33 RTC Battery Connector ( BAT1) P in P in Name Sig nal Type Sig nal Level +3.3VA_RTC 3.3V Chapter 2 – Hardware Information...

  • Page 65: Cpu Installation

    2.5 CPU Installation Step 1: Power down the system, unplug the power cord and ensure the system is off. Step 2: Have 8 Generation Intel Core, Xeon, Celeron or Pentium CPU ready. See Chapter 1 for processor compatibility. Step 3: Remove the top cover by unscrewing the four retentio n screws. You will see the CPU socket as in Figure 1.

  • Page 66: Expansion Card Installation

    2.6 E xpansion Card Installation Step 1: Power down the system, unplug the power cord and ensure the system is off. Step 2: Have the PCI Express card you wish to install ready, with the rear bracket attached. Step 3: Remove the bottom panel from the system. Note: there are ten (10) retaining screws.
  • Page 67 Step 6: Secure the card in place with the sliding bracket as follows: A : Turn the securing screws counter-clockwise to Open. B : Push the middle of the securing bracket down towards the expansion card. Note: the bracket should fit securely but not apply pressure onto the card. C: Lock the securing screws by turning them clockwise.
  • Page 68 Step 7: Reattach the bottom panel with the ten screws removed in Step 3, as shown in figure 3. Step 8: Attach mounting brackets as shown in figure 4. Chapter 2 – Hardware Information...

  • Page 69: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 70: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 71: Ami Bios Setup

    3.2 AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 72: Setup Submenu: Main

    3.3 Se tup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 73: Setup Submenu: Advanced

    3.4 Se tup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 74: Trusted Computing

    3.4.1 Trusted Computing Op tions Summary Security Device Enable Optimal Default, Failsafe Default Sup port Disable Enable or Disable BIOS support for security device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SHA-1 PCR Bank SHA 256 PCR Bank...
  • Page 75 Op tions Summary P latform Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Platform Hierarchy St orage Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Storage Hierarchy End orsement Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Endorsement Hierarchy TP M2.0 UEFI Spec TCG_2...

  • Page 76: Cpu Configuration

    3.4.2 CPU Configuration Op tions Summary I nt el (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. A ctive Processor Cores Optimal Default, Failsafe Default Number of cores to enable in each processor package.
  • Page 77 Op tions Summary Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available or enabled). C s t ates Disabled Optimal Default, Failsafe Default Enabled Enable/Disable CPU Power Management. Allows CPU to go C states when it’s not 100% utilized Chapter 3 –...

  • Page 78: Pch-Fw Configuration

    3.4.3 PCH-FW Configuration Op tions Summary ME State Enabled Optimal Default, Failsafe Default Disabled When Disabled ME will be put into ME Temporarily Disabled Mode. A MT BIOS Feature Enabled Optimal Default, Failsafe Default Disabled When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup.

  • Page 79: Firmware Update Configuration

    3.4.3.1 Fi rmware Update Configuration Op tions Summary ME F W Image Re-Flash Enabled Disabled Optimal Default, Failsafe Default Enable/Disable ME FW Image Re-Flash function. Chapter 3 – AMI BIOS Setup...

  • Page 80: Ptt Configuration

    3.4.3.2 PT T Configuration Op tions Summary ME F W Image Re-Flash dTPM Optimal Default, Failsafe Default Selects TPM device: PTT or dTPM. PTT – Enables PTT in SkuMgr dTPM 1.2 – Disables PTT in SkuMgr Warning! PTT/dTPM will be disabled and all saved data will be lost. Chapter 3 –...

  • Page 81: Sata Configuration

    3.4.4 SATA Configuration Op tions Summary SATA Mode AHCI Mode Optimal Default, Failsafe Default Selection Intel RST Premium With Intel Optane System Acceleration Determines how SATA controller(s) operate. A g gressive LPM Enabled Sup port Disabled Optimal Default, Failsafe Default Enable PCH to aggressively enter link power state.

  • Page 82: Usb Configuration

    3.4.5 USB Configuration Op tions Summary X HCI Hand-off Enabled Optimal Default, Failsafe Default Disabled This is a workaround for OSes without XHCI Hand-off support. The XHCI ownership change should be claimed by XHCI driver. U SB Mass Storage Driver Enabled Optimal Default, Failsafe Default Sup port...

  • Page 83: Hardware Monitor

    3.4.6 Hardware Monitor Op tions Summary Smart Fan Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Smart Fan Chapter 3 – AMI BIOS Setup...

  • Page 84: Smart Fan Mode Configuration

    3.4.6.1 Sm ar t Fan Mode Configuration Op tions Summary Fan 1/2 Output Mode Output PWM mode Optimal Default, Failsafe Default (push pull) Linear Fan Application Output PWM mode (open drain) Output PWM mode (push pull) to control 4-wire fans. Linear fan application circuit to control 3-wire fan speed by fan’s power terminal.
  • Page 85 Op tions Summary Temperature 1/2/3/4 1-100 Range 60/50/40/30 Optimal Default, Failsafe Default Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Dut y Cycle 1/2/3/4/5 1-100 Range 85/70/60/50/40 Optimal Default, Failsafe Default Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Fan 2 Smart Fan Manual RPM Mode...

  • Page 86: Sio Configuration

    3.4.7 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 87: Serial Port 1 Configuration

    3.4.7.1 Se ri al Port 1 Configuration Op tions Summary U s e This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default s ettings IO=3F8h; IRQ = 4; IO=2F8h;...

  • Page 88: Serial Port 2 Configuration

    3.4.7.2 Se ri al Port 2 Configuration Op tions Summary U s e This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default s ettings IO=2F8h; IRQ = 3; IO=3F8h;...

  • Page 89: Serial Port 3 Configuration

    3.4.7.3 Se ri al Port 3 Configuration Op tions Summary U s e This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default s ettings IO=3E8h; IRQ = 11; IO=2E8h;...

  • Page 90: Serial Port 4 Configuration

    3.4.7.4 Se ri al Port 4 Configuration Op tions Summary U s e This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default s ettings IO=2E8h; IRQ = 11; IO=3E8h;...

  • Page 91: Network Stack Config Uration

    3.4.8 Ne twork Stack Configuration N etwork Stack Disabled: Op tions Summary N etwork Stack Disabled Enabled Optimal Default, Failsafe Default Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup...
  • Page 92 N etwork Stack Enabled: Op tions Summary N etwork Stack Disabled Enabled Optimal Default, Failsafe Default Enable/Disable UEFI Network Stack I p v4 PXE Support Disabled Enabled Optimal Default, Failsafe Default Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.

  • Page 93: Digital Io Port Config Uration

    3.4.9 Di gital IO Port Configuration Op tions Summary DI O Type Output Optimal Default, Failsafe Default Input Set DIO as Input or Output DI O Data High Optimal Default, Failsafe Default Set is output level when DIO pin is output Chapter 3 –...

  • Page 94: Power Management

    3.4.10 Powe r Management Op tions Summary Po wer Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. A C Power Loss Last State Optimal Default, Failsafe Default Power On Power Off Select power state when power is re-applied after a power failure. R TC wake system Disabled Optimal Default, Failsafe Default...
  • Page 95 Op tions Summary Wake up hour Select 0-23; For example: enter 3 for 3am and 15 for 3pm Wake up minute 0 – 59 Wake up second 0 - 59 Chapter 3 – AMI BIOS Setup...

  • Page 96: Setup Submenu: Chipset

    3.5 Se tup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 97: System Agent (Sa) Configuration

    3.5 .1 System Agent (SA) Configuration Op tions Summary P rimary Display Auto Optimal Default; Failsafe Default IGFX Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx. SA GV Enabled Optimal Default, Failsafe Default Disabled Fixed Low Fixed High...
  • Page 98 Op tions Summary R C6(Render Standby) Enabled Optimal Default, Failsafe Default Disabled Check to enable render standby support. DVMT Total Gfx Mem 128M 256M Optimal Default, Failsafe Default Select DVMT5.0 Total Graphic Memory sized used by the Internal Graphics Device. VT- d Enabled Disabled...

  • Page 99: Peg Port Configuration

    3.5.2 PE G Port Configuration Op tions Summary Max Link Speed Auto Optimal Default, Failsafe Default Gen 1 Gen 2 Gen 3 Configure PEG 0:1:0/0:1:1 Max Speed Chapter 3 – AMI BIOS Setup...

  • Page 100: Pch-Io Configuration

    3.5 .3 PCH-IO Configuration Op tions Summary HD A udio Enabled Optimal Default, Failsafe Default Disabled Control the Detection of the Audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled. PCI Express x4 Slot (x4) Auto Optimal Default, Failsafe Default P CI e Speed...

  • Page 101: Setup Submenu: Security

    3.6 Se tup Submenu: Security Change User/Administrator Password Y ou can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 102: Secure Boot

    3.6.1 Se cure Boot Op tions Summary Secure Boot Disable Optimal Default, Failsafe Default Enable Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System mode is in User mode. The mode change requires platform reset. Secure Boot Mode Standard Custom...

  • Page 103: Key Management

    3.6.1.1 Ke y Management Op tions Summary Factory key Provision Disabled Optimal Default, Failsafe Default Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode. R estore Factory Keys Press ‘Y es’ to install factory default keys Y es Force System to User Mode.
  • Page 104 Secure Boot variable |Size | Keys#| key Source Platform key (PK) | Details Enroll Factory Defaults or load certificates from a 1153 | 1 | No Key file: 1.Public key Certificate: Export a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER) c) EFI_CERT_RSA2048 (bin) Update d) EFI_CERT_SHAXXX 2.Authenticated UEFI Variable...
  • Page 105 Secure Boot variable |Size | Keys#| key Source Forbidden Details Enroll Factory Defaults or load certificates from a Signatures | 3274 | file: 77 | No Key 1.Public key Certificate: Export a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER) Update c) EFI_CERT_RSA2048 (bin) d) EFI_CERT_SHAXXX Append 2.Authenticated UEFI Variable...

  • Page 106: Setup Submenu: Boot

    3.7 Se tup Submenu: Boot Op tions Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables Quiet Boot option. Chapter 3 – AMI BIOS Setup...

  • Page 107: Setup Submenu: Save & Exit

    3.8 Se tup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 108: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 109: Drivers Download And Installation

    Dri vers Download and Installation Drivers for the BOXER-8332AI can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/ai-edge-solution-boxer-8332ai-cfl Download the driver(s) you need and follow the steps below to install them. I nstall Chipset Drivers Unzip the Chipset driver zip file Run the Set upChipset.exe file in the folder Follow the instructions...
  • Page 110 I nstall LAN Drivers Unzip the LAN driver zip file Run the P R OWinx64.exe file in the folder Follow the instructions Drivers will be installed automatically I nstall Audio Drivers Unzip the Audio driver zip file Run the 0008-64bit_Win7_Win8_Win81_Win10_R281.exe file in the folder Follow the instructions Drivers will be installed automatically I nstall Intel RST Drivers...

  • Page 111: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 112: Watchdog Timer Introduction

    Watchdog T imer Introduction This section details the initial program setting for the Watchdog Timer program. If you have any questions or need support, please contact an AAEON representative by visiting the support page at AAEON.com Please refer to the Linux Driver User Guide to access DIO, Watchdog Timer and Hardware Manager.

  • Page 113: Watchdog Timer Initial Program

    A.2 Watchdog T imer Initial Program Tab le 1: Super IO relative register table Default Value N o te SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Dat a 0x2F(Note2) 0x2F or 0x4F Tab le 2: Watchdog relative register table R egister B itNum...
  • Page 114 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 115 ************************************************************************************ Main VOID // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 116 ************************************************************************************ // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 1 // Procedure : AaeonWDTConfig AaeonWDTConfig () VOID // Disable WDT counting WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 0 // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting();...
  • Page 117 ************************************************************************************ SIOEnterMBPnPMode() VOID IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); SIOExitMBPnPMode() VOID IOWriteByte(SIOIndex, 0xAA); SIOSelectLDN(byte LDN) VOID IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value) VOID Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 <<...

  • Page 118: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 119: I/O Address Map

    I/O Address Map Appendix B – I/O Informati o n...
  • Page 120 Appendix B – I/O Informati o n...

  • Page 121: Irq Mapping Chart

    B.2 IRQ Mapping Chart Appendix B – I/O Informati o n...
  • Page 122 Appendix B – I/O Informati o n...
  • Page 123 Appendix B – I/O Informati o n...
  • Page 124 Appendix B – I/O Informati o n...
  • Page 125 Appendix B – I/O Informati o n...
  • Page 126 Appendix B – I/O Informati o n...
  • Page 127 Appendix B – I/O Informati o n...
  • Page 128 Appendix B – I/O Informati o n...
  • Page 129 Appendix B – I/O Informati o n...
  • Page 130 Appendix B – I/O Informati o n...

  • Page 131: Memory Address Map

    B.3 Me m or y Address Map Appendix B – I/O Informati o n...

  • Page 132: Appendix C - Digital I/O Ports

    Appendix C Appendix C - Digital I/O Ports...

  • Page 133: Dio Introduction

    DIO Introduction This section details the specifications and information needed to setup and program the Digital I/O ports for your system (DIO). Please refer to the Linux Driver User Guide to access DIO, Watchdog Timer and Hardware Manager. The User Guide is available to download from the Drivers section of the product page.

  • Page 134: Dio Programming

    C.3 DIO Programming BOXER-8332AI utilizes FINTEK F81966 chipset as its Digital I/O controller. The following sections detail the procedures to complete its configuration. There are three steps to complete the configuration setup: St ep 1 Enter MB PnP Mode. St ep 2 Modify the data in the configuration registers.

  • Page 135: Digital I/O Register

    C.4 Di gital I/O Register Tab le 1: SuperIO relative register table Default Value N o te SIO MB PnP Mode Index Register I nd ex 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Dat a 0x2F(Note2) 0x2F or 0x4F Tab le 2: Digital Input relative register table R egister B itNum...

  • Page 136: Digital I/O Sample Program

    C.5 Di gital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #d efine byte SIOIndex //This parameter is represented from N o te1 #d efine byte SIOData //This parameter is represented from N o te2 #d efine vo id IOWriteByte(b yte IOPort, b yte Value);...
  • Page 137 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #d efine byte DOutput1LDN // This parameter is represented from N ote27 #d efine byte DOutput1Reg // This parameter is represented from N o te28 #d efine byte DOutput1Bit // This parameter is represented from N o te29 #d efine byte DOutput1Val // This parameter is represented from N o te30 #d efine byte DOutput2LDN // This parameter is represented from N ote31 #d efine byte DOutput2Reg // This parameter is represented from N o te32...
  • Page 138 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DI nput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 139 ************************************************************************************ Boolean A aeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID A aeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Information...
  • Page 140 ************************************************************************************ VOID SI OEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SI OExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SI OSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SI OBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode();...
  • Page 141 ************************************************************************************ Boolean SI OBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID Co nfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

  • Page 142: Appendix D - Glue Removal Procedure

    Appendix D Appendix D – Glue Removal Procedure...

  • Page 143: Removing Glue From Y Our System

    Re m oving Glue f rom Your System To protect components from damage and ensure proper operation out of the box, glue may have been applied to some cables or connectors to keep them in place during shipping. This glue must be removed before attempting to swap components or perform maintenance.
  • Page 144 St ep 1: Using an eyedropper or bottle as shown above, apply a few drops of alcohol to the glue. St ep 2: Allow the alcohol to soak for 10 seconds, then use a cotton swab or cotton with anti-static tweezers to evenly rub the alcohol over the glue. St ep 3: Let soak for 10 more seconds, then use anti-static tweezers to remove the glue.
  • Page 145 If you encounter any issues or need support, please contact your AAEON representative or visit our Support Page at AAEON.com Appendix C – Digital I/O Information...

Table of Contents