Related Manuals for Asus AAEON GENE-TGU6
Summary of Contents for Asus AAEON GENE-TGU6
- Page 1 GENE-TGU6 3.5” Subcompact Board User’s Manual 2 Last Updated: April 12, 2022...
- Page 2 Copyright Notice This document is copyrighted, 2022. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
- Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel® and Celeron® are registered trademarks of Intel Corporation ⚫ Intel Core™ are trademarks of Intel Corporation ⚫...
- Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-TGU6 MB If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
- Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
- Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
- Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
- Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
- Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○ 连接器及线材...
- Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...
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Page 11: Table Of Contents
Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................6 Chapter 2 – Hardware Information ..................7 Dimensions ....................... 8 Jumpers and Connectors ..................10 List of Jumpers ......................12 2.3.1 Front Panel Connector (JP1) ................ 12 2.3.2 Touch Screen 4, 5, 8-Wire Selection (JP2).......... - Page 12 2.4.12 Touchscreen Connector (Optional) (CN15) ..........26 2.4.13 eSPI Debug Port (CN16) ................29 2.4.14 Digital I/O Connector (CN17) ..............30 2.4.15 LVDS/eDP Port (CN18) ................30 2.4.16 Nano SIM Card Socket (CN19) ..............32 2.4.17 USB 2.0 Port 5, Port 6 Dual Header (CN21)..........33 2.4.18 LVDS/eDP Port Inverter/ Backlight Connector (CN22) ......
- Page 13 3.4.1.1 LVDS Panel Configuration ............... 57 3.4.2 CPU Configuration ..................60 3.4.3 Memory Configuration ................61 3.4.4 Hardware Monitor ..................62 3.4.4.1 Smart Fan Mode Configuration ............. 63 3.4.5 PCH-FW Configuration ................65 3.4.5.1 Firmware Update Configuration ............ 66 3.4.6 Power Management ..................
- Page 14 3.6.1.1 Key Management ................104 Setup Submenu: Boot ..................106 3.7.1 BBS Priorities ....................107 Setup Submenu: Save & Exit ................108 Chapter 4 – Driver Installation .................... 109 Driver Download/Installation ................110 Appendix A - I/O Information ....................113 I/O Address Map ....................114 Memory Address Map ..................
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Page 15: Chapter 1 - Product Specifications
Chapter 1 Chapter 1 - Product Specifications... -
Page 16: Specifications
Specifications System Form Factor 3.5" Subcompact Board Intel® 11th Generation Core™/ Celeron CPU: Core i7-1185G7E (4C/8T, 1.80GHz, up to 4.40GHz) Core i5-1145G7E (4C/8T, 1.50GHz, up to 4.10GHz) Core i3-1115G4E (2C/4T, 2.20GHz, up to 3.90GHz) Celeron® 6305E (2C/2T, 1.80GHz) CPU TDP 15W, up to 28W: Core i7-1185G7E Core i5-1145G7E... - Page 17 Power Power Requirement +9 ~ 36V (Optional: +12V) Power Supply Type AT/ATX Connector Phoenix 2-pin Connector Power Consumption (Typical) 4.96A at +12V, Intel® i7-1185G7E, DDR4 3200MHz 32GB x 2 Power Consumption (Max) 7.32A at +12V, Intel® i7-1185G7E, DDR4 3200MHz 32GB x 2 Display Controller Intel®...
- Page 18 External I/O Ethernet Intel® i219LM, 10/100/1000Base, RJ-45 x 1 Intel® i225LM, 100/1000/2500Base, RJ-45 x 1 USB3.2 Gen 2 x 4 USB3.2 Gen 2 Type C x 1 (PD 5V/3A) Serial Port — Video HDMI 2.0b x 1 DP1.4a x 2 Type C DP1.4 x 1 Power Input Phoenix 2-pin Connector...
- Page 19 Expansion Mini PCIe/ mSATA Full-Sized mSATA/mPCIe x 1 (default: mSATA, select with BIOS) M-Key 2280 x 1 (PCIe [x4]) E-Key 2230 x 1 (PCIe, USB2.0) — Other — Mechanical Dimensions 5.75” x 4” (146mm x 101.7mm) Environmental Operating Temperature 32°F ~ 140°F (0°C ~ 60°C) Storage Temperature -40°F ~ 176°F (-40°C ~ 80°C) Operating Humidity...
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Page 20: Block Diagram
Block Diagram Chapter 1 – Product Specifications... -
Page 21: Chapter 2 - Hardware Information
Chapter 2 Chapter 2 – Hardware Information... -
Page 22: Dimensions
Dimensions Note: Advanced version Note: Standard version Chapter 2 – Hardware Information... - Page 23 Chapter 2 – Hardware Information...
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Page 24: Jumpers And Connectors
Jumpers and Connectors Top View Front I/O View Chapter 2 – Hardware Information... - Page 25 Bottom View Thermal Source 2 Front I/O Chapter 2 – Hardware Information...
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Page 26: List Of Jumpers
List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Front Panel Connector Touch Screen 4/5/8-wire Mode Selection Auto Power Button Enable/ Disable Selection COM2 Pin 8 Function Selection LVDS/eDP Port Backlight Inverter VCC Selection and Operating VDD Selection LVDS/eDP Port Backlight Lightness Control Mode Selection... -
Page 27: Touch Screen 4, 5, 8-Wire Selection (Jp2)
2.3.2 Touch Screen 4, 5, 8-Wire Selection (JP2) 1 2 3 4/8-Wire Mode 5-Wire Mode (Default) 2.3.3 Auto Power Button Enable/Disable Selection (JP3) 1 2 3 Disable/ Enable/ ATX Power Mode AT Power Mode (Default) 2.3.4 COM2 Pin8 Function Selection (JP4) +12V Ring (Default) 2.3.5... -
Page 28: Lvds/Edp Port Backlight Lightness Control Mode Selection (Jp6)
2.3.6 LVDS/eDP Port Backlight Lightness Control Mode Selection (JP6) 1 2 3 VR Mode PWM Mode (Default) 2.3.7 Clear CMOS Jumper (JP7) Normal (Default) Clear CMOS Chapter 2 – Hardware Information... -
Page 29: List Of Connectors
List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function +5V Output for SATA HDD SATA Port External Power Input Audio I/O Port External +5VSB Input DDR4 SO-DIMM Slot COM Port 3, Port 4;... -
Page 30: Output For Sata Hdd (Cn1)
Label Function CN30 Type C Connector (USB3.2 Gen 2 Only) CN31 Battery Connector CN32 SPI BIOS Debug Port CN33 M.2 M Key 2280 CN35 USB3.2 Gen 2 Port 3, Port 4, Dual Port Connector CN36 i219 LED Connector CN37 i225 LED Connector 2.4.1 +5V Output for SATA HDD (CN1) Pin Name... -
Page 31: Sata Port (Cn2)
2.4.2 SATA Port (CN2) Pin 1 Pin 7 Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.4.3 External Power Input (CN3) +12V GND Pin Name Signal Type Signal Level +12V +9~+36V (or +12V) at 8A Note: There are two types of power input, 9~36V or 12V (by BOM option). -
Page 32: Audio I/O Port (Cn5)
2.4.4 Audio I/O Port (CN5) Pin Name Signal Type LOUT_R MIC_R LOUT_L MIC_L JD_LOUT JD_MIC AUD_GND AUD_GND JD_LIN LIN_R +VDD_AUD LIN_L Chapter 2 – Hardware Information... -
Page 33: External +5Vsb Input (Cn6)
2.4.5 External +5VSB Input (CN6) Pin Name Signal Type Signal Level PS_ON# +5VSB +5V at 2A 2.4.6 DDR SO-DIMM Slot (CN7) Standard Specifications Chapter 2 – Hardware Information... -
Page 34: Com Port 3, Port 4 Dual Header (Cn8)
2.4.7 COM Port 3, Port 4 Dual Header (CN8) RS-232 Pin Name Signal Type Signal Level ±5V ±5V ±5V Chapter 2 – Hardware Information... - Page 35 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V RS-422 Pin Name Signal Type Signal Level RS422_TX- RS422_TX+ ±5V RS422_RX+ RS422_RX- Chapter 2 – Hardware Information...
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Page 36: Mini Card Slot (Full-Size) (Cn10)
2.4.8 Mini Card Slot (Full-Size) (CN10) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V Chapter 2 – Hardware Information... - Page 37 Pin Name Signal Type Signal Level PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...
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Page 38: Ddr So-Dimm Slot (Cn11)
Pin Name Signal Type Signal Level +3.3VSB +3.3V 2.4.9 DDR SO-DIMM Slot (CN11) Standard Specifications 2.4.10 M.2 E-Key 2230 (CN12) Standard Specifications 2.4.11 COM Port 1, Port 2 Dual Header (CN13) RS-232 Pin Name Signal Type Signal Level ±5V ±5V Chapter 2 –... - Page 39 Pin Name Signal Type Signal Level ±5V RI/+5V/+12V Note: RI/+5V/+12V for COM2 only. RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V RS-422 Pin Name Signal Type Signal Level RS422_TX- RS422_TX+ ±5V RS422_RX+ RS422_RX- Chapter 2 – Hardware Information...
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Page 40: Touchscreen Connector (Optional) (Cn15)
Pin Name Signal Type Signal Level Note 1: COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. Note 2: Pin 8 function can be set by JP4 (See Ch 2.3.4). 2.4.12 Touchscreen Connector (Optional) (CN15) Note: Touch mode can be set by BIOS. 8-Wire Mode Pin Name Signal Type... - Page 41 4-Wire Mode Pin Name Signal Type Signal Level BOTTOM LEFT RIGHT Chapter 2 – Hardware Information...
- Page 42 5-Wire Mode Pin Name Signal Type Signal Level UL(Y) UR(H) LL(L) LR(X) SENSE(S) Note: Touch Mode can be set by BIOS Chapter 2 – Hardware Information...
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Page 43: Espi Debug Port (Cn16)
2.4.13 eSPI Debug Port (CN16) Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK SMB_DATA/I2C_SDA SMB_CLK/I2C_CLK SMB_ALERT/SERIRQ +3.3V Chapter 2 – Hardware Information... -
Page 44: Digital I/O Connector (Cn17)
2.4.14 Digital I/O Connector (CN17) Signal Description Signal Description +V5S (0.5A) 2.4.15 LVDS/eDP Port (CN18) Note: LVDS LCD_PWR can be set to +3.3V or +5V by JP5. (See Ch 2.3.5) Note: LVDS LCD_PWR supports current of 2A Chapter 2 – Hardware Information... - Page 45 LVDS Signal Type Signal Level BKL_ENABLE BKL_ENABLE BKL_CONTROL BKL_CONTROL LCD_PWR LCD_PWR +3.3V/+5V LVDS_A_CLK- eDP_TXN3 DIFF LVDS_A_CLK+ eDP_TXP3 DIFF LCD_PWR LCD_PWR +3.3V/+5V LVDS_DA0- eDP_TXN2 DIFF LVDS_DA0+ eDP_TXP2 DIFF LVDS_DA1- eDP_TXN1 DIFF LVDS_DA1+ eDP_TXP1 DIFF LVDS_DA2- eDP_TXN0 DIFF LVDS_DA2+ eDP_TXP0 DIFF LVDS_DA3- DIFF LVDS_DA3+ eDP_HPD...
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Page 46: Nano Sim Card Socket (Cn19)
LVDS Signal Type Signal Level LCD_PWR LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF 2.4.16 Nano SIM Card Socket (CN19) Pin Name Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information... -
Page 47: Usb 2.0 Port 5, Port 6 Dual Header (Cn21)
2.4.17 USB 2.0 Port 5, Port 6 Dual Header (CN21) USB Port 5 USB Port 6 Pin Name Pin Name +5VSB (0.5A) +5VSB (0.5A) USB5_D- USB6_D- USB5_D+ USB6_D+ Chapter 2 – Hardware Information... -
Page 48: Lvds/Edp Port Inverter/ Backlight Connector (Cn22)
2.4.18 LVDS/eDP Port Inverter/ Backlight Connector (CN22) Pin Name Signal Type Signal level BKL_PWR +5V / +12V BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE +3.3V Note 1: LVDS BKL_PWR can be set to +5V or +12V by JP5. (See Ch 2.3.5) Note 2: LVDS BKL_PWR supports current of 1.5A Note 3: LVDS BKL_CONTROL can be set by JP6. -
Page 49: Cpu Fan (Cn23)
2.4.19 CPU Fan (CN23) Pin Name Signal Type Signal Level FAN_POWER +12V at 1A FAN_TAC FAN_CTL 2.4.20 USB 3.2 Gen 2 Ports 1 & 2 Dual Connector (CN26) Pin Name Signal Type Signal Level +5VSB +5V at 0.9A USB0_D- DIFF USB0_D+ DIFF USB0_SSRX−... -
Page 50: Lan (Rj-45) Dual Port I225 And I219 (Cn27)
Pin Name Signal Type Signal Level USB0_SSTX− DIFF USB0_SSTX+ DIFF +5VSB +5V at 0.9A USB1_D- DIFF USB1_D+ DIFF USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF 2.4.21 LAN (RJ-45) Dual Port i225 and i219 (CN27) i225 i219 Pin Name Pin Name LAN2_MDI0_P LAN1_MDI0_P LAN2_MDI0_N... -
Page 51: Dp Connector (Cn28)
i225 i219 Pin Name Pin Name LAN2_MDI2_N LAN1_MDI2_N LAN2_MDI3_P LAN1_MDI3_P 1P10 LAN2_MDI3_N 2P10 LAN1_MDI3_N 2.4.22 DP Connector (CN28) Pin Name Signal Type Signal Level DP1_TX0_DP DIFF DP1_TX0_DN DIFF DP1_TX1_DP DIFF DP1_TX1_DN DIFF DP1_TX2_DP DIFF DP1_TX2_DN DIFF DP1_TX3_DP DIFF DP1_TX3_DN DIFF Chapter 2 –... -
Page 52: Dp + Hdmi Connector (Cn29)
Pin Name Signal Type Signal Level DP1_AUX_DP DP1_AUX_DN DP1_HPD +V3P3S +3.3V 2.4.23 DP + HDMI Connector (CN29) Pin Name Signal Type Signal Level DP Port DP2_TX0_DP DIFF DP2_TX0_DN DIFF DP2_TX1_DP DIFF DP2_TX1_DN DIFF DP2_TX2_DP DIFF Chapter 2 – Hardware Information... - Page 53 Pin Name Signal Type Signal Level DP2_TX2_DN DIFF DP2_TX3_DP DIFF DP2_TX3_DN DIFF DP2_AUX_DP DP2_AUX_DN DP2_HPD +V3P3S +3.3V HDMI Port HDMI_TX2+ DIFF HDMI_TX2- DIFF HDMI_TX1+ DIFF HDMI_TX1- DIFF HDMI_TX0+ DIFF HDMI_TX0- DIFF HDMI_CLK+ DIFF HDMI_CLK- DIFF Chapter 2 – Hardware Information...
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Page 54: Battery Connector (Cn31)
Pin Name Signal Type Signal Level DDC_CLK DDC_DATA HDMI_HPD 2.4.24 Battery Connector (CN31) Pin Name Signal Type Signal Level +3.3V 3.3V Chapter 2 – Hardware Information... -
Page 55: Spi Bios Debug Port (Cn32)
2.4.25 SPI BIOS Debug Port (CN32) Pin Name Signal Type Signal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI SPI_CS 2.4.26 M.2 M-Key 2280 Slot (CN33) Standard specifications Chapter 2 – Hardware Information... -
Page 56: Usb3.2 Gen 2 Ports 3 & 4 Dual Connector (Cn35)
2.4.27 USB3.2 Gen 2 Ports 3 & 4 Dual Connector (CN35) Pin Name Signal Type Signal Level +5VSB +5V at 0.9A USB2_D- DIFF USB2_D+ DIFF USB2_SSRX− DIFF USB2_SSRX+ DIFF USB2_SSTX− DIFF USB2_SSTX+ DIFF +5VSB +5V at 0.9A USB3_D- DIFF USB3_D+ DIFF USB3_SSRX−... -
Page 57: I219 Led Connector (Cn36)
2.4.28 i219 LED Connector (CN36) Pin Name Signal Type Signal Level LINK_ACT# +V3P3A +3.3V LAN_1000# LAN_100# LAN_100# LAN_1000# 2.4.29 i225 LED Connector (CN37) Pin Name Signal Type Signal Level LINK_ACT# +V3P3A +3.3V LAN_2500# LAN_1000# LAN_1000# LAN_2500# Chapter 2 – Hardware Information... -
Page 58: Thermal Solutions
Thermal Solutions 2.5.1 GENE-TGU6-FAN01 Single piece cooler, does not require use of heat spreader Chapter 2 – Hardware Information... - Page 59 GENE-TGU6-FAN01 Assembly Chapter 2 – Hardware Information...
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Page 60: Gene-Tgu6-Hsk01
2.5.2 GENE-TGU6-HSK01 Single-piece heat sink, does not require use of heat spreader. Chapter 2 – Hardware Information... - Page 61 GENE-TGU6-HSK01 Assembly Chapter 2 – Hardware Information...
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Page 62: Gene-Tgu6-Hsp01
2.5.3 GENE-TGU6-HSP01 Chapter 2 – Hardware Information... - Page 63 GENE-TGU6-HSP01 Assembly Chapter 2 – Hardware Information...
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Page 64: Chapter 3 - Ami Bios Setup
Chapter 3 Chapter 3 - AMI BIOS Setup... -
Page 65: System Test And Initialization
System Test and Initialization The GENE-TGU6 board uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the module will output a few short beeps or display an error message. The module can usually continue the boot up sequence with non-fatal errors. -
Page 66: Ami Bios Setup
AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>... -
Page 67: Setup Submenu: Main
Setup Submenu: Main Chapter 3 – AMI BIOS Setup... -
Page 68: Setup Submenu: Advanced
Setup Submenu: Advanced Options Summary In-Band ECC Support Disabled Enabled Optimal Default; Failsafe Default Enable/Disabled In-Band ECC Support In-Band ECC Error Enabled Injection Disabled Optimal Default, Failsafe Default By enabling this Error Injection feature, the user acknowledges the security risks. Enabling Error Injection allows attackers who have access to the Host Operating System to inject IBECC errors that can cause unintended memory corruption and enable the leak of security data in the BIOS stolen memory regions. - Page 69 Options Summary IBECC Protect Region 0-7 Disabled Optimal Default, Failsafe Default Enabled Enable/Disabled In-Band ECC for Region 0-7 Note: In-Band ECC Support availability depends on CPU. Chapter 3 – AMI BIOS Setup...
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Page 70: Graphics Configuration
3.4.1 Graphics Configuration Chapter 3 – AMI BIOS Setup... -
Page 71: Lvds Panel Configuration
3.4.1.1 LVDS Panel Configuration Options Summary LVDS/eDP Disabled Optimal Default, Failsafe Default Enabled Enable/Disabled this panel. LVDS Panel Type 640X480@60HZ 800X480@60HZ 800X600@60HZ 1024X600@60HZ 1024X768@60HZ Optimal Default, Failsafe Default 1280X768@60HZ 1280X800@60HZ 1280X1024@60HZ 1366X768@60HZ 1440X900@60HZ 1600X1200@60HZ 1920X1080@60HZ 1920X1200@60HZ Chapter 3 – AMI BIOS Setup... - Page 72 Options Summary Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel type Backlight Mode BIOS & Application Windows Slider Optimal Default, Failsafe Default Select backlight control signal type Backlight Type Normal...
- Page 73 Options Summary Swing Level 450mV Select Swing Level Center Spreading Depth no spreading Optimal Default, Failsafe Default 0.5% 1.0% 1.5% 2.0% 2.5% Select Center Spreading Depth Chapter 3 – AMI BIOS Setup...
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Page 74: Cpu Configuration
3.4.2 CPU Configuration Options Summary Intel (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. Intel(R) SpeedStep(tm) Disabled Enabled Optimal Default, Failsafe Default Allows more than two frequency ranges to be supported. Turbo Mode Disabled Enabled... -
Page 75: Memory Configuration
3.4.3 Memory Configuration Chapter 3 – AMI BIOS Setup... -
Page 76: Hardware Monitor
3.4.4 Hardware Monitor Options Summary Smart Fan Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Smart Fan Chapter 3 – AMI BIOS Setup... -
Page 77: Smart Fan Mode Configuration
3.4.4.1 Smart Fan Mode Configuration Auto Duty Cycle Mode Options Summary FAN1 Output Mode Output PWM mode (push pull) Linear Fan Application Output PWM mode Optimal Default, Failsafe Default (open drain) Output PWM mode (push pull) to control 4-wire fans.\nLinear fan application circuit to control 3-wire fan speed by fan’s power terminal.\nOutput PWM mode (open drain) to control Intel 4-wire fans. - Page 78 Options Summary Duty Cycle Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Temperature Manual Duty Mode Options Summary Manual Duty Mode Optimal Default, Failsafe Default Manual mode fan control, user can write expected duty cycle (PWM fan type) 1-100 Chapter 3 –...
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Page 79: Pch-Fw Configuration
3.4.5 PCH-FW Configuration Chapter 3 – AMI BIOS Setup... -
Page 80: Firmware Update Configuration
3.4.5.1 Firmware Update Configuration Options Summary Me FW Image Re-Flash Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Me FW Image Re-Flash function. FW Update Disabled Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup... -
Page 81: Power Management
3.4.6 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off IO Restore AC power Loss RTC wake system from S5 Disable Optimal Default, Failsafe Default Fixed Time... -
Page 82: Aaeon Bios Robot
3.4.7 AAEON BIOS Robot Options Summary Sends watch dog before Disabled Optimal Default, Failsafe Default BIOS POST Enabled Enabled - Robot set Watch Dog Time r(WDT) right after power on, before BIOS start POST process. Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero. - Page 83 Options Summary OS Timer (minute) Optimal Default, Failsafe Default Timer count set to Watch Dog Timer for OS loading. Delayed POST (PEI phase) Disabled Optimal Default, Failsafe Default Enabled Enabled - Robot holds BIOS from starting POST, right after power on. This allows BIOS POST to start with stable power or start after system is physically warmed-up.
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Page 84: Device Detecting Configuration
3.4.7.1 Device Detecting Configuration Action: Rest System Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Soft or hard reset Soft Optimal Default, Failsafe Default Hard Select reset type robot should send on each boot. Retry-Count Optimal Default, Failsafe Default Fill retry counter here. - Page 85 Action: Hold System Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Holding time out Optimal Default, Failsafe Default (second) Fill hold time out here. Robot will hold system no longer then time-out value, and then let system continue its POST.
- Page 86 3.4.7.1.1 Device # Detecting Configuration Interface: Disabled Options Summary Interface Disabled Optimal Default, Failsafe Default SMBUS Legacy I/O Super I/O MMIO Select interface robot should use to communicate with device. Chapter 3 – AMI BIOS Setup...
- Page 87 Interface: PCI Options Summary Optimal Default, Failsafe Default Fill BUS number to a PCI device, in hexadecimal. Range: 0 - FF Device Optimal Default, Failsafe Default Fill DEVICE number to a PCI device, in hexadecimal. Range: 0 - FF Function Optimal Default, Failsafe Default Fill FUNCTION number to a PCI device, in hexadecimal.
- Page 88 Options Summary Register data is bitwise equal to Optimal Default, Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register, to a value configured below. Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal.
- Page 89 Interface: DIO Options Summary Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. DIO pin number DIO1 Optimal Default, Failsafe Default DIO* Fill DIO pin number. 0 - DIO0, 1 - DIO1, and so on. For COM express product: 0-3 - GPI0-3, 4-7 - GPO0-3 Device Is not...
- Page 90 Interface: SMBUS Options Summary SMBUS Slave Address Optimal Default, Failsafe Default Fill slave address to a SMBUS device, in hexadecimal. Range: 0 - FF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default...
- Page 91 Options Summary Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal. Range: 0 - FF Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High...
- Page 92 Interface: Legacy I/O Options Summary I/O Address Optimal Default, Failsafe Default Fill I/O address device is responding to. Range: 0~FFFF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default Specified register data...
- Page 93 Options Summary Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. Byte value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.
- Page 94 Interface: Super I/O Options Summary Super I/O LDN Optimal Default, Failsafe Default Fill LDN number to a Super I/O device. Range: 0~FF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default...
- Page 95 Options Summary Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal. Range: 0 - FF Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High...
- Page 96 Interface: MMIO Options Summary MMIO Address Optimal Default, Failsafe Default Fill Memory Mapped I/O address device is responding to. Range: 0~FFFFFFFF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default...
- Page 97 Options Summary Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. Byte value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.
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Page 98: Tsn Gbe Configuration
3.4.8 TSN GBE Configuration Options Summary PCH TSN LAN Enabled Optimal Default, Failsafe Default Controller Disabled Enable/Disable TSN LAN Enable Timed TSN Disabled Optimal Default, Failsafe Default Enabled Enable/Disable TSN PCS. When enabled, TSN PCS device will appear in ACPI table PCH TSN Multi-Vc Disabled Optimal Default, Failsafe Default... -
Page 99: Setup Submenu: System I/O
Setup Submenu: System I/O Chapter 3 – AMI BIOS Setup... -
Page 100: Pci Express Configuration
3.5.1 PCI Express Configuration Options Summary PCI Express Root Port 5 Enabled Optimal Default, Failsafe Default (CN12) / Port11 Disabled Control the PCI Express Root Port. PCIe Speed Auto Optimal Default, Failsafe Default Gen1 Gen2 Gen3 Control the PCI Express Speed Chapter 3 –... -
Page 101: Storage Configuration
3.5.2 Storage Configuration Options Summary SATA Controller(s) Disabled Enabled Optimal Default, Failsafe Default Enable/Disable SATA Device. Port 0 / 1 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port Hot Plug Disabled Optimal Default, Failsafe Default Enabled Designates this port as Hot Pluggable. Chapter 3 –... -
Page 102: Nvme Configuration
3.5.2.1 NVMe Configuration Chapter 3 – AMI BIOS Setup... -
Page 103: Hd Audio Subsystem Configuration Settings
3.5.3 HD Audio Subsystem Configuration Settings Options Summary HD Audio Disabled Enabled Optimal Default, Failsafe Default Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled. Chapter 3 – AMI BIOS Setup... -
Page 104: Digital Io Port Configuration
3.5.4 Digital IO Port Configuration Options Summary DIO Port # Output Input Set DIO as Input or Output Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup... -
Page 105: Legacy Logical Devices Configuration
3.5.5 Legacy Logical Devices Configuration Chapter 3 – AMI BIOS Setup... -
Page 106: Serial Port 1 Configuration
3.5.5.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts. -
Page 107: Serial Port 2 Configuration
3.5.5.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts. -
Page 108: Serial Port 3 Configuration
3.5.5.3 Serial Port 3 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3E8h; IRQ=11 IO=2E8h; IRQ=11 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts. -
Page 109: Serial Port 4 Configuration
3.5.5.4 Serial Port 4 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2E8h; IRQ=11 IO=3E8h; IRQ=11 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts. -
Page 110: Serial Port Console Redirection
3.5.6 Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Console Redirection EMS Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup... -
Page 111: Console Redirection Settings
3.5.6.1 Console Redirection Settings Options Summary Terminal Type VT100 VT100+ VT-UTF8 ANSI Optimal Default, Failsafe Default Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. - Page 112 Options Summary Parity None Optimal Default, Failsafe Default Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd.
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Page 113: Pch-Io Configuration
3.5.7 PCH-IO Configuration Options Summary MiniCard Slot Function SATA Optimal Default, Failsafe Default PCIe Select function enabled for Full size MiniCard Slot (CN10) Chapter 3 – AMI BIOS Setup... -
Page 114: Setup Submenu: Security
Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility. -
Page 115: Trusted Computing
3.6.1 Trusted Computing Options Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default... - Page 116 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy Endorsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec Version TCG_1_2 TCG_2...
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Page 117: Secure Boot
3.6.2 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom Optimal Default, Failsafe Default... -
Page 118: Key Management
3.6.1.1 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Restore Factory Keys Force System to User Mode. - Page 119 Options Summary Remove 'UEFI CA' from Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) Restore DB defaults Restore DB variable to factory defaults Platform Key(PK) Details Export Update Delete Key Exchange Keys Details Export Update...
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Page 120: Setup Submenu: Boot
Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables showing boot logo. Network Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup... -
Page 121: Bbs Priorities
3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup... -
Page 122: Setup Submenu: Save & Exit
Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup... -
Page 123: Chapter 4 - Driver Installation
Chapter 4 Chapter 4 – Driver Installation... -
Page 124: Driver Download/Installation
Driver Download/Installation Drivers for the GENE-TGU6 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/3-and-half-inch-sbc-gene-tgu6 Download the driver(s) you need and follow the steps below to install them. Audio Driver (Windows 10) Open the folder where you unzipped the Audio Drivers Run the Setup.exe in the folder Follow the instructions Drivers will be installed automatically... - Page 125 LAN Drivers (Windows 10) Open the folder where you unzipped the LAN Drivers Read the ReadMe.txt file before proceeding. Caution: Be sure to install the driver package before installing the Intel® PROSet package. Open the Wired_driver_26.3_x64 folder Run the Wired_driver_26.3_x64.exe file in the folder Follow the instructions, drivers will be installed automatically.
- Page 126 Touch Drivers (Windows 10) Open the folder where you unzipped the Peripheral Drivers Run the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Peripheral Driver (Linux) Open the folder where you unzipped the Peripheral Drivers Follow the instructions contained within the user guides Touch Drivers (Linux) Touch Drivers can be installed via terminal, or through the graphical UI if...
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Page 127: Appendix A - I/O Information
Appendix A Appendix A - I/O Information... -
Page 128: I/O Address Map
I/O Address Map Appendix A – I/O Information... -
Page 129: A.2 Memory Address Map
A.2 Memory Address Map Appendix A – I/O Information... - Page 130 Appendix A – I/O Information...
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Page 131: A.3 Irq Mapping Chart
A.3 IRQ Mapping Chart Appendix A – I/O Information... - Page 132 Appendix A – I/O Information...
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Page 133: Appendix B - Mating Connectors And Cables
Appendix B Appendix B – Mating Connectors and Cables... -
Page 134: Mating Connectors And Cables
Mating Connectors and Cables Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model no Front Panel Flyingway FWAA-1049 LED cable 1709100108 Connector +5Vout 2 Pins for PINREX PHR-2 1702150155 Connector HDD Power SATA Molex 887505318 SATA Cable 1709070460 Connector +9~36V Vin Power Cable... - Page 135 Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model no Digital I/O CN17 Neltron 2026B-10 Connector LVDS DF13-30DS-1. CN18 HIROSE Connector USB Port 50238-01041- USB Wafer CN21 Aces 170010010D Connector Cable LVDS 50228-00671- Inverter CN22 Inverter Aces 170X000152 cable Connector CPU Fan...