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Specifications
| The following figure describes system board performance.
Access to Channel:
Single Transfer:
Burst Transfers:
Number
Device
of Waits
Cycle Time (ns)
Microprocessor (10 MHz
— 100 ns Clock):
Access to System Board RAM
1
300
Access to System Board ROM
1
300
Default Transfer Cycle:
I/O Access
1
300
Memory Access
0
200
Synchronous Extended Transfer Cycle
1
300
Refresh Rate
500 (min)
(Typically performed every 15.1 ys)
Bus Master Access to System Board RAM
300 (min)
DMA Controller (10 MHz
~ 100 ns Clock):
300 + I/O Access + Memory Access
300 + (1/0 Access + Memory Access)N *
System Board Memory Access
300
Default Transfer Cycle:
1/0 Access
300
Memory Access
200
Synchronous Extended Transfer Cycle
300
* N is the number of transfers in the burst.
Figure
1-4. Performance Specifications
— System Board
Model 60 System Overview
— October 1990
1-7
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