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IBM DARA-206000 - Travelstar 12 GB Hard Drive Specifications
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IBM DARA-206000 - Travelstar 12 GB Hard Drive Specifications

IBM DARA-206000 - Travelstar 12 GB Hard Drive Specifications

Dara-2 series 6 gb - 25 gb 2.5-inch hard disk drive with ata interface
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S25L-1638-03
OEM HARD DISK DRIVE SPECIFICATIONS
for
DARA-2xxxxx
( 6 GB - 25 GB )
2.5-Inch Hard Disk Drive with ATA Interface
Revision (2.1)

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  • Page 1 S25L-1638-03 OEM HARD DISK DRIVE SPECIFICATIONS DARA-2xxxxx ( 6 GB - 25 GB ) 2.5-Inch Hard Disk Drive with ATA Interface Revision (2.1)
  • Page 3 S25L-1638-03 OEM HARD DISK DRIVE SPECIFICATIONS DARA-2xxxxx ( 6 GB - 25 GB ) 2.5-Inch Hard Disk Drive with ATA Interface Revision (2.1)
  • Page 4 This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

  • Page 5: Table Of Contents

    ......... Copyright IBM Corp. 1999...
  • Page 6 5.5 Vibration and Shock ..........5.5.1 Operating Vibration .
  • Page 7 9.10 Features Register ..........9.11 Sector Count Register .
  • Page 8 11.3 Non-Data Commands ..........11.4 D M A Data Transfer Commands .
  • Page 9 Index ............Contents...
  • Page 10 viii O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 11: General

    1.0 General This document describes the specifications of the following IBM 2.5-inch, ATA interface hard disk drives: DARA-206000 ( 6 GB) 9.5mm height 4200 rpm DARA-209000 ( 9 GB) 9.5mm height 4200 rpm DARA-212000 (12 GB) 9.5mm height 4200 rpm DARA-215000 (15 GB) 12.7mm height 4200 rpm...

  • Page 12: Caution Of Usage

    1.2.1 Caution of usage Figure 1. Handling caution of DARA-2xxxxx O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...
  • Page 13 Figure 2. Breathing hole caution of DARA-2xxxxx General...
  • Page 14 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 15: General Features

    800 G/1ms (DARA-212000/209000/206000) 700 G/1ms (DARA-218000/215000) 500 G/2ms (DARA-225000) Operating Shock 175 G/2ms (DARA-218000/215000/212000/209000/206000) 150 G/2ms (DARA-225000) Address Offset Feature to support D F T implementation Note: Mounting screw position is Incompatible with DBOA/DMCA/DCRA/DSOA/DPRA-2xxxx. Compatible with DTNA/DLGA/DDLA/DTCA/DPLA/DYKA/DYLA/DADA/ DKLA/DBCA/DCXA/DCYA-2xxxxx. Copyright IBM Corp. 1999...
  • Page 16 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 17: Part 1. Functional Specification

    Part 1. Functional Specification Copyright IBM Corp. 1999...
  • Page 18 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 19: Drive Characteristics

    Number of zone Number of disks 1 / 2 / 2 / 3 / 3 / 5 Number of heads 2 / 3 / 4 / 5 / 6 / 10 Servo design method Embedded sector servo Copyright IBM Corp. 1999...

  • Page 20: Performance Characteristics

    3.3 Performance Characteristics File performance is characterized by the following parameters: Command Overhead Mechanical Positioning Seek Time Latency Data Transfer Speed Buffering Operation Note: All the above parameters contribute to a file performance. There are other parameters which con- tribute to the performance on the actual system. This specification tries to define the essential file character- istics, not the system throughput which is dependent on the system and the application.

  • Page 21: Command Processing

    3.3.1 Command Processing Command overhead time is defined as the total time from when the command is received by the drive to the start of motion of the actuator. 3.3.2 Average Seek Time (Including Settling) Command Type Typical Read 12 msec 16 msec Write 14 msec (except DARA-225000)

  • Page 22: Full Stroke Seek

    3.3.4 Full Stroke Seek Function Typical Read 23.0 msec 30.0 msec Write 24.0 msec 31.0 msec Figure 8. Full Stroke Seek Time Full stroke seek is measured as the average of 1000 full stroke seeks. 3.3.5 Average Latency Model Time for a revolution Average Latency DARA-225000 5411...

  • Page 23: Operating Modes

    3.3.7 Operating Modes. O p e r a t i n g m o d e D e s c r i p t i o n S p i n U p S t a r t u p t i m e p e r i o d f r o m s p i n d l e s t o p o r p o w e r d o w n . S e e k S e e k o p e r a t i o n m o d e W r i t e...

  • Page 24: Mode Transition Time

    3.3.7.1 Mode Transition Time. Model From Transition Time DARA-225000 Standby Idle 4.5 sec (typical) / 9.5 sec (max) Others Standby Idle 1.8 sec (typical) / 9.5 sec (max) Figure 12. Drive Ready Time 3.3.7.2 Operating mode at power on The device goes to Idle mode after power on or hard reset as an initial state. Initial state may be changed to Standby mode using pin C on the interface connector.

  • Page 25: Data Integrity

    Appropriate error status is made available to the host system if any of the following conditions occur after the drive has once become ready: Spindle speed outside requirements for reliable operation. Occurrence of a Write Fault condition. Copyright IBM Corp. 1999...

  • Page 26: Write Safety

    4.4 WRITE Safety The drive ensures that the data is written into the disk media properly. Following conditions are monitored during a write operation. When one of those conditions exceeds the criteria, the write operation is terminated and automatic retry sequence will be invoked. Head off track External shock Low supply voltage...

  • Page 27: Specification

    The system has to provide sufficient ventilation to maintain a surface temperature below 60 ˚ C at the center of the top cover of the drive. Non-condensing should be kept at any time. Maximum storage period with shipping package is one year. Figure 14. Limits of Temperature and Humidity Copyright IBM Corp. 1999...

  • Page 28: Magnetic Fields

    5.1.2 Magnetic Fields The disk drive will withstand radiation & conductive noise within the limits shown below. 5.1.2.1 Radiation Noise The disk drive shall work without degradation of the soft error rate under the following Magnetic Flux Density Limits at the enclosure surface. Frequency ( KHz ) Limits ( Gauss rms ) 0 - 60...

  • Page 29: Dc Power Requirements

    5.2 DC Power Requirements Connection to the product should be made in isolated secondary circuits (SELV). The voltage specifications are applied at the power connector of the drive. Item Requirements Notes Nominal Supply + 5 Volt Power Supply Ripple ( 0- 20Mhz) 100 mv p-p max Tolerance + / - 5 %...
  • Page 30 (*2) The disk drive shall not incur damage for an over voltage condition of + 2 5 % (maximum duration of 20 ms) on the 5-volt nominal supply. (*3) The idle current is specified at an inner track. (*4) The read/write current is specified based on three operations of 63 sector read/write per 100 msec. (*5) The seek average current is specified based on three operations per 100 msec.

  • Page 31: Start Up Current

    5.2.1 Start Up Current Figure 17. Typical current wave form at start up of DARA-212000/209000/206000 Figure 18. Typical current wave form at start up of DARA-218000/215000 Specification...
  • Page 32 Figure 19. Typical current wave form at start up of DARA-225000 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 33: Reliability

    Service life of DARA-2xxxxx is approximately 5 years or 15,000 (20,000 for DARA-225000) power-on hours, whichever comes first. Actual product life and failure rate depend on duty cycle and environmental conditions. Consult your IBM representative for reliability estimate if atypical operating conditions are anticipated. 5.3.5 Preventive Maintenance None.

  • Page 34: Load/Unload

    5.3.6 Load/Unload The product supports a minimum of 300,000 normal load/unloads. Load/unload is a functional mechanism of the HDD. It is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the commands: Hard Reset Soft Reset Standby Standby Immediate Sleep...
  • Page 35 DARA-2xxxxx invokes the emergency unload mechanism, and subjects the H D D to non- typical mechanical stress. Power cycling testing may be required to test the boot-up function of the system. In this case IBM recom- mends that the power-off portion of the cycle contain the sequence specified in 5.3.6.2, “ Required Power-Off Sequence”...

  • Page 36: Mechanical Specifications

    5.4 Mechanical Specifications 5.4.1 Mechanical Dimensions and Weight The following chart describes the dimensions for the 2.5" hard disk drive form factor. Model Height (mm) Width (mm) Length (mm) Weight (gram) DARA-212000/209000/206000 9.5 ± 0.2 69.85 ± 0.25 100.2 ± 0.25 99 Max DARA-218000/215000 12.7 +0.0/-0.5...
  • Page 37 Figure 22. Hole Location of DARA-218000/215000 Figure 23. Hole Location of DARA-225000 Specification...

  • Page 38: Mounting Orientation

    5.4.3 Mounting Orientation The drive will operate in all axes (6 directions). The drive will operate within the specified error rates when tilted ± 5 degree from these positions. Performance and error rate will stay within specification limits if the drive is operated in the other permis- sible orientations from which it was formatted.

  • Page 39: Vibration And Shock

    5.5 Vibration and Shock All vibration and shock measurements in this section shall be for the disk drive without the mounting attach- ments for the systems. The input level shall be applied to the normal drive mounting points. Vibration test and shock test are to be conducted by mounting the drive to the table using the bottom four screws.

  • Page 40: Operating Shock

    5.5.2.2 Swept Sine Vibration 25.4mm (peak to peak) displacement, 5 to 10 to 5 Hz 5 G (zero to peak), 10 to 500 to 10 Hz sine wave 0.5 oct/min sweep rate 5.5.3 Operating Shock The drive meets the following criteria. DARA-218000/215000/212000/209000/206000.

  • Page 41: Acoustics

    5.6 Acoustics 5.6.1 Sound Power Level The criteria of A-weighted sound power level is described below. Measurements are to be taken in accordance with ISO 7779. The mean of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. Drives are to meet this requirement in both board down orientations.

  • Page 42: Discrete Tone Penalty

    5.6.2 Discrete Tone Penalty Discrete tone penalties are added to the A-weighted sound power (Lw) with following formula only when determining compliance. Lwt(spec)=Lw+0.1*Pt+0.3 < 4.0 (Bels) where: : A-weighted sound power level. : Value of discrete tone penalty = dLt-6.0 (dBA) : Tone-to-noise ratio taken in accordance with ISO 7779.

  • Page 43: Identification

    5.7.1 Labels The following labels are affixed to every disk drive . A label placed on the top of the HDA containing the statement 'Made by IBM' or equivalent, Part No., EC No. and F R U No. A bar code label placed on the disk drive based on user request. The location on the disk drive is to be designated in the drawing.

  • Page 44: Safety

    5.9 Safety 5.9.1 Underwriters Lab(UL) Approval DARA-2xxxxx complies with UL 1950:1995+A1. 5.9.2 Canadian Standards Authority(CSA) Approval DARA-2xxxxx complies with CSA C22.2 950-M1995. 5.9.3 IEC Compliance DARA-2xxxxx complies with IEC 950:1991+A1-4. 5.9.4 German Safety Mark DARA-2xxxxx are approved by TUV on Test Requirement: EN 60 950:1992+A1-4.

  • Page 45: Electrical Interface Specifications

    Figure 25. AT Attachment connector of DARA-2xxxxx Note 1 : Pin position 20 is left blank for correct connector insertion. Note 2 : Pin position A,B,C,D are used for drive address setting. (Refer to Figure 48 on page 58 for address setting.) Copyright IBM Corp. 1999...

  • Page 46: Signal Definition

    6.2.1 Signal Definition The pin assignments of interface signals are listed as follows: P I N S I G N A L I / O T y p e P I N S I G N A L I / O T y p e R E S E T T T L...
  • Page 47 7. "(Resv)" designates reserved pin which must be left unconnected. DD00-DD15 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer. These are 3-State lines with 24 mA current sink capability.
  • Page 48 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready ( D R D Y = 1 ) . CSEL (Cable Select) This signal is monitored to determine the drive address, 0 or 1, when the jumper on the interface connector is at Position-3.

  • Page 49: Interface Logic Signal Levels

    -DDMARDY (Ultra DMA) This signal is used only for Ultra D M A data transfers between host and drive. -DDMARDY is a flow control signal for Ultra D M A data out bursts. This signal is held asserted by the device to indicate to the host that the device is ready to receive Ultra D M A data out transfers.

  • Page 50: Reset Timings

    6.4 Reset timings H D D reset timing. R E S E T < > B U S Y X X X X X X X < > P A R A M E T E R D E S C R I P T I O N M i n M a x ( u s e c )

  • Page 51: Pio Timings

    6.5 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. C S 0 , C S 1 + D A 0 2 < > < T 1 > < > D I O R , D I O W <...

  • Page 52: Dma Timings (Single Word)

    6.5.1 DMA Timings (Single Word) The Single Word D M A timing meets Mode 2 of the ATA-3 description. + D M A R Q < > < > : D M A C K > T I < > T J < D I O R / D I O W <...

  • Page 53: Dma Timings (Multiword)

    6.5.2 DMA Timings (Multiword) The Multiword D M A timing meets Mode 2 of the ATA-3 description. + D M A R Q < T L > D M A C K < > > T J < > T I < >...

  • Page 54: Ultra Dma Timings

    6.5.3 Ultra DMA Timings The Ultra D M A timing meets Mode 0,1,2,3 and 4 of the Ultra D M A Protocol. 6.5.3.1 Initiating Read DMA D M A R Q < T u i > D M A C K <...
  • Page 55 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 56: Host Pausing Read Dma

    6.5.3.2 Host Pausing Read DMA D M A R Q D M A C K S T O P < T s r > H D M A R D Y < T r f s > D S T R O B E Figure 34.

  • Page 57: Host Terminating Read Dma

    6.5.3.3 Host Terminating Read DMA < T l i > D M A R Q < T m l i > D M A C K < T r p > < T a c k > S T O P <...
  • Page 58 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 59: Device Terminating Read Dma

    6.5.3.4 Device Terminating Read DMA < > T s s D M A R Q < T m l i > D M A C K < T l i > < T a c k > S T O P <...
  • Page 60 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 61: Initiating Write Dma

    6.5.3.5 Initiating Write DMA D M A R Q < T u i > D M A C K < T a c k > < T e n v > S T O P T z r d y > <...
  • Page 62 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 63: Device Pausing Write Dma

    6.5.3.6 Device Pausing Write DMA D M A R Q D M A C K S T O P < T s r > D D M A R D Y < T r f s > H S T R O B E Figure 42.

  • Page 64: Device Terminating Write Dma

    6.5.3.7 Device Terminating Write DMA < T r p > D M A R Q < T m l i > D M A C K < T a c k > S T O P < > T r d y z D D M A R D Y <...
  • Page 65 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 66: Host Terminating Write Dma

    6.5.3.8 Host Terminating Write DMA < T l i > D M A R Q < T m l i > D M A C K < > T s s < T a c k > S T O P <...
  • Page 67 [ n s e c ] M O D E 0 M O D E 1 M O D E 2 P A R A M E T E R D E S C R I P T I O N M I N M A X M I N...

  • Page 68: Drive Address Setting

    6.6 Drive Address Setting A jumper is available at the interface connector to determine the drive address. The set position of the jumper is as shown in Figure 48. Using Cable Selection, the drive address depends on the condition of pin 28 of the AT interface cable. In the case when pin 28 is ground or low, the drive is a Master.

  • Page 69: Addressing Of Drive Registers

    The -HCS0 is used to address Command Block registers. while the -HCS1 is used to address Control Block registers. The following table shows the standard I/O address range for IBM PC-AT machines. A d d r . C S 0...
  • Page 70 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 71: Part 2. Ata Interface Specification

    Part 2. ATA Interface Specification Copyright IBM Corp. 1999...
  • Page 72 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 73: General

    Host indicates the system that the device is attached to. First Command The command which is executed first right after power on reset or hard reset when the initial power mode at power on is Standby mode. INTRQ Interrupt request (Device or Host) Copyright IBM Corp. 1999...
  • Page 74 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 75: Deviations From Standard

    Count register value) x 5 seconds. Check Power Mode While the drive is in idle mode, F F h is returned as a response to Check Power Mode command. 80h is not used for the response. Copyright IBM Corp. 1999...
  • Page 76 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 77: Registers

    The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status. 9.1 Alternate Status Register Copyright IBM Corp. 1999...

  • Page 78: Command Register

    A l t e r n a t e S t a t u s R e g i s t e r B S Y R D Y D S C D R Q C O R I D X E R R Figure 51.

  • Page 79: Device Control Register

    9.6 Device Control Register D e v i c e C o n t r o l R e g i s t e r S R S T I E N Figure 52. Device Control Register Bit Definitions SRST (RST) Software Reset.

  • Page 80: Error Register

    D e v i c e / H e a d R e g i s t e r D R V H S 3 H S 2 H S 1 H S 0 Figure 54. Device/Head Register This register contains the device and head numbers. Bit Definitions Binary encoded address mode select.

  • Page 81: Features Register

    TK0NF (T0N) Track 0 Not Found. T 0 N = 1 indicates track 0 was not found during a Recalibrate command. AMNF (AMN) Address Mark Not Found. A M N = 1 indicates the data address mark has not been found after finding the correct ID field for the requested sector.
  • Page 82 Bit Definitions Busy. B S Y = 1 whenever the device is accessing the registers. The host should not read or write any registers when B S Y = 1 . If the host reads any register when B S Y = 1 , the contents of the Status Register will be returned. DRDY (RDY) Device Ready.

  • Page 83: General Operation Descriptions

    SRST bit in the Device Control Register is set, then is reset. The device resets the interface circuitry according to the Set Features requirement. The actions of each reset is shown in Figure 57 on page 74. Copyright IBM Corp. 1999...
  • Page 84 P O R h a r d s o f t r e s e t r e s e t A b o r t i n g H o s t i n t e r f a c e A b o r t i n g D e v i c e o p e r a t i o n ( * 1 ) ( * 1 )

  • Page 85: Register Initialization

    10.1.1 Register Initialization R e g i s t e r D e f a u l t V a l u e E r r o r D i a g n o s t i c C o d e S e c t o r C o u n t 0 1 h S e c t o r N u m b e r...

  • Page 86: Diagnostic And Reset Considerations

    10.2 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset, Hard Reset DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands.

  • Page 87: Sector Addressing Mode

    10.4 Sector Addressing Mode All addressing of data sectors recorded on the device's media is by a logical sector address. The logical CHS address for DARA-2xxxxx is different from the actual physical CHS location of the data sector on the disk media.

  • Page 88: Power Management Feature

    10.5 Power Management Feature The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.

  • Page 89: Standby Timer

    5. Activate the spindle break to stop the spindle motor 6. Wait until spindle motor is stopped 7. Perform post process 10.5.4 Standby timer The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity.

  • Page 90: Advanced Power Management (Able-3) Feature

    10.6 Advanced Power Management (ABLE-3) Feature This feature provides power saving without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host. This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle mode. This feature allows the host to select an advanced power management level.
  • Page 91 transition time with the condition that the calculated response delay is shorter than the value calculated from the specifid level by Set Feature Enable Adaptive Power Management command. The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is not possible to achieve the same level of Power savings with a fixed entry time into Active Idle because every users data and access pattern is different.

  • Page 92: Function

    10.7 S.M.A.R.T. Function The intent of Self-monitoring, analysis and reporting technology (S.M.A.R.T) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault con- dition.

  • Page 93: Operation With Power Management Modes

    10.7.6 S.M.A.R.T. operation with power management modes It is recommended that, when a host system utilizes both the power management and S.M.A.R.T. features, the system enable the device's attribute autosave feature to allow the device's automatic attribute saving upon receipt of STANDBY IMMEDIATE or SLEEP commands. If the device has been set to utilize the standby timer, the devce also saves attributes values prior to going from an Idle state to Standby state.

  • Page 94: Security Mode Feature Set

    10.8 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to hard disk device even if the device is removed from the computer. New commands are supported for this feature as below. Security Set Password ('F1'h) Security Unlock...

  • Page 95: Master Password Revision Code

    The system manufacturer/dealer who intends to enable the device lock function for the end users, must set the master password even if only single level password protection is required. 10.8.4 Master Password Revision Code This Master Password Revision Code is set by Security Set Password command with the master password. And this revision code field is returned in the Identify Device command word 92.
  • Page 96 10.8.5.3 Operation from POR after User Password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. P O R > D e v i c e L o c k e d m o d e <...

  • Page 97: User Password Lost

    10.8.5.4 User Password Lost If the User Password is forgotten and High level security is set, the system user can't access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.

  • Page 98: Command Table

    10.8.6 Command Table This table shows the device's response to commands when the Security Mode Feature Set (Device lock func- tion) is enabled. D e v i c e D e v i c e D e v i c e C o m m a n d L o c k e d U n l o c k F r o z e n M o d e...
  • Page 99 D e v i c e D e v i c e D e v i c e C o m m a n d L o c k e d U n l o c k F r o z e n M o d e M o d e M o d e...

  • Page 100: Protected Area Function

    10.9 Protected Area Function Protected Area Function is to provide the 'protected area' which can not be accessed via conventional method. This 'protected area' is used to contain critical system data such as BIOS or system management information. The contents of entire system main memory may also be dumped into 'protected area' to resume after system power off.
  • Page 101 3. Conventional usage without system software support Since the H D D works as 528MB device, there is no special care to use this device for normal use. 4. Advanced usage using protected area The data in the protected area is accessed by following. Issue Read Native Max ADDRESS command to get the real device max LBA/CYL.

  • Page 102: Address Offset Feature (Vendor Specific)

    10.10 Address Offset Feature (Vendor Specific) Computer systems perform initial code loading (booting) by reading from a predefined address on a disk drive. To allow an alternate bootable operating system to exist in a reserved area on a disk drive this feature provides a Set Features function to temporarily offset the drive address space.

  • Page 103: Identify Device Data

    B e f o r e E n a b l e A d d r e s s O f f s e t M o d e A r e s e r v e d a r e a h a s b e e n c r e a t e d u s i n g a n o n v o l a t i l e S e t M a x c o m m a n d . U s e r A c c e s s i b l e A r e a R e s e r v e d A r e a L B A 0...

  • Page 104: Write Cache Function

    10.11 Write Cache Function Write cache is a performance enhancement whereby the device reports completion of the write command (Write Sectors and Write Multiple) to the host as soon as the device has received all of the data into its buffer.

  • Page 105: Delayed Write Function (Vendor Specific)

    10.12 Delayed Write Function (Vendor Specific) Delayed Write function is a power saving enhancement whereby the device delays the actual data writing into the media. When the device is in the power saving mode and the Write command (Write Sectors, Write Multiple, or Write DMA) comes from the host, the transferred data is not written into the media imme- diately, only stored into the cache buffer.

  • Page 106: Reassign Function

    10.13 Reassign Function The reassign Function is used with read commands and write commands. The sectors of data for reassign- ment are prepared as the spare data sector. The number of the spare sector's entry is 868 entries. The one entry can register 256 consecutive sectors maximally.

  • Page 107: Command Protocol

    In response to the interrupt, the host reads the Status Register. d. The device clears the interrupt in response to the Status Register being read. e. The host reads one sector (or block) of data via the Data Register. Copyright IBM Corp. 1999...

  • Page 108: Data Out Commands

    f. The device sets D R Q = 0 after the sector (or block)has been transferred to the host. 4. For the Read Long command: a. The device sets B S Y = 1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets B S Y = 0 , sets D R Q = 1 , and interrupts the host.
  • Page 109 Write Sectors Write Verify Execution includes the transfer of one or more 512 byte ( > 5 1 2 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers.

  • Page 110: Non-Data Commands

    11.3 Non-Data Commands These commands are: Check Power Mode Enable/Disable Delayed Write Execute Device Diagnostic Flush Cache Format Unit Idle Idle Immediate Initialize Device Parameters Read Native Max ADDRESS Read Verify Sectors Recalibrate Security Erase Prepare Security Freeze Lock Seek Set Features Set Max ADDRESS Set Multiple Mode...

  • Page 111: Dma Data Transfer Commands

    11.4 DMA Data Transfer Commands These commands are: Identify Device D M A Read D M A Write D M A Data transfer using D M A commands differ in two ways from PIO transfers: data transfers are performed using the slave-DMA channel no intermediate sector interrupts are issued on multi-sector commands Initiation of the D M A transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command.
  • Page 112 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 113: Command Descriptions

    S e t M a x A D D R E S S 1 1 1 1 1 0 0 1 S e t M u l t i p l e M o d e 1 1 0 0 0 1 1 0 Figure 68. Command Set Copyright IBM Corp. 1999...
  • Page 114 P r o t o C o m m a n d C o d e B i n a r y C o d e c o l ( H e x ) B i t 7 6 5 4 3 2 1 0 S l e e p 1 1 1 0 0 1 1 0 S l e e p *...
  • Page 115 C o m m a n d F e a t u r e C o m m a n d ( S u b c o m m a n d ) C o d e R e g i s t e r ( H e x ) ( H e x ) ( D e l a y e d W r i t e F u n c t i o n )
  • Page 116 The following symbols are used in the command descriptions: Output Registers Indicates that the bit must be set to 0. Indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified.

  • Page 117: Check Power Mode (E5H/98H)

    12.1 Check Power Mode (E5h/98h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 118: Enable/Disable Delayed Write (Fah: Vendor Specific)

    12.2 Enable/Disable Delayed Write (FAh: Vendor Specific) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 119: Execute Device Diagnostic (90H)

    12.3 Execute Device Diagnostic (90h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 120: Flush Cache (E7H)

    12.4 Flush Cache (E7h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 121: Format Track (50H: Vendor Specific)

    12.5 Format Track (50h: Vendor Specific) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 122 Input Parameters From The Device Sector Number In LBA mode, this register specifies current LBA address bits 0-7. ( L = 1 ) Cylinder High/Low In LBA mode, this register specifies current LBA address bits 8 - 15 (Low), 16 - 23 (High) In LBA mode, this register specifies current LBA address bits 24 - 27.

  • Page 123: Format Unit (F7H: Vendor Specific)

    12.6 Format Unit (F7h: Vendor Specific) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 124 The execution time of this command is shown below. DARA-225000 about 44 min DARA-218000 about 38 min DARA-215000 about 30 min DARA-212000 about 26 min DARA-209000 about 20 min DARA-206000 about 14 min O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 125: Identify Device (Ech)

    12.7 Identify Device (ECh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 126 W o r d C o n t e n t D e s c r i p t i o n 0 4 5 A H D r i v e c l a s s i f i c a t i o n , b i t a s s i g n m e n t s : 1 5 ( = 0 ) : 1 = A T A P I d e v i c e , 0 = A T A d e v i c e 1 4 ( = 0 ) : 1 = f o r m a t s p e e d t o l e r a n c e g a p r e q u i r e d 1 3 ( = 0 ) : 1 = t r a c k o f f s e t o p t i o n a v a i l a b l e...
  • Page 127 W o r d C o n t e n t D e s c r i p t i o n 0 0 0 0 H C a p a b i l i t i e s 1 5 ( = 0 ) 0 = t h e c o n t e n t s o f w o r d 5 0 a r e v a l i d 1 4 ( = 1 ) 1 = t h e c o n t e n t s o f w o r d 5 0 a r e v a l i d 1 ( = 0 ) R e s e r v e d 0 ( = 0 ) 1 = t h e d e v i c e h a s a m i n i m u m S t a n d b y t i m e r...
  • Page 128 W o r d C o n t e n t D e s c r i p t i o n 6 9 7 9 0 0 0 0 H R e s e r v e d 0 0 1 E H M a j o r v e r s i o n n u m b e r 0 ( = 1 E ) A T A 1 , A T A 2 , A T A 3 a n d A T A / A T A P I 4 0 0 1 7 H...
  • Page 129 W o r d C o n t e n t D e s c r i p t i o n F 4 X X H C o m m a n d s e t / f e a t u r e e n a b l e d 1 5 ( = 1 ) R e s e r v e d 1 4 ( = 1 ) 1 = N O P c o m m a n d s u p p o r t e d 1 3 ( = 1 ) 1 = R E A D B U F F E R c o m m a n d s u p p o r t e d...
  • Page 130 W o r d C o n t e n t D e s c r i p t i o n 4 0 X X H C u r r e n t A d v a n c e d P o w e r M a n a g e m e n t l e v e l 8 ( = 4 0 h ) R e s e r v e d 0 ( = X ) C u r r e c t A d v a n c e d P o w e r M a n a g e m e n t l e v e l s e t...
  • Page 131 M i c r o c o d e r e v i s i o n S H x O A x x x D A R A 2 2 5 0 0 0 N u m b e r o f c y l i n d e r s 3 F F F h N u m b e r o f h e a d s 0 0 1 0 h...

  • Page 132: Identify Device Dma (Eeh)

    12.8 Identify Device DMA (EEh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 133: Idle (E3H/97H)

    12.9 Idle (E3h/97h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 134: Idle Immediate (E1H/95H)

    12.10 Idle Immediate (E1h/95h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 135: Initialize Device Parameters (91H)

    12.11 Initialize Device Parameters (91h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 136: Read Buffer (E4H)

    12.12 Read Buffer (E4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 137: Read Dma (C8H/C9H)

    12.13 Read DMA (C8h/C9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 138 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register specifies LBA bits 24-27 to be transferred. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 139: Read Long (22H/23H)

    12.14 Read Long (22h/23h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 140 The head number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24-27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. Input Parameters From The Device Sector Count The number of requested sectors not transferred.

  • Page 141: Read Multiple (C4H)

    12.15 Read Multiple (C4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 142 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 143: Read Native Max Address (F8H)

    12.16 Read Native Max ADDRESS (F8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 144 Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the device. Indicates that the bit is not used. O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 145: Read Sectors (20H/21H)

    12.17 Read Sectors (20h/21h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 146 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 147: Read Verify Sectors (40H/41H)

    12.18 Read Verify Sectors (40h/41h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 148 Input Parameters From The Device Sector Count The number of requested sectors not verified. This will be zero, unless an unrecover- able error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 149: Recalibrate (1Xh)

    12.19 Recalibrate (1xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 150: Security Disable Password (F6H)

    12.20 Security Disable Password (F6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 151: Security Erase Prepare (F3H)

    12.21 Security Erase Prepare (F3h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 152: Security Erase Unit (F4H)

    12.22 Security Erase Unit (F4h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 153 Identifier Zero indicates that the device should check the supplied password against the user password stored internally. One indicates that the device should check the given pass- word against the master password stored internally. The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).

  • Page 154: Security Freeze Lock (F5H)

    12.23 Security Freeze Lock (F5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 155: Security Set Password (F1H)

    12.24 Security Set Password (F1h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 156 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 7...

  • Page 157: Security Unlock (F2H)

    12.25 Security Unlock (F2h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 158 W o r d D e s c r i p t i o n C o n t r o l w o r d b i t 0 : I d e n t i f i e r ( 1 M a s t e r , 0 U s e r ) b i t 1 1 5...

  • Page 159: Seek (7Xh)

    12.26 Seek (7xh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 160: Set Features (Efh)

    12.27 Set Features (EFh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 161 AAH Enable read look-ahead feature BBH 4 bytes of ECC apply on Read Long/Write Long commands CCH Enable reverting to power on defaults Warning 1. Hard reset or power off must not be done in 5 seconds after write command completion when write cache is enabled. Note 1.

  • Page 162: Set Max Address (F9H)

    12.28 Set Max ADDRESS (F9h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 163 Sector Number In LBA mode, this register contains LBA bits 0 - 7 which is to be input.(L=1) In CHS mode, this register is ignored. ( L = 0 ) Cylinder High/Low In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High) which is to be set.

  • Page 164: Set Multiple (C6H)

    12.29 Set Multiple (C6h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 165: Sleep (E6H/99H)

    12.30 Sleep (E6h/99h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 166: Function Set (B0H)

    12.31 S.M.A.R.T. Function Set (B0h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 167 SMART Enable Operations SMART Disable Operations SMART Return Status SMART Enable/Disable Automatic Off-Line 12.31.1.1 SMART Read Attribute Values (Subcommand D0h) This subcommand returns the device's Attribute Values to the host. Upon receipt of the SMART Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated Attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register.
  • Page 168 12.31.1.4 SMART Save Attribute Values (Subcommand D3h) This subcommand causes the device to immediately save any updated Attribute Values to the device's Attri- bute Data sector regardless of the state of the Attribute Autosave feature. Upon receipt of the SMART Save Attribute Values subcommand from the host, the device asserts BSY, writes any updated Attribute Values to the Attribute Data sector, clears BSY and asserts INTRQ.
  • Page 169 12.31.1.7 SMART Write Log Sector (Subcommand D6h) This command writes 512 bytes data to the specified log sector. The 512 bytes data are transfered at a command and the Sector Count value shall be set to one. The Sector Number shall be set to specify the log sector address (Figure 113). If Read Only log sector is specified, the device returns ABRT error.

  • Page 170: Device Attributes Data Structure

    If the device detects a Threshold Exceeded Condition for prefailure attributes, the device loads F4h into the Cylinder Low register, 2Ch into the Cylinder High register, clears BSY, and asserts INTRQ. Advisory attri- butes never result in negative reliability condition. 12.31.1.11 SMART Enable/Disable Automatic Off-Line (Subcommand DBh) This subcommand enables and disables the optional feature that cause the device to perform the set of off- line data collection activities that automatically collect attribute data in an off-line mode and then save this...
  • Page 171 D e s c r i p t i o n B y t e s O f f s e t F o r m a t V a l u e D a t a S t r u c t u r e R e v i s i o n N u m b e r 0 0 h b i n a r y 0 0 1 0 h...

  • Page 172: Individual Attribute Data Structure

    12.31.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attri- bute Data Structure. D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h...
  • Page 173 Throughput Performance (*) Spin Up Time Start/Stop Count Reallocated Sector Count Seek Error Rate Seek Time Performance (*) Power-On Hours Count Spin Retry Count Device Power Cycle Count Reallocation Event Count Current Pending Sector Count Off-Line Scan Uncorrectable Sector Count Ultra D M A C R C Error Count Command Descriptions...
  • Page 174 12.31.2.2.2 Status Flag Definitions B i t F l a g N a m e D e f i n i t i o n P r e F a i l u r e / I f b i t = 0 , a n A t t r i b u t e V a l u e l e s s t h a n o r A d v i s o r y b i t e q u a l t o i t s c o r r e s p o n d i n g A t t r i b u t e T h r e s h o l d i n d i c a t e s a n A d v i s o r y c o n d i t i o n...
  • Page 175 All segments completed without errors. In this case, current segment pointer equals to total seg- ments required. Off-line data collection suspended by interrupting command Off-line data collecting aborted by interrupting command Off-line data collection aborted with fatal error 12.31.2.4 Self-test execution status Definition Percent Self-test remaining An approximation of the percent of the self-test routine remaining until completion in ten...

  • Page 176: Device Attribute Thresholds Data Structure

    Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit Self-test routine is not implemented Self-test routine is implemented Reserved (0) 12.31.2.8 SMART Capability This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h indi- cating that the device will save its Attribute Values prior to going into a power saving mode and supports the SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE command.
  • Page 177 D e s c r i p t i o n B y t e s O f f s e t F o r m a t V a l u e D a t a S t r u c t u r e R e v i s i o n N u m b e r 0 0 h b i n a r y 0 0 1 0 h...
  • Page 178 D e s c r i p t i o n B y t e s O f f s e t F o r m a t A t t r i b u t e I D N u m b e r ( 0 1 h t o F F h ) 0 0 h b i n a r y A t t r i b u t e T h r e s h o l d ( f o r c o m p a r i s o n w i t h...

  • Page 179: Smart Error Log Sector

    12.31.4 SMART error log sector The following defines the 512 bytes that make up the SMART error log sector. All multi-byte fields shown in these data structures follow the ATA/ATAPI-4 specifications for byte ordering. D e s c r i p t i o n B y t e s O f f s e t S M A R T e r r o r l o g v e r s i o n 0 0 h...
  • Page 180 D e s c r i p t i o n B y t e s O f f s e t 1 s t c o m m a n d d a t a s t r u c t u r e 0 0 h 2 n d c o m m a n d d a t a s t r u c t u r e 0 C h...
  • Page 181 D e s c r i p t i o n B y t e s O f f s e t R e s e r v e d 0 0 h E r r o r r e g i s t e r 0 1 h S e c t o r c o u n t r e g i s t e r 0 2 h...

  • Page 182: Self-Test Log Data Structure

    12.31.5 Self-test log data structure The following defines the 512 bytes that make up the Self-test log sector. All multi-byte fields shown in these data structures follow the ATA/ATAPI-4 specifications for byte ordering. D e s c r i p t i o n B y t e s O f f s e t D a t a s t r u c t u r e r e v i s i o n...

  • Page 183: Error Reporting

    12.31.6 Error Reporting The following table shows the values returned in the Status and Error Registers when specific error condi- tions are encountered by a device. E r r o r C o n d i t i o n S t a t u s E r r o r R e g i s t e r R e g i s t e r...

  • Page 184: Standby (E2H/96H)

    12.32 Standby (E2h/96h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 185: Standby Immediate (E0H/94H)

    12.33 Standby Immediate (E0h/94h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 186: Write Buffer (E8H)

    12.34 Write Buffer (E8h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...

  • Page 187: Write Dma (Cah/Cbh)

    12.35 Write DMA (CAh/CBh) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 188 The head number of the first sector to be transferred. ( L = 0 ) In LBA mode, this register contains LBA bits 24 - 27. ( L = 1 ) The retry bit. If set to one, then retries are disabled. When write cache is enabled, They are ignored.

  • Page 189: Write Long (32H/33H)

    12.36 Write Long (32h/33h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 190 Input Parameters From The Device Sector Count The number of requested sectors not transferred. Sector Number The sector number of the sector to be transferred. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the sector to be transferred.

  • Page 191: Write Multiple (C5H)

    12.37 Write Multiple (C5h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 192 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 193: Write Sectors (30H/31H)

    12.38 Write Sectors (30h/31h) C o m m a n d B l o c k O u t p u t R e g i s t e r s C o m m a n d B l o c k I n p u t R e g i s t e r s R e g i s t e r 7 6 5 4 3 2 1 0 R e g i s t e r...
  • Page 194 Input Parameters From The Device Sector Count The number of requested sectors not transferred. This will be zero, unless an unre- coverable error occurs. Sector Number The sector number of the last transferred sector. ( L = 0 ) In LBA mode, this register contains current LBA bits 0 - 7. ( L = 1 ) Cylinder High/Low The cylinder number of the last transferred sector.

  • Page 195: Write Verify (3Ch: Vendor Specific)

    12.39 Write Verify (3Ch: Vendor Specific) In DARA-2xxxxx implementation, Write Verify command is exactry same as Write Sectors command(30h). No read verification is performed after write operation. Refer to Write Sectors Command for parameters. Command Descriptions...
  • Page 196 O E M Specifications of DARA-2xxxxx 2.5 inch H D D Rev 2.1...

  • Page 197: Timeout Values

    3 0 s e c C o m m a n d C o m p l e t e B S Y = 1 ( N o t e . 2 ) Figure 132. Timeout Values Copyright IBM Corp. 1999...
  • Page 198 F U N C T I O N I N T E R V A L S T A R T S T O P T I M E O U T D M A D a t a D e v i c e B u s y a f t e r O u t t o C o m m a n d S t a t u s R e g i s t e r 4 0 0 n s...

  • Page 199: Appendix

    N o t t o b e u s e d A 2 h S E R V I C E N o t t o b e u s e d Figure 134. Command coverage Copyright IBM Corp. 1999...
  • Page 200 C o m m a n d C o m m a n d I m p l e m e n t a t i o n A T A 4 C a t e g o l y C o d e N a m e f o r D A R A 2 X X X X...
  • Page 201 N o t e : ( 1 ) T h e s e c o m m a n d s h a v e t w o c o m m a n d c o d e s a n d a p p e a r i n t h i s t a b l e t w i c e , o n c e f o r e a c h c o m m a n d c o d e .

  • Page 202: Set Features Command Support Coverage

    14.2 SET FEATURES Command Support Coverage The following table is provided to facilitate the understanding of DARA-2xxxxx. "Set Features" command support coverage comparing to the ATA-4 defined command set. The column of 'Implementation' shows the capability of DARA-2xxxxx for those commands. For detail operation, refer to 12.27, “Set Features (EFh)”...
  • Page 203 Recalibrate (1xh) Format Track 98, 111 S.M.A.R.T. Function Set (B0h) Format Unit 100, 113 Security Disable Password (F6h) Security Erase Prepare (F3h) Security Erase Unit (F4h) Security Freeze Lock (F5h) Security Set Password (F1h) Security Unlock (F2h) Copyright IBM Corp. 1999...
  • Page 204 Register (continued) Command Register Cylinder High Register Cylinder Low Register Data Register Device Control Register Device/Head Register Drive Address Register Error Register Features Register ICRCE Register Initialization Identify Device 97, 115 Sector Count Register Identify Device D M A 101, 122 Sector Number Register Idle 100, 123...
  • Page 205 Standby 100, 174 Standby Immediate 100, 175 Timeout Interval 69, 187 Timeout Parameter 123, 174 TK0NF Write Buffer 98, 176 Write Cache Write D M A 101, 177 Write Long 98, 179 Write Multiple 98, 181 Write Sectors 98, 183 Write Verify 99, 185 W T G...
  • Page 206 S25L-1638-03 Published in Japan...

This manual is also suitable for:

Dara-209000Dara-212000Dara-215000Dara-218000Dara-225000

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