6-11. BLOCK DIAGRAM – HDMI RECEIVER SECTION –
CN3201
HDMI ASSIGNABLE
IN 1
DATA2+
1
DATA2–
3
DATA1+
4
DATA1–
6
DATA0+
7
DATA0–
9
CLOCK+
10
CLOCK–
12
SCL (5V)
15
SDA (5V)
16
HOT PLUG DET
19
CN3202
HDMI ASSIGNABLE
IN 2
DATA2+
1
DATA2–
3
DATA1+
4
DATA1–
6
DATA0+
7
DATA0–
9
CLOCK+
10
CLOCK–
12
SCL (5V)
15
SDA (5V)
16
HOT PLUG DET
19
EEPROM
DATA SELECTOR
IC3202
IC3203
SDA 5
3
2C
2Y3
SCL 6
13
1C
2Y2 2
WP 7
2Y1 5
2Y0 1
1Y3 11
1Y2 15
1Y1 14
1Y0
INH
A
B
6
10
9
Q3203
LEVEL
SHIFT
Q3207
IC3204, 3206, 3207
+5V
43
34
HDMI TX
38
MAINCPU_TX
39
HDMI RX
39
MAINCPU_RX
HDMI RESET
14
RESET
(Page 62)
STR-DA7100ES
HDMI PANELLINK CINEMA RECIVER
71
R1X2+
70
R1X2–
67
R1X1+
66
R1X1–
63
R1X0+
62
R1X0–
59
R1XC+
58
R1XC–
LEVEL
30
DSCL1
SHIFT
29
DSDA1
Q3205
HOT PLUG
DETECT
Q3201, 3210
52
R0X2+
51
R0X2–
48
R0X1+
47
R0X1–
44
R0X0+
43
R0X0–
40
R0XC+
39
R0XC–
LEVEL
32
DSCL0
SHIFT
31
DSDA0
Q3204
HOT PLUG
DETECT
Q3202, 3209
28 27
96
4
28.322MHz
12
LEVEL
SHIFT
Q3206
35
36
IC3205
119 – 116,
Q16 – Q23
D16 – D23
113 – 110
(Page 70)
132 – 129,
41
Q8 – Q15
D8 – D15
126 – 123
(Page 72)
144 – 140,
Q0 – Q7
D0 – D7
137 136, 133
I/H BUS
SD0
SD0 84
SD1
SD1 83
SD2
SD2 82
SD3
SD3 81
SPDIF
SPDIF 78
MCKO
MCKOUT 88
MCKIN 87
BCKO
SCK 86
LRCKO
WS 85
MUTEOUT 77
DE
DE 1
DCK
ODCK 121
HSYNC
HSYNC 2
VSYNC
VSYNC 3
97
104
102
X3201
32
33
HDMI CONTROLLER
IC3209 (1/2)
71
71
DIGITAL CHROMA DECODER
IC3402
CVBS IN
167
CVBSIN
DOUT2
44
CB IN
161
BIN
DOUT3
CR IN
156
CIN
DOUT4
DOUT5
SD-RAM
DOUT6
IC3403
DOUT7
LDQM 15
115
DQM
UDQM 39
DOUT8
CLK 38
120
SDCK
CKE 37
123
CKE
DOUT9
/RAS 18
122
XRAS
/CAS 17
117
XCAS
/WE 16
116
XWE
/CS 19
124
XCS
37
27MHz
(Page 63)
DQ0
DQ0
DQ15
DQ15
A0
ADDR0
A11
ADDR11
BA0 20
126
BA0
BA1 21
128
BA1
11
12
173
14
16 25
X3401
27MHz
73
72
STR-DA7100ES
V2
72
V3
73
V4
74
V5
76
V6
77
V7
78
V8
79
V9
80
27MHz
66
HDMI BUS
40
(Page 72)
• SIGNAL PATH
: AUDIO (DIGITAL)
: VIDEO