3-2. OVERALL BLOCK DIAGRAM (2/2)
HD-035 BOARD (2/2)
CN101
PLUS
DC IN
1
F101
CN102
BATT (+)
BATT IN
1
F102
Q106, Q107
BATT
DATA
DCIN_AD
BATT_AD
IB_ENABLE
SLEEP
SLEEP
A
HD-035
BOARD (1/2)
(PAGE 3-1)
IC115
(1/5)
SW_OFF
1
PWR_SUB_33
2
7
2
4
IC116(2/2)
(1/5)
PWR_MAIN_33
PWR_HDD
PWR_P33
PWR_LCD
POR-
MRESET
08
HVR-DR60
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
Q115, Q118
Q108, Q109
DC POWER
SELECT
SPWR
23
IC101
DC_DC
CONV.
(1/5)
13
Q103
28
IC116(1/2)
6
(1/5)
5
Q102
3
TG2
14
L101
SWTCHING
Q105
BG2
18
SENSE2+
12
SENSE2-
11
VOSENSE2
9
TG1
26
L102
SWTCHING
Q114
BG1
22
SENSE1+
30
SENSE1-
31
VOSENSE1
1
3-2
Q111
PWR_MAIN_33
2
4
Q110
PWR_HDD
IC106
5
4
LCD POWER REG
(1/5)
1
PWR_LCD
Q101
Q116
2
IC114
Q104
3.3V
5
3
REG.
6
(1/5)
PWR_P33
IC105
2
RESET
1
GEN
4
(1/5)
MAIN
M3.3V
IC110
RESET
1
GEN
(1/5)
HDD
H3.3V
LCD
3.0V
1.8V
A1.8V
S3.3V
Q117
P3.3V