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NEC 78KF1 Manuals
Manuals and User Guides for NEC 78KF1. We have
1
NEC 78KF1 manual available for free PDF download: User Manual
NEC 78KF1 User Manual (626 pages)
8-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 4.95 MB
Table of Contents
Table of Contents
12
Chapter 1 Outline
33
Features
33
Applications
34
Ordering Information
35
Pin Configuration (Top View)
38
K1 Family Lineup
40
78K0/Kx1 Product Lineup
40
V850Es/Kx1 Product Lineup
42
Block Diagram
44
Outline of Functions
45
Chapter 2 Pin Functions
47
Pin Function List
47
Description of Pin Functions
51
P00 to P06 (Port 0)
51
P10 to P17 (Port 1)
52
P20 to P27 (Port 2)
52
P30 to P33 (Port 3)
53
P40 to P47 (Port 4)
53
P50 to P57 (Port 5)
53
P60 to P67 (Port 6)
54
P70 to P77 (Port 7)
54
P120 (Port 12)
54
P130 (Port 13)
54
P140 to P145 (Port 14)
55
Av Ref
55
Av Ss
55
Reset
56
Regc
56
X1 and X2
56
XT1 and XT2
56
VDD and EV DD
56
VSS and EV SS
56
VPP (Flash Memory Versions Only)
56
IC (Mask ROM Versions Only)
56
Pin I/O Circuits and Recommended Connection of Unused Pins
57
Chapter 3 Cpu Architecture
61
Memory Space
61
Internal Program Memory Space
67
Internal Data Memory Space
68
Special Function Register (SFR) Area
68
Data Memory Addressing
69
Processor Registers
74
Control Registers
74
General-Purpose Registers
78
Special Function Registers (Sfrs)
79
Instruction Address Addressing
84
Relative Addressing
84
Immediate Addressing
85
Register Addressing
86
Operand Address Addressing
87
Implied Addressing
87
Register Addressing
88
Direct Addressing
89
Short Direct Addressing
90
Special Function Register (SFR) Addressing
91
Register Indirect Addressing
92
Based Addressing
93
Based Indexed Addressing
94
Stack Addressing
95
Chapter 4 Port Functions
96
Port Functions
96
Port Configuration
98
Port 0
99
Port 1
103
Port 2
108
Port 3
109
Port 4
111
Port 5
112
Port 6
113
Port 7
116
Port 12
117
Port 13
118
Port 14
119
Block Diagram of P142
120
Block Diagram of P143
121
Block Diagram of P144 and P145
122
Registers Controlling Port Function
123
Format of Port Mode Register
123
Format of Port Register
126
Format of Pull-Up Resistor Option Register
127
Port Function Operations
128
Writing to I/O Port
128
Reading from I/O Port
128
Operations on I/O Port
128
Chapter 5 External Bus Interface
129
External Bus Interface
129
Memory Map When Using External Bus Interface
130
Registers Controlling External Bus Interface
132
Format of Memory Expansion Mode Register (MEM)
132
Pins Specified for Address (with Μ PD780143)
133
Format of Memory Expansion Wait Setting Register (MM)
134
External Bus Interface Function Timing
135
Instruction Fetch from External Memory
136
External Memory Read Timing
137
External Memory Write Timing
138
External Memory Read Modify Write Timing
139
Example of Connection with Memory
140
Connection Example of Μ PD780144 and Memory
140
Chapter 6 Clock Generator
141
Functions of Clock Generator
141
Configuration of Clock Generator
141
Block Diagram of Clock Generator
142
Registers Controlling Clock Generator
143
Format of Processor Clock Control Register (PCC)
144
Format of Ring-OSC Mode Register (RCM)
145
Format of Main Clock Mode Register (MCM)
146
Format of Main OSC Control Register (MOC)
147
Format of Oscillation Stabilization Time Counter Status Register (OSTC)
148
Format of Oscillation Stabilization Time Select Register (OSTS)
149
System Clock Oscillator
150
X1 Oscillator
150
Subsystem Clock Oscillator
150
Examples of External Circuit of X1 Oscillator
150
Examples of External Circuit of Subsystem Clock Oscillator
150
Examples of Incorrect Resonator Connection
151
When Subsystem Clock Is Not Used
153
Ring-OSC Oscillator
153
Prescaler
153
Subsystem Clock Feedback Resistor
153
Clock Generator Operation
154
Timing Diagram of CPU Default Start Using Ring-OSC
155
Status Transition Diagram
156
Time Required to Switch between Ring-OSC Clock and X1 Input Clock
161
Time Required for CPU Clock Switchover
162
Clock Switching Flowchart and Register Setting
163
Switching from Ring-OSC Clock to X1 Input Clock
163
Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
163
Switching from X1 Input Clock to Ring-OSC Clock
164
Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
164
Switching from X1 Input Clock to Subsystem Clock
165
Switching from X1 Input Clock to Subsystem Clock (Flowchart)
165
Switching from Subsystem Clock to X1 Input Clock
166
Switching from Subsystem Clock to X1 Input Clock (Flowchart)
166
Register Settings
167
Chapter 7 16-Bit Timer/Event Counters 00 and 01
168
Functions of 16-Bit Timer/Event Counters 00 and 01
168
Configuration of 16-Bit Timer/Event Counters 00 and 01
169
Block Diagram of 16-Bit Timer/Event Counter 00
169
PD780146, 780148, and 78F0148 Only)
170
Format of 16-Bit Timer Counter 0N (Tm0N)
171
Format of 16-Bit Timer Capture/Compare Register 00N (Cr00N)
171
Format of 16-Bit Timer Capture/Compare Register 01N (Cr01N)
173
Registers Controlling 16-Bit Timer/Event Counters 00 and 01
174
Format of 16-Bit Timer Mode Control Register 00 (TMC00)
175
Format of 16-Bit Timer Mode Control Register 01 (TMC01)
176
Format of Capture/Compare Control Register 00 (CRC00)
177
Format of Capture/Compare Control Register 01 (CRC01)
178
Format of 16-Bit Timer Output Control Register 00 (TOC00)
179
Format of 16-Bit Timer Output Control Register 01 (TOC01)
180
Format of Prescaler Mode Register 00 (PRM00)
182
Format of Prescaler Mode Register 01 (PRM01)
183
Format of Port Mode Register 0 (PM0)
184
Operation of 16-Bit Timer/Event Counters 00 and 01
185
Interval Timer Operation
185
Control Register Settings for Interval Timer Operation
186
Interval Timer Configuration Diagram
187
Timing of Interval Timer Operation
187
PPG Output Operations
188
Control Register Settings for PPG Output Operation
189
Configuration Diagram of PPG Output
190
PPG Output Operation Timing
190
Pulse Width Measurement Operations
191
Cr01N Capture Operation with Rising Edge Specified
191
And One Capture Register (When Ti00N and Cr01N Are Used)
192
Configuration Diagram for Pulse Width Measurement with Free-Running Counter
193
And One Capture Register (with both Edges Specified)
193
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
194
(With both Edges Specified)
195
Two Capture Registers (with Rising Edge Specified)
196
And Two Capture Registers (with Rising Edge Specified)
197
(With Rising Edge Specified)
198
Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
198
External Event Counter Operation
199
Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
200
Configuration Diagram of External Event Counter
201
External Event Counter Operation Timing (with Rising Edge Specified)
201
Square-Wave Output Operation
202
Control Register Settings in Square-Wave Output Mode
202
Square-Wave Output Operation Timing
203
One-Shot Pulse Output Operation
204
Control Register Settings for One-Shot Pulse Output with Software Trigger
205
Timing of One-Shot Pulse Output Operation with Software Trigger
206
(With Rising Edge Specified)
207
Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
208
Cautions for 16-Bit Timer/Event Counters 00 and 01
209
Start Timing of 16-Bit Timer Counter 0N (Tm0N)
209
Chapter 8 8-Bit Timer/Event Counters 50 and 51
212
Functions of 8-Bit Timer/Event Counters 50 and 51
212
Configuration of 8-Bit Timer/Event Counters 50 and 51
214
Registers Controlling 8-Bit Timer/Event Counters 50 and 51
216
Operations of 8-Bit Timer/Event Counters 50 and 51
221
Operation as Interval Timer
221
Operation as External Event Counter
223
Square-Wave Output Operation
224
PWM Output Operation
225
Cautions for 8-Bit Timer/Event Counters 50 and 51
229
Chapter 9 8-Bit Timers H0 and H1
230
Functions of 8-Bit Timers H0 and H1
230
Configuration of 8-Bit Timers H0 and H1
230
Registers Controlling 8-Bit Timers H0 and H1
234
Operation of 8-Bit Timers H0 and H1
239
Operation as Interval Timer/Square-Wave Output
239
Operation as PWM Output Mode
242
Carrier Generator Mode Operation (8-Bit Timer H1 Only)
248
Chapter 10 Watch Timer
255
Functions of Watch Timer
255
Configuration of Watch Timer
257
Register Controlling Watch Timer
257
Watch Timer Operations
259
Watch Timer Operation
259
Interval Timer Operation
260
Cautions for Watch Timer
261
Chapter 11 Watchdog Timer
262
Functions of Watchdog Timer
262
Configuration of Watchdog Timer
264
Block Diagram of Watchdog Timer
264
Registers Controlling Watchdog Timer
265
Format of Watchdog Timer Mode Register (WDTM)
265
Format of Watchdog Timer Enable Register (WDTE)
266
Operation of Watchdog Timer
267
Watchdog Timer Operation When "Ring-OSC Cannot be Stopped" Is Selected by Mask Option
267
Watchdog Timer Operation When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option
268
Watchdog Timer Operation in STOP Mode (When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option)
269
Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
269
Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
269
Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock)
270
Watchdog Timer Operation in HALT Mode (When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option)
271
Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
271
Operation in HALT Mode
271
Chapter 12 Clock Output/Buzzer Output Controller
272
Functions of Clock Output/Buzzer Output Controller
272
Block Diagram of Clock Output/Buzzer Output Controller
272
Configuration of Clock Output/Buzzer Output Controller
273
Register Controlling Clock Output/Buzzer Output Controller
273
Format of Clock Output Selection Register (CKS)
274
Format of Port Mode Register 14 (PM14)
275
Clock Output/Buzzer Output Controller Operations
276
Clock Output Operation
276
Operation as Buzzer Output
276
Remote Control Output Application Example
276
Chapter 13 A/D Converter
277
Functions of A/D Converter
277
Block Diagram of A/D Converter
277
Configuration of A/D Converter
278
Registers Used in A/D Converter
280
Format of A/D Converter Mode Register (ADM)
281
Timing Chart When Boost Reference Voltage Generator Is Used
282
Format of Analog Input Channel Specification Register (ADS)
283
Format of A/D Conversion Result Register (ADCR)
284
Format of Power-Fail Comparison Mode Register (PFM)
285
Format of Power-Fail Comparison Threshold Register (PFT)
285
A/D Converter Operations
286
Basic Operations of A/D Converter
286
Basic Operation of A/D Converter
287
Input Voltage and Conversion Results
288
Relationship between Analog Input Voltage and A/D Conversion Result
288
A/D Converter Operation Mode
289
A/D Conversion Operation
289
Power-Fail Detection (When PFEN = 1 and PFCM = 0)
290
How to Read A/D Converter Characteristics Table
292
Overall Error
292
Quantization Error
292
Zero-Scale Error
293
Full-Scale Error
293
Integral Linearity Error
293
Differential Linearity Error
293
Cautions for A/D Converter
294
Circuit Configuration of Series Resistor String
294
Analog Input Pin Connection
295
Timing of A/D Conversion End Interrupt Request Generation
296
Timing of A/D Converter Sampling and A/D Conversion Start Delay
297
Internal Equivalent Circuit of Anin Pin
298
Chapter 14 Serial Interface Uart0
299
Functions of Serial Interface UART0
299
Configuration of Serial Interface UART0
300
Block Diagram of Serial Interface UART0
301
Registers Controlling Serial Interface UART0
303
Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0)
303
Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
305
Format of Baud Rate Generator Control Register 0 (BRGC0)
306
Format of Port Mode Register 1 (PM1)
307
Operation of Serial Interface UART0
308
Operation Stop Mode
308
Asynchronous Serial Interface (UART) Mode
309
Format of Normal UART Transmit/Receive Data
310
Example of Normal UART Transmit/Receive Data Waveform
310
Transmission Completion Interrupt Request Timing
312
Reception Completion Interrupt Request Timing
313
Noise Filter Circuit
314
Dedicated Baud Rate Generator
315
Configuration of Baud Rate Generator
315
Permissible Baud Rate Range During Reception
318
Chapter 15 Serial Interface Uart6
320
Functions of Serial Interface UART6
320
LIN Transmission Operation
321
LIN Reception Operation
322
Port Configuration for LIN Reception Operation
323
Configuration of Serial Interface UART6
324
Block Diagram of Serial Interface UART6
325
Registers Controlling Serial Interface UART6
327
Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)
327
Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
329
Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
330
Format of Clock Selection Register 6 (CKSR6)
331
Format of Baud Rate Generator Control Register 6 (BRGC6)
332
Format of Asynchronous Serial Interface Control Register 6 (ASICL6)
333
Format of Input Switch Control Register (ISC)
334
Format of Port Mode Register 1 (PM1)
334
Operation of Serial Interface UART6
335
Operation Stop Mode
335
Asynchronous Serial Interface (UART) Mode
336
Format of Normal UART Transmit/Receive Data
338
Example of Normal UART Transmit/Receive Data Waveform
339
Normal Transmission Completion Interrupt Request Timing
341
Example of Continuous Transmission Processing Flow
343
Timing of Starting Continuous Transmission
344
Timing of Ending Continuous Transmission
345
Reception Completion Interrupt Request Timing
346
Reception Error Interrupt
347
Noise Filter Circuit
348
Example of Setting Procedure of SBF Transmission (Flowchart)
349
SBF Transmission
349
SBF Reception
350
Dedicated Baud Rate Generator
351
Configuration of Baud Rate Generator
352
Permissible Baud Rate Range During Reception
355
Data Frame Length During Continuous Transmission
357
Chapter 16 Serial Interfaces Csi10 and Csi11
358
Functions of Serial Interfaces CSI10 and CSI11
358
Configuration of Serial Interfaces CSI10 and CSI11
359
Block Diagram of Serial Interface CSI10
359
PD780146, 780148, and 78F0148 Only)
360
Registers Controlling Serial Interfaces CSI10 and CSI11
361
Format of Serial Operation Mode Register 10 (CSIM10)
361
Format of Serial Operation Mode Register 11 (CSIM11)
362
Format of Serial Clock Selection Register 10 (CSIC10)
363
Format of Serial Clock Selection Register 11 (CSIC11)
365
Format of Port Mode Register 0 (PM0)
366
Format of Port Mode Register 1 (PM1)
366
Operation of Serial Interfaces CSI10 and CSI11
367
Operation Stop Mode
367
3-Wire Serial I/O Mode
368
Timing in 3-Wire Serial I/O Mode
372
Timing of Clock/Data Phase
374
Output Operation of First Bit
375
Output Value of So1N Pin (Last Bit)
376
Chapter 17 Serial Interface Csia0
378
Functions of Serial Interface CSIA0
378
Configuration of Serial Interface CSIA0
379
Block Diagram of Serial Interface CSIA0
380
Registers Controlling Serial Interface CSIA0
381
Format of Automatic Data Transfer Address Count Register 0 (ADTC0)
381
Format of Serial Operation Mode Specification Register 0 (CSIMA0)
382
Format of Serial Status Register 0 (CSIS0)
383
Format of Serial Trigger Register 0 (CSIT0)
385
Format of Divisor Selection Register 0 (BRGCA0)
386
Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0)
386
Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0)
388
Format of Port Mode Register 14 (PM14)
389
Operation of Serial Interface CSIA0
390
Operation Stop Mode
390
3-Wire Serial I/O Mode
391
3-Wire Serial I/O Mode Timing
393
Format of Transmit/Receive Data
394
Transfer Bit Order Switching Circuit
395
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function
396
Automatic Transmission/Reception Mode Operation Timings
399
Automatic Transmission/Reception Mode Flowchart
400
(In Automatic Transmission/Reception Mode) (1/2
401
Automatic Transmission Mode Operation Timing
403
Automatic Transmission Mode Flowchart
404
Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode)
405
Repeat Transmission Mode Operation Timing
407
Repeat Transmission Mode Flowchart
408
Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
409
Format of CSIA0 Transmit/Receive Data
411
Automatic Transmission/Reception Suspension and Restart
412
System Configuration When Busy Control Option Is Used
413
Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1)
414
Busy Signal and Wait Release (When BUSYLV0 = 1)
414
Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1)
415
Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0)
416
Automatic Transmit/Receive Interval Time
417
Chapter 18 Multiplier/Divider
418
Functions of Multiplier/Divider
418
Configuration of Multiplier/Divider
418
Register Controlling Multiplier/Divider
423
Operations of Multiplier/Divider
424
Multiplication Operation
424
Division Operation
426
Chapter 19 Interrupt Functions
428
Interrupt Function Types
428
Interrupt Sources and Configuration
428
Registers Controlling Interrupt Functions
432
Interrupt Servicing Operations
439
Maskable Interrupt Request Acknowledgement
439
Software Interrupt Request Acknowledgment
441
Multiple Interrupt Servicing
442
Interrupt Request Hold
445
Chapter 20 Key Interrupt Function
446
Functions of Key Interrupt
446
Configuration of Key Interrupt
446
Register Controlling Key Interrupt
447
Chapter 21 Standby Function
448
Standby Function and Configuration
448
Standby Function
448
Registers Controlling Standby Function
450
Standby Function Operation
452
HALT Mode
452
STOP Mode
457
Chapter 22 Reset Function
461
Register for Confirming Reset Source
468
Chapter 23 Clock Monitor
469
Functions of Clock Monitor
469
Configuration of Clock Monitor
469
Registers Controlling Clock Monitor
470
Operation of Clock Monitor
471
Chapter 24 Power-On-Clear Circuit
476
Functions of Power-On-Clear Circuit
476
Configuration of Power-On-Clear Circuit
477
Operation of Power-On-Clear Circuit
477
Block Diagram of Power-On-Clear Circuit
477
Timing of Internal Reset Signal Generation in Power-On-Clear Circuit
477
Cautions for Power-On-Clear Circuit
478
Example of Software Processing after Release of Reset
478
Chapter 25 Low-Voltage Detector
480
Functions of Low-Voltage Detector
480
Configuration of Low-Voltage Detector
480
Block Diagram of Low-Voltage Detector
480
Registers Controlling Low-Voltage Detector
481
Format of Low-Voltage Detection Register (LVIM)
482
Format of Low-Voltage Detection Level Selection Register (LVIS)
483
Operation of Low-Voltage Detector
484
Timing of Low-Voltage Detector Internal Reset Signal Generation
485
Timing of Low-Voltage Detector Interrupt Signal Generation
487
Cautions for Low-Voltage Detector
488
Example of Software Processing after Release of Reset
489
Chapter 26 Regulator
492
Outline of Regulator
492
Block Diagram of Regulator Periphery
492
REGC Pin Connection
493
Chapter 27 Mask Options
494
Chapter 28 Pd78F0148
495
Internal Memory Size Switching Register
496
Format of Internal Memory Size Switching Register (IMS)
496
Internal Expansion RAM Size Switching Register
497
Format of Internal Expansion RAM Size Switching Register (IXS)
497
Writing with Flash Programmer
498
Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode
500
Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode
501
Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode
502
Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode
503
Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode
504
Programming Environment
505
Communication Mode
505
Environment for Writing Program to Flash Memory
505
Communication with Dedicated Flash Programmer (CSI10)
505
Communication with Dedicated Flash Programmer (CSI10 + HS)
506
Communication with Dedicated Flash Programmer (UART0)
506
Communication with Dedicated Flash Programmer (UART0 + HS)
507
Communication with Dedicated Flash Programmer (UART6)
507
Processing of Pins on Board
509
VPP Pin
509
Example of Connection of V Pin
509
Serial Interface Pins
510
Signal Collision (Input Pin of Serial Interface)
510
Malfunction of Other Device
511
RESET Pin
512
Port Pins
512
REGC Pin
512
Other Signal Pins
512
Power Supply
512
Signal Collision (RESET Pin)
512
Programming Method
513
Controlling Flash Memory
513
Flash Memory Manipulation Procedure
513
Flash Memory Programming Mode
514
Selecting Communication Mode
514
Communication Commands
515
Chapter 29 Instruction Set
516
Conventions Used in Operation List
516
Operand Identifiers and Specification Methods
516
Description of Operation Column
517
Description of Flag Operation Column
517
Operation List
518
Instructions Listed by Addressing Type
526
Chapter 30 Electrical Specifications
529
(Standard Products, (A) Grade Products)
529
Chapter 31 Electrical Specifications ((A1) Grade Products)
554
Chapter 32 Electrical Specifications ((A2) Grade Products)
575
Chapter 33 Package Drawings
591
Chapter 34 Recommended Soldering Conditions
593
Chapter 35 Cautions for Wait
596
Cautions for Wait
596
Peripheral Hardware that Generates Wait
597
Example of Wait Occurrence
598
Appendix A Development Tools
599
Development Tool Configuration
600
Software Package
602
Language Processing Software
603
Control Software
604
Flash Memory Writing Tools
604
Debugging Tools (Hardware)
605
When Using In-Circuit Emulators IE-78K0-NS and IE-78K0-NS-A
605
When Using In-Circuit Emulator IE-78K0K1-ET
606
Debugging Tools (Software)
607
Embedded Software
608
Appendix B Notes on Target System Design
609
Distance between IE System and Conversion Adapter
609
Connection Conditions of Target System (When Using NP-80GC-TQ)
610
Connection Conditions of Target System (When Using NP-H80GC-TQ)
611
Connection Conditions of Target System (When Using NP-80GK)
612
Appendix C Register Index
614
Register Index (in Alphabetical Order with Respect to Register Names)
614
Register Index (in Alphabetical Order with Respect to Register Symbol)
618
Appendix D Revision History
622
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