HCD-ZX10D
QQ
3 7 63 1515 0
Pin No.
Pin Name
86
MDQM2
87
VDD25
88 to 95
MD20 to MD27
96
GND25
97
MDQM3
98
VDD25
99 to 102
MD28 to MD31
103
GND25
104
VDD25
105
VCLK
106
XCK_I/O_SEL
107
VS
108
I/P SW
109
CDSEL
110
MREQ
111
VDDP
112
GNDP
113
MDI
114
MC
115
ML
116
HIRQ2
TE
L 13942296513
117
VDAC_4B
118
VDAC_VDD4
119
VDAC_4
120
VDAC_3B
121
VDAC_VDD3
122
VDAC_3
123
VDAC_2B
124
VDAC_VDD2
125
VDAC_2
126
VDAC_1B
127
VDAC_VDD1
128
VDAC_1
129
VDAC_0B
130
VDAC_VDD0
131
VDAC_0
132
VDAC_DVSS
133
VDAC_DVDD
134
VDAC_REFVDD
135
VDAC_REF
136
VDAC_REFVSS
137
XVSS
138
XOUT
www
139
XIN
140
XVDD
141
AVSS2
.
142
AVDD2
143
AVDD1
144
AVSS1
80
http://www.xiaoyu163.com
I/O
O
Write mask signal output to the SD-RAM
–
Power supply terminal (+3.3V)
I/O
Two-way data bus with the SD-RAM
–
Ground terminal
O
Write mask signal output to the SD-RAM
–
Power supply terminal (+3.3V)
I/O
Two-way data bus with the SD-RAM
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Not used
O
Not used
O
Wide control signal output to the video amplifier
Interlace/progressive selection signal output terminal
O
"L": interlace, "H": progressive
O
Digital out signal selection signal output terminal
O
Muting request signal output to the master controller
–
Power supply terminal (+3.3V)
–
Ground terminal
O
Serial data output to the D/A converter
O
Serial data transfer clock signal output to the D/A converter
O
Serial data latch pulse signal output to the D/A converter
I
Busy signal input from the EEPROM
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Component video signal output to the video amplifier
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Component video signal output to the video amplifier
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Y signal output to the video amplifier
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Chroma signal output to the video amplifier
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Video signal output to the video amplifier
–
Ground terminal
–
Power supply terminal (+3.3V)
–
Power supply terminal (+3.3V)
I
Reference voltage input terminal
–
Ground terminal
–
Ground terminal
O
Clock signal output terminal
I
System clock signal (27 MHz) input from the clock generator
x
ao
u163
–
Power supply terminal (+3.3V)
y
–
Ground terminal
i
–
Power supply terminal (+3.3V)
–
Power supply terminal (+3.3V)
–
Ground terminal
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2 9
8
Description
Q Q
3
6 7
1 3
1 5
Not used
co
.
9 4
2 8
Not used
0 5
8
2 9
9 4
2 8
m
9 9
9 9