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µPD750008 USER'S MANUAL
Figure 4-13. Data Restored from the Stack Memory (Mk I Mode)
POP instruction
Stack
SP
Lower bits of pair register
SP + 1
Upper bits of pair register
SP + 2
Note PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.
PUSH instruction
SP – 2
Lower bits of pair register
SP – 1
Upper bits of pair register
SP
Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.
2. PSW bits other than MBE and RBE are not saved or restored.
Remark * indicates an undefined bit.
6 0
SP
SP + 1
SP + 2
SP + 3
SP + 4
Figure 4-14. Data Saved to the Stack Memory (Mk II Mode)
CALL, CALLA, or CALLF instruction
Stack
SP – 6
SP – 5
SP – 4
SP – 3
SP – 2
SP – 1
SP
RET or RETS instruction
Stack
PC11 - PC8
Note
Note
MBE
RBE
PC13
PC12
PC3 - PC0
PC7 - PC4
Stack
PC11 - PC8
Note 1
Note 1
0
0
PC13
PC12
PC3 - PC0
PC7 - PC4
MBE
RBE
*
*
Note 2
*
*
*
*
RETI instruction
Stack
SP
PC11 - PC8
Note
SP + 1
MBE
RBE
PC13
SP + 2
PC3 - PC0
SP + 3
PC7 - PC4
SP + 4
IST1
IST0
MBE
PSW
SP + 5
CY
SK2
SK1
SP + 6
Interrupt
Stack
SP – 6
PC11 - PC8
Note 1
0
0
PC13
PC12
SP – 5
SP – 4
PC3 - PC0
SP – 3
PC7 - PC4
SP – 2
IST1
IST0
MBE
RBE
PSW
CY
SK2
SK1
SK0
SP – 1
SP
Note
PC12
RBE
SK0
Note 1
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