Table of Contents
Advertisement
• Modes 1 to 5 (Expanded Modes)
P6
functions as the clock output pin (φ) or an input port. P6
7
PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1.
function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
P6
to P6
6
3
settings of bits P6
function as bus control input/output pins (BACK, BREQ, and WAIT) or
P6
to P6
2
0
input/output ports. For the method of selecting the pin functions, see table 7.11.
When P6
to P6
function as input/output ports, the pin becomes an output port if the
2
0
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
• Modes 6 and 7 (Single-Chip Mode)
P6
functions as the clock output pin (φ) or an input port. P6
7
input/output ports. P6
(initial value), and an input port if this bit is set to 1. A pin in port 6 becomes an output port if
the corresponding bit of P6
to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the
corresponding pin maintains its output state.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P6
pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
7
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
Bit
P6
Initial value
Read/Write
R
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
186
DDR to P6
DDR.
6
3
is the clock output pin (φ) if the PSTOP bit in MSTCRH is cleared to 0
7
DDR to P6
6
7
6
5
P6
P6
6
7
1
0
0
R/W
R/W
DDR is set to 1, and an input port if this pin is cleared
0
4
3
P6
P6
5
4
3
0
0
R/W
R/W
Port 6 data 7 to 0
These bits store data for port 6 pins
is the clock output pin (ø) if the
7
to P6
function as generic
6
0
2
1
P6
P6
2
1
0
0
R/W
R/W
0
P6
0
0
R/W
Advertisement
Table of Contents
