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15.9
Usage Notes
15.9.1
Operating Frequency
When the on-chip PLL circuit is used, the system clock of this LSI must be 16 MHz. This 16-MHz
system clock, used as base clock, is tripled in the on-chip PLL circuit to generate the 48-MHz USB
operating clock. When the USB operating clock (48 MHz) oscillator or 48-MHz external clock is
used, the system clock of the LSI must be 13 MHz to 16 MHz. Medium-speed mode is not
supported; use full-speed mode.
15.9.2
Bus Interface
This module's interface is based on the bus specifications of external area 6. Before accessing the
USB, area 6 must be specified as having an 8-bit bus width and 3-state access using the bus
controller register. In mode 7 (single-chip mode), the USB module cannot be accessed. In mode 6
(internal ROM enabled mode), CS6 and A7 to A0 pins are used as inputs at initialization and USB
cannot be accessed. Before access to this module, set P72DDR and PC7DDR to PC0DDR to 1 and
H'FF, respectively, to use CS6 and A7 to A0 pins as outputs.
15.9.3
Setup Data Reception
The following must be noted for the EP0s FIFO used to receive 8-byte setup data. The USB is
designed to always receive setup commands. Accordingly, write from the UDC has higher priority
than read from the LSI. If the reception of the next setup command starts while the is LSI reading
data after completing reception, this data read from the LSI is forcibly cancelled and the next setup
command write starts. After the next setup command write, data read from the LSI is thus
undefined. Read operation is forcibly disabled because data cannot be guaranteed if DP-RAM used
as FIFO accesses the same address for write and read.
15.9.4
FIFO Clear
If the USB cable is disconnected during communication, old data may be contained in the FIFO.
Accordingly, FIFO must be cleared immediately after USB cable connection. In addition, after bus
reset, all FIFO must also be cleared. Note, however, that FIFOs that are currently used for data
transfer to or from the host must not be cleared.
IRQ6 Interrupt
IRQ6
IRQ6
IRQ6
15.9.5
A suspend/resume interrupt requested by IRQ6 must be specified as falling-edge sensitive.
Rev. 3.0, 10/02, page 525 of 686
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