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Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10
value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output
controller 1 is inverted. Thus, when using the 8-bit timer/event counter as a 16-bit interval timer,
set the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation
instruction.
Table 7-9. Interval Time When 2-Channel 8-Bit Timer/Event Counter
TCL13
TCL12
TCL11
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Other than above
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses apply to operation with f
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
(TM1 and TM2) Is Used as 16-Bit Timer/Event Counter
TCL10
Minimum Interval Time
0
TI1 input cycle
1
TI1 input cycle
1
2 x 1/f
(400 ns)
X
0
2
2
x 1/f
(800 ns)
X
(1.6 µ s)
3
1
2
x 1/f
X
(3.2 µ s)
0
2
4
x 1/f
X
(6.4 µ s)
5
1
2
x 1/f
X
(12.8 µ s)
0
2
6
x 1/f
X
(25.6 µ s)
1
2
7
x 1/f
X
(51.2 µ s)
8
0
2
x 1/f
X
(102.4 µ s)
1
2
9
x 1/f
X
(204.8 µ s)
10
0
2
x 1/f
X
(819.2 µ s)
1
2
12
x 1/f
X
Setting prohibited
User's Manual U11302EJ4V0UM
Maximum Interval Time
2
8
x TI1 input cycle
8
2
x TI1 input cycle
17
2
x 1/f
(26.2 ms)
X
2
18
x 1/f
(52.4 ms)
X
19
2
x 1/f
(104.9 ms)
X
2
20
x 1/f
(209.7 ms)
X
21
2
x 1/f
(419.4 ms)
X
2
22
x 1/f
(838.9 ms)
X
2
23
x 1/f
(1.7 s)
X
24
2
x 1/f
(3.4 s)
X
2
25
x 1/f
(6.7 s)
X
26
2
x 1/f
(13.4 s)
X
2
28
x 1/f
(53.7 s)
X
= 5.0 MHz.
X
Resolution
TI1 input edge cycle
TI1 input edge cycle
2 x 1/f
(400 ns)
X
2
2
x 1/f
(800 ns)
X
(1.6 µ s)
3
2
x 1/f
X
(3.2 µ s)
2
4
x 1/f
X
(6.4 µ s)
5
2
x 1/f
X
(12.8 µ s)
2
6
x 1/f
X
(25.6 µ s)
2
7
x 1/f
X
(51.2 µ s)
8
2
x 1/f
X
(102.4 µ s)
2
9
x 1/f
X
(204.8 µ s)
10
2
x 1/f
X
(819.2 µ s)
2
12
x 1/f
X
163
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