Table of Contents
Advertisement
(3) Signals
Figure 13-32 shows the RELT and CMDT operations.
SO0 latch
RELT
CMDT
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following
two conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start.
2. Because the N-ch open-drain output must be high impedance for data reception,
write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag
(CSIIF0) is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into serial I/
O shift register 0 (SIO0) of the transmitting device. Thus, transmit errors can be detected in the following
two ways.
(a) Comparison of SIO0 data before transmission to that after transmission
In this case, if the two data differ, a transmit error is judged to have occurred.
(b) Use of the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the
COI bit (match signal coming from the address comparator) of serial operating mode register 0
(CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit
error is judged to have occurred.
254
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
Figure 13-32. RELT and CMDT Operations
User's Manual U11302EJ4V0UM
Advertisement
Table of Contents
