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16.4.5 Interrupt request hold
Some instructions hold an interrupt request, if any, pending until the completion of execution of the next instruction.
These instructions (that hold an interrupt request pending) are listed below.
• MOV
PSW, #byte
• MOV
A, PSW
• MOV
PSW, A
• MOV1
PSW.bit, CY
• MOV1
CY, PSW.bit
• AND1
CY, PSW.bit
• OR1
CY, PSW.bit
• XOR1
CY, PSW.bit
• SET1
PSW.bit
• CLR1
PSW.bit
• RETB
• RETI
• PUSH
PSW
• POP
PSW
• BT
PSW.bit, $addr16
• BF
PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
• Manipulation instructions for IF0L, IF0H, MK0L, MK0H, PR0L, PR0H and INTM0 registers
Caution The BRK instruction does not belong to the above group of instructions. However, the software
interrupt that is started by execution of the BRK instruction clears the IE flag to 0. Therefore,
even if a maskable interrupt request is generated, it is not acknowledged when the BRK
instruction is executed. However, a non-maskable interrupt request is acknowledged.
The timing at which interrupt requests are held pending is shown in Figure 16-16.
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
356
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
Figure 16-16. Interrupt Request Hold
Instruction N
User's Manual U11302EJ4V0UM
Save PSW and PC,
Instruction M
jump to interrupt servicing
Interrupt servicing
program
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