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CPU
8. Exception Handling
The H8/300L CPU supports two types of exceptions: resets and interrupts. When the H8/300L
CPU starts interrupt exception handling, it saves the PC and CCR on the stack by referencing
the SP. Then it sets the CCR I bit to 1 and fetches the starting address of the interrupt handling
routine from the vector table.
Note that reset is the highest priority exception, and that when multiple interrupts occur at the
same time they are processed according to their relative priorities. (See the description of the
interrupt vector table.)
Priority
Exception Type
1
Reset
2
Interrupt
Note: * Not detected after the ANDC, ORC, XORC, and LDC instructions.
Interrupt Handling
Interrupt factors fall into two classes: external interrupts requested from external pins and
internal interrupts requested by on-chip peripheral modules. Both external and internal
interrupts are masked by the CCR I bit. That is, all interrupts are masked when the CCR I bit is
set to 1. A unique vector address is allocated to each interrupt.
Interrupts are controlled by the interrupt controller. When multiple interrupts are requested at
the same time, the interrupt controller selects the highest priority interrupt, and leaves the
lower priority interrupts pending. When an interrupt occurs, the H8/300L CPU stores the
program counter and CCR contents in the location indicated by the stack pointer, then fetches
the address of the interrupt handler from the vector table, and begins executing that interrupt
handler.
Activation Factors
Reset exception processing starts when the RES pin changes from
low to high.
When an interrupt occurs, interrupt handling starts at the
completion of the current instruction execution.*
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