Page 1 User’s Manual V850E/IA1 32-Bit Single-Chip Microcontrollers Hardware µ µ µ µ PD703116 µ µ µ µ PD703116(A) µ µ µ µ PD703116(A1) µ µ µ µ PD70F3116 µ µ µ µ PD70F3116(A) µ µ µ µ PD70F3116(A1) Document No. U14492EJ3V0UD00 (3rd edition) Date Published February 2003 N CP(K) ©...
Page 2 [MEMO] User’s Manual U14492EJ3V0UD...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V850 Series, V850E/IA1, and V850E/IA2 are trademarks of NEC Electronics Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Page Description p.110 Modification of description in 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access p.140 Addition of description to 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) p.140 Addition of description to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) p.142...
Page 7 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850E/IA1 and design application systems using it. The target products are as follows. • Standard products: µ PD703116, 70F3116 • Special products: µ PD703116(A), 703116(A1), 70F3116(A), 70F3116(A1) Purpose This manual introduces the hardware functions of the V850E/IA1 shown below for user’s understanding.
Page 8 • To know details of the electrical specifications of the V850E/IA1 →Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS. • To understand the overall functions of the V850E/IA1 →Read this manual according to the CONTENTS. • How to read register formats → The name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file.
Page 9 Documents related to development tools (User’s Manuals) Document Name Document No. IE-V850E-MC, IE-V850E-MC-A (In-Circuit Emulator) U14487E IE-703116-MC-EM1 (In-Circuit Emulator Option Board) U14700E CA850 Ver.2.40 or Later C Compiler Operation U15024E Package C Language U15025E Project Manager U15026E Assembly Language U15027E ID850 Ver.2.40 Integrated Debugger Operation Windows Based...
Page 10: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................30 Outline ............................30 Features............................32 Applications..........................33 Ordering Information ........................ 34 Pin Configuration (Top View) ....................35 Configuration of Function Block ..................... 37 1.6.1 Internal block diagram ......................... 37 1.6.2 Internal units ..........................38 Differences Between Products ....................40 CHAPTER 2 PIN FUNCTIONS ........................41 List of Pin Functions.........................
Page 11 Memory Block Function ......................111 4.3.1 Chip select control function ......................112 Bus Cycle Type Control Function ..................115 Bus Access..........................116 4.5.1 Number of access clocks ......................116 4.5.2 Bus sizing function ........................117 4.5.3 Word data processing format .....................117 4.5.4 Bus width............................118 Wait Function ...........................124 4.6.1 Programmable wait function.......................124 4.6.2...
Page 12 6.6.1 Two-cycle transfer ........................157 Transfer Object........................158 6.7.1 Transfer type and transfer object....................158 6.7.2 External bus cycles during DMA transfer (two-cycle transfer) ........... 159 DMA Channel Priorities ......................159 Next Address Setting Function....................159 6.10 DMA Transfer Start Factors ....................161 6.11 Forcible Interruption .......................
Page 13 8.3.5 Peripheral status register (PHS)....................210 PLL Lockup..........................211 Power Save Control .........................212 8.5.1 Overview ............................212 8.5.2 Control registers .........................215 8.5.3 HALT mode ..........................218 8.5.4 IDLE mode ..........................220 8.5.5 Software STOP mode ........................222 Securing Oscillation Stabilization Time ................224 8.6.1 Oscillation stabilization time security specification ..............224 8.6.2 Time base counter (TBC) ......................225 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)........226...
Page 14 9.5.7 Precautions..........................411 Timer Connection Function ....................412 9.6.1 Overview............................ 412 9.6.2 Control register .......................... 413 CHAPTER 10 SERIAL INTERFACE FUNCTION.................414 10.1 Features............................ 414 10.2 Asynchronous Serial Interface 0 (UART0)................415 10.2.1 Features ............................ 415 10.2.2 Configuration ..........................416 10.2.3 Control registers ........................
Page 15 11.8.7 Baud rate control function ......................544 11.9 Cautions on Bit Set/Clear Function..................547 11.10 Control Registers ........................549 11.11 Operations ..........................601 11.11.1 Initialization processing ......................601 11.11.2 Transmit setting..........................612 11.11.3 Receive setting...........................613 11.11.4 CAN sleep mode ........................614 11.11.5 CAN stop mode ..........................615 11.12 Rules for Correct Setting of Baud Rate .................617 11.13 Prioritization of Message Buffers During Receive Comparison .........620 11.13.1 Reception of data frames ......................620 11.13.2 Reception of remote frames .......................621...
Page 16 13.6.2 Operation in scan mode ......................664 13.7 Operation in A/D Trigger Polling Mode ................. 665 13.7.1 Operation in select mode......................665 13.7.2 Operation in scan mode ......................666 13.8 Operation in Timer Trigger Mode ..................667 13.8.1 Operation in select mode......................667 13.8.2 Operation in scan mode ......................
Page 17 16.5 Pin Connection.........................733 16.5.1 pin............................733 16.5.2 Serial interface pin........................733 16.5.3 RESET pin ..........................735 16.5.4 NMI pin............................735 16.5.5 MODE0 to MODE2 pins ......................735 16.5.6 Port pins .............................735 16.5.7 Other signal pins ........................735 16.5.8 Power supply..........................736 16.6 Programming Method......................736 16.6.1 Flash memory control.........................736 16.6.2 Flash memory programming mode.....................737 16.6.3...
Page 18 APPENDIX C INSTRUCTION SET LIST ....................805 Functions ..........................805 Instruction Set (Alphabetical Order) ..................808 APPENDIX D INDEX..........................814 APPENDIX E REVISION HISTORY......................823 User’s Manual U14492EJ3V0UD...
Page 19 LIST OF FIGURES (1/8) Figure No. Title Page CPU Address Space ............................69 Image on Address Space ..........................70 Memory Map ..............................72 Internal ROM/Internal Flash Memory Area..................... 73 Internal ROM Area in Single-Chip Mode 1 ..................... 75 Recommended Memory Map ......................... 80 Programmable Peripheral I/O Register (Outline)....................
Page 20 LIST OF FIGURES (2/8) Figure No. Title Page Specification of INTTM0n Interrupt During PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (MOD01, MOD00 Bits of TMC0n Register = 0n) ........238 Interrupt Culling Processing..........................239 Interrupt Culling Ratio Change Timing (Relationship Between STINTn Bit Setting and CUL Bit Change): PWM Mode 1 (Asymmetric Triangular Wave)....................240 Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (Without Dead Time (TM0CED0 Bit = 1)) .....................244...
Page 21 LIST OF FIGURES (3/8) Figure No. Title Page 9-40 Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/2 ............. 293 9-41 Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/1 ............................
Page 22 LIST OF FIGURES (4/8) Figure No. Title Page 9-71 Capture Operation: Mode with 16-Bit Buffer (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0)..367 9-72 Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register’s TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary, EEVEy Bit = 1, and CSCE0 Register’s...
Page 23 LIST OF FIGURES (5/8) Figure No. Title Page 10-3 Asynchronous Serial Interface Transmission Completion Interrupt Timing ..........428 10-4 Continuous Transmission Processing Flow....................430 10-5 Continuous Transmission Starting Procedure ....................431 10-6 Continuous Transmission End Procedure ....................432 10-7 Asynchronous Serial Interface Reception Completion Interrupt Timing ............434 10-8 When Reception Error Interrupt Is Separated from INTSR0 Interrupt (ISRM Bit = 0)........
Page 24 LIST OF FIGURES (6/8) Figure No. Title Page 11-11 Arbitration Field (In Extended Format Mode)....................533 11-12 Control Field ..............................534 11-13 Data Field ..............................535 11-14 CRC Field ..............................535 11-15 ACK Field ..............................536 11-16 End of Frame (EOF) .............................536 11-17 Interframe Space ............................537 11-18 Error Frame ..............................538 11-19 Overload Frame............................539 11-20 Nominal Bit Time ............................544...
Page 25 LIST OF FIGURES (7/8) Figure No. Title Page 13-4 Example of Select Mode Operation Timing (ANI01): For A/D Converter 0........... 661 13-5 Example of Scan Mode Operation Timing: For A/D Converter 0 (4-Channel Scan (ANI00 to ANI03))..662 13-6 Example of Select Mode (A/D Trigger Select) Operation (ANI02): For A/D Converter 0 ......663 13-7 Example of Scan Mode (A/D Trigger Scan) Operation (ANI02 to ANI05): For A/D Converter 0....
Page 26 LIST OF FIGURES (8/8) Figure No. Title Page 16-8 Conflict of Signals (RESET Pin) ........................735 16-9 Flash Memory Manipulating Procedure ......................736 16-10 Flash Memory Programming Mode ......................737 16-11 Communication Commands .........................738 16-12 Outline of Self-Programming ........................739 16-13 Outline of Self-Programming Interface ......................741 16-14 Example of Self-Programming Circuit Configuration ..................741 16-15 Timing to Apply Voltage to V Pin .......................742...
Page 27 LIST OF TABLES (1/3) Table No. Title Page Differences Between V850E/IA1 and V850E/IA2 ................... 31 Differences Between V850E/IA1 and V850E/IA2 Register Setting Values............. 31 Program Registers ............................64 System Register Numbers ..........................65 Interrupt/Exception Table ..........................74 Bus Priority Order............................130 Relationship Between Transfer Type and Transfer Object................
Page 28 LIST OF TABLES (2/3) Table No. Title Page 10-6 ASIMn0, ASIMn1 Register Settings and Data Format ..................460 10-7 Reception Error Causes ..........................467 10-8 Baud Rate Generator Setting Data (BRG = f /2) ..................478 10-9 SCKn Pin Output Status ..........................515 10-10 SOn Pin Output Status ..........................515 10-11 Baud Rate Generator Setting Data.......................519 11-1 Overview of Functions ..........................520...
Page 29 LIST OF TABLES (3/3) Table No. Title Page 13-3 Correspondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers ......655 15-1 Operation Status of Each Pin During Reset Period ..................721 15-2 Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset ........... 723 16-1 Connection of V850E/IA1 Flash Programming Adapter (FA-144GJ-8EU)............
Page 30: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850E/IA1 is a product in the V850 Series of NEC Electronics Corporation single-chip microcontrollers. This chapter provides an overview of the V850E/IA1. 1.1 Outline The V850E/IA1 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation.
Page 31 CHAPTER 1 INTRODUCTION Table 1-1 lists the differences between the V850E/IA1 and V850E/IA2. Table 1-2 lists the differences between the V850E/IA1 and V850E/IA2 register setting values. Table 1-1. Differences Between V850E/IA1 and V850E/IA2 Item V850E/IA1 V850E/IA2 Maximum operating frequency 50 MHz 40 MHz µ...
Page 32: Features
CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions Minimum instruction execution time 20 ns (@ internal 50 MHz operation) General-purpose registers 32 bits × 32 registers Instruction set V850E1 CPU Signed multiplication (32 bits × 32 bits → 64 bits): 1 or 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instruction: 1 clock Bit manipulation instructions...
Page 33: Applications
CHAPTER 1 INTRODUCTION DMA controller 4-channel configuration Transfer unit: 8 bits/16 bits Maximum transfer count: 65,536 (2 Transfer type: 2-cycle transfer Transfer modes: Single transfer, single-step transfer, block transfer Memory ↔ Memory, Memory ↔ I/O, I/O ↔ I/O Transfer subjects: Transfer requests: On-chip peripheral I/O, software Next address setting function...
Page 34: Ordering Information
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 35: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) • • • • 144-pin plastic LQFP (fine pitch) (20 × × × × 20) µ µ µ µ PD703116GJ-××× ××× ×××-UEN, 703116GJ(A)-××× ××× ××× ×××-UEN, 703116GJ(A1)-××× ××× ××× ×××-UEN ××× µ µ µ µ PD70F3116GJ-UEN, 70F3116GJ(A)-UEN, 70F3116GJ(A1)-UEN ANI07 TIUD11/TO11/P13 TCLR10/INTP101/P12...
Page 36 CHAPTER 1 INTRODUCTION Pin Identification A16 to A23: Address bus P20 to P27: Port 2 AD0 to AD15: Address/data bus P30 to P37: Port 3 AD0_DBG to AD3_DBG: Debug address/data bus P40 to P47: Port 4 ADTRG0, ADTRG1: A/D trigger input PCM0 to PCM4: Port CM ANI00 to ANI07,...
Page 37: Configuration Of Function Block
CHAPTER 1 INTRODUCTION 1.6 Configuration of Function Block 1.6.1 Internal block diagram MEMC INTP0 to INTP6 Instruction INTC SRAMC HLDRQ INTP20 to INTP25 queue Note 1 HLDAK INTP30, INTP31 32-bit CS0 to CS7 INTP100, INTP101 barrel Multiplier ROMC INTP110, INTP111 shifter ASTB 32×32...
Page 38: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses 5-stage pipeline control to execute address calculation, arithmetic and logical operation, data transfer, and most other instruction processing in one clock. A multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accelerate complex instruction processing.
Page 39 CHAPTER 1 INTRODUCTION (9) Real-time pulse unit (RPU) The RPU has a 2-channel 16-bit timer (TM0) for 3-phase sine wave PWM inverter control, a 2-channel 16-bit up/down counter (TM1) that can be used for 2-phase encoder input or as a general-purpose timer, a 2- channel 16-bit general-purpose timer unit (TM2), a 1-channel 16-bit timer/event counter (TM3), and a 1- channel 16-bit interval timer (TM4) on-chip.
Page 40: Differences Between Products
CHAPTER 1 INTRODUCTION 1.7 Differences Between Products µ PD703116 µ PD703116(A) µ PD703116(A1) µ PD70F3116 µ PD70F3116(A) µ PD70F3116(A1) Item Internal ROM Mask ROM Flash memory 256 KB Internal RAM 10 KB NBD (Non Break Not provided Provided Debug) function (IC1 to IC4) (TRIG_DBG, AD0_DBG to AD3_DBG, SYNC, CLK_DBG)
Page 41: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the V850E/IA1 pins are shown below. These pins can be divided by function into port pins and non-port pins. 2.1 List of Pin Functions (1) Port pins (1/3) Pin Name Function Alternate Function Port 0 8-bit input-only port...
Page 42 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function Port 4 8-bit I/O port Input or output can be specified in 1-bit units SCK0 SCK1 CRXD CTXD PCM0 Port CM WAIT 5-bit I/O port PCM1 CLKOUT Input or output can be specified in 1-bit units PCM2 HLDAK PCM3...
Page 43 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function PDL0 Port DL 16-bit I/O port PDL1 Input or output can be specified in 1-bit units PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14...
Page 44 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name Function Alternate Function − TO000 Timer 00 pulse signal output − TO001 − TO002 − TO003 − TO004 − TO005 − TO010 Timer 01 pulse signal output − TO011 − TO012 −...
Page 45 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function INTP100 External maskable interrupt request input and timer 10 external capture P11/TCUD10 trigger input INTP101 P12/TCLR10 INTP110 External maskable interrupt request input and timer 11 external capture P14/TCUD11 trigger input INTP111 P15/TCLR11 INTP20...
Page 46 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function WAIT Control signal input to insert wait in bus cycle PCM0 HLDAK Bus hold acknowledge output PCM2 HLDRQ Bus hold request input PCM3 External data lower byte write strobe signal output PCT0 External data upper byte write strobe signal output PCT1...
Page 47: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The following table shows the status of each pin after a reset, in power-saving mode (software STOP mode, IDLE, HALT), on a DMA transfer, and on a bus hold. Operating Status Reset Reset IDLE Mode/ HALT Mode/ (Single-Chip...
Page 48: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) … Input Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as an input port, in control mode, P00 to P07 operate as NMI input, real-time pulse unit (RPU) output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input.
Page 49 CHAPTER 2 PIN FUNCTIONS (2) P10 to P15 (Port 1) … I/O Port 1 is a 6-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P10 to P15 operate as RPU I/O and external interrupt request input.
Page 50 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) … I/O Port 2 is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P20 to P27 operate as RPU I/O and external interrupt request input.
Page 51 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) … I/O Port 3 is an 8-bit I/O that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface (UART0 to UART2) I/O.
Page 52 CHAPTER 2 PIN FUNCTIONS (5) P40 to P47 (Port 4) … I/O Port 4 is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P40 to P47 operate as serial interface (CSI0, CSI1, FCAN) I/O.
Page 53 CHAPTER 2 PIN FUNCTIONS (6) PCM0 to PCM4 (Port CM) … I/O Port CM is a 5-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, PCM0 to PCM4 operate as wait insertion signal input, internal system clock output, and bus hold control signal output.
Page 54 CHAPTER 2 PIN FUNCTIONS (7) PCT0 to PCT7 (Port CT) … I/O Port CT is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, it operates as control signal output for when memory is expanded externally.
Page 55 CHAPTER 2 PIN FUNCTIONS (8) PCS0 to PCS7 (Port CS) … I/O Port CS is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, these operate as chip select signal output for when memory is expanded externally.
Page 56 CHAPTER 2 PIN FUNCTIONS (10) PDL0 to PDL7 (Port DL) … I/O Port DL is a 16-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address/data bus (AD0 to AD15) for when memory is expanded externally.
Page 57 CHAPTER 2 PIN FUNCTIONS (15) MODE0 to MODE2 (Mode) … Input These are the input pins that specify the operation mode. Operation modes are broadly divided into normal operation modes and flash memory programming mode. The normal operation modes are single-chip modes 0 and 1 and ROMless modes 0 and 1 (see 3.3 Operation Modes for details).
Page 58 CHAPTER 2 PIN FUNCTIONS (20) V (Power supply) This is the positive power supply pin for the peripheral interface. (21) V (Ground) This is the ground pin for the peripheral interface. (22) V (Power supply) This is the positive power supply pin for the internal CPU. (23) V (Ground) This is the ground pin for the internal CPU.
Page 59: Types Of Pin I/O Circuit And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Types of Pin I/O Circuit and Connection of Unused Pins Connection of a 1 to 10 kΩ resistor is recommended when connecting to V , CV , CV , or AV via a resistor. (1/2) I/O Circuit Type Recommended Connection P00/NMI...
Page 60 CHAPTER 2 PIN FUNCTIONS (2/2) I/O Circuit Type Recommended Connection PCM3/HLDRQ Input status: Independently connect to V or V via a resistor. Output status: Leave open. PCM4 PCT0/LWR PCT1/UWR PCT2 PCT3 PCT4/RD PCT5 PCT6/ASTB PCT7 PCS0/CS0 PCS1/CS1 PCS2/CS2 PCS3/CS3 PCS4/CS4 PCS5/CS5 PCS6/CS6 PCS7/CS7...
Page 61: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 5 Data P-ch IN/OUT Output N-ch disable Input Schmitt-triggered input with hysteresis characteristics enable Type 3 Type 5-AC Data P-ch IN/OUT P-ch Output N-ch disable N-ch Input enable Type 4 Type 7 Data P-ch...
Page 62: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/IA1 is based on RISC architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features • Minimum instruction execution time: 20 ns (@ internal 50 MHz operation) •...
Page 63: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/IA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E1 Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 64: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 65: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2.
Page 66 CHAPTER 3 CPU FUNCTION (2) Program status word (PSW) Initial value 00000020H Bit Position Flag Function 31 to 8 Reserved field (fixed to 0). Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set when an NMI is acknowledged, and disables multiple interrupts. 0: NMI servicing not under execution.
Page 67: Operation Modes
CHAPTER 3 CPU FUNCTION 3.3 Operation Modes 3.3.1 Operation modes The V850E/IA1 has the following operation modes. Mode specification is carried out by the MODE0 to MODE2 pins. (1) Normal operation mode (a) Single-chip modes 0, 1 Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts.
Page 68: Operation Mode Specification
CHAPTER 3 CPU FUNCTION 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation.
Page 69: Address Space
CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/IA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 70: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image 16 images, each containing a 256 MB physical address space, are seen in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address.
Page 71: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 72: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/IA1 reserves areas as shown below. Each mode is specified by the MODE0 to MODE2 pins. Figure 3-3. Memory Map Single-chip mode 0 Single-chip mode 1 ROMless mode 0, 1 xFFFFFFFH On-chip peripheral On-chip peripheral On-chip peripheral 4 KB...
Page 73: Area
CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal ROM/internal flash memory area (a) Memory map Up to 1 MB of internal ROM/internal flash memory area is reserved. 256 KB are provided in the following addresses as physical internal ROM (mask ROM/flash memory). •...
Page 74 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Start Address of Interrupt/Exception Interrupt/Exception Table Source Interrupt/Exception Table Source 00000000H RESET 00000200H INTP21/INTCC21 00000010H NMI0 00000210H INTP22/INTCC22 00000040H TRAP0n (n = 0 to F) 00000220H INTP23/INTCC23 00000050H TRAP1n (n = 0 to F) 00000230H INTP24/INTCC24...
Page 75 CHAPTER 3 CPU FUNCTION (c) Internal ROM area relocation function If set in single-chip mode 1, the internal ROM area is located beginning from address 100000H, so booting from external memory becomes possible. Therefore, in order to resume correct operation after reset, provide a handler address to the reset routine in address 0 of the external memory.
Page 76 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and Note 3FFFFFFH Note Access to the area of addresses 3FFF000H to 3FFFFFFH is prohibited.
Page 77 CHAPTER 3 CPU FUNCTION (4) External memory area 256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the higher 192 MB as data area. • When in single-chip mode 0: x0100000H to xFFFBFFFH •...
Page 78: External Memory Expansion
CHAPTER 3 CPU FUNCTION 3.4.6 External memory expansion By setting the port n mode control register (PMCn) to control mode, an external device can be connected to the external memory space using each pin of ports DH, DL, CS, CT, and CM. Each register is set by selecting control mode for each pin of these ports using PMCn (n = DH, DL, CS, CT, CM).
Page 79: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.7 Recommended use of address space The architecture of the V850E/IA1 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. Operand data access from instruction can be directly executed at the address in this pointer register ±32 KB.
Page 80 CHAPTER 3 CPU FUNCTION Figure 3-6. Recommended Memory Map Program space Data space FFFFFFFFH On-chip FFFFFA78H peripheral I/O FFFFFA77H FFFFF000H FFFFEFFFH Internal RAM FFFFE800H FFFFE7FFH xFFFFFFFH On-chip xFFFFA78H peripheral I/O FFFFC000H xFFFFA77H FFFFBFFFH xFFFF000H xFFFEFFFH Internal RAM xFFFE800H xFFFE7FFH xFFFC000H 04000000H xFFFBFFFH 03FFFFFFH...
Page 81: On-Chip Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 On-chip peripheral I/O registers (1/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF004H Port DL Undefined √ √ FFFFF004H Port DLL PDLL Undefined √ √...
Page 82 CHAPTER 3 CPU FUNCTION (2/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF094H DMA destination address register 2L DDA2L Undefined √ FFFFF096H DMA destination address register 2H DDA2H Undefined √...
Page 83 CHAPTER 3 CPU FUNCTION (3/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF11AH Interrupt control register P0IC5 √ √ FFFFF11CH Interrupt control register P0IC6 √ √ FFFFF11EH Interrupt control register DETIC0 √...
Page 84 CHAPTER 3 CPU FUNCTION (4/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF164H Interrupt control register CSIIC1 √ √ FFFFF166H Interrupt control register SRIC0 √ √ FFFFF168H Interrupt control register STIC0 √...
Page 85 CHAPTER 3 CPU FUNCTION (5/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF244H A/D voltage detection mode register 1 ADETM1 0000H √ √ FFFFF244H A/D voltage detection mode register 1L ADETM1L √...
Page 86 CHAPTER 3 CPU FUNCTION (6/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF572H Buffer register CM00 BFCM00 FFFFH √ FFFFF574H Buffer register CM01 BFCM01 FFFFH √ FFFFF576H Buffer register CM02 BFCM02 FFFFH √...
Page 87 CHAPTER 3 CPU FUNCTION (7/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ √ FFFFF5EFH Status register 0 STATUS0 √ √ FFFFF5F6H CC101 capture input selection register CSL10 √ √ FFFFF5F8H Timer 10 noise elimination time selection register NRC10 √...
Page 88 CHAPTER 3 CPU FUNCTION (8/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF646H Timer 2 time base control register 0 TCRE0 0000H √ √ FFFFF646H Timer 2 time base control register 0L TCRE0L √...
Page 89 CHAPTER 3 CPU FUNCTION (9/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF668H Timer 2 output delay register 0 ODELE0 0000H √ √ FFFFF668H Timer 2 output delay register 0L ODELE0L √...
Page 90 CHAPTER 3 CPU FUNCTION (10/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFF908H Clocked serial interface initial transmission SOTBF0 0000H buffer register 0 √ √ FFFFF908H Clocked serial interface initial transmission SOTBFL0 buffer register L0 √...
Page 91 CHAPTER 3 CPU FUNCTION (11/11) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ FFFFFA26H Transmission shift register L1 TXSL1 Undefined √ √ FFFFFA28H Asynchronous serial interface mode register 10 ASIM10 √...
Page 92: Programmable Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.9 Programmable peripheral I/O registers In the V850E/IA1, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x2000H and x2FFFH is used exclusively for the FCAN controller. The internal bus of the V850E/IA1 becomes active when the on-chip peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n = xx11B).
Page 93 CHAPTER 3 CPU FUNCTION (1) Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. Address Initial value FFFFF064H 0000H PA15 PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 Bit Position Bit Name Function PA15...
Page 94 CHAPTER 3 CPU FUNCTION (1/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn804H CAN message data length register 00 M_DLC00 Undefined √ xxxxn805H CAN message control register 00 M_CTRL00 Undefined √...
Page 95 CHAPTER 3 CPU FUNCTION (2/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn849H CAN message data register 021 M_DATA021 Undefined √ xxxxn84AH CAN message data register 022 M_DATA022 Undefined √...
Page 96 CHAPTER 3 CPU FUNCTION (3/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn88DH CAN message data register 045 M_DATA045 Undefined √ xxxxn88EH CAN message data register 046 M_DATA046 Undefined √...
Page 97 CHAPTER 3 CPU FUNCTION (4/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn8D2H CAN message ID register H06 M_IDH06 Undefined √ xxxxn8D4H CAN message configuration register 06 M_CONF06 Undefined √...
Page 98 CHAPTER 3 CPU FUNCTION (5/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn924H CAN message data length register 09 M_DLC09 Undefined √ xxxxn925H CAN message control register 09 M_CTRL09 Undefined √...
Page 99 CHAPTER 3 CPU FUNCTION (6/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn969H CAN message data register 111 M_DATA111 Undefined √ xxxxn96AH CAN message data register 112 M_DATA112 Undefined √...
Page 100 CHAPTER 3 CPU FUNCTION (7/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn9ADH CAN message data register 135 M_DATA135 Undefined √ xxxxn9AEH CAN message data register 136 M_DATA136 Undefined √...
Page 101 CHAPTER 3 CPU FUNCTION (8/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxn9F2H CAN message ID register H15 M_IDH15 Undefined √ xxxxn9F4H CAN message configuration register 15 M_CONF15 Undefined √...
Page 102 CHAPTER 3 CPU FUNCTION (9/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnA44H CAN message data length register 18 M_DLC18 Undefined √ xxxxnA45H CAN message control register 18 M_CTRL18 Undefined √...
Page 103 CHAPTER 3 CPU FUNCTION (10/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnA89H CAN message data register 201 M_DATA201 Undefined √ xxxxnA8AH CAN message data register 202 M_DATA202 Undefined √...
Page 104 CHAPTER 3 CPU FUNCTION (11/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnACDH CAN message data register 225 M_DATA225 Undefined √ xxxxnACEH CAN message data register 226 M_DATA226 Undefined √...
Page 105 CHAPTER 3 CPU FUNCTION (12/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnB12H CAN message ID register H24 M_IDH24 Undefined √ xxxxnB14H CAN message configuration register 24 M_CONF24 Undefined √...
Page 106 CHAPTER 3 CPU FUNCTION (13/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnB64H CAN message data length register 27 M_DLC27 Undefined √ xxxxnB65H CAN message control register 27 M_CTRL27 Undefined √...
Page 107 CHAPTER 3 CPU FUNCTION (14/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnBA9H CAN message data register 291 M_DATA291 Undefined √ xxxxnBAAH CAN message data register 292 M_DATA292 Undefined √...
Page 108 CHAPTER 3 CPU FUNCTION (15/15) Address Function Register Name Symbol Bit Units for Manipulation Initial Value 1 Bit 8 Bits 16 Bits √ xxxxnBEDH CAN message data register 315 M_DATA315 Undefined √ xxxxnBEEH CAN message data register 316 M_DATA316 Undefined √...
Page 109: Specific Registers
CHAPTER 3 CPU FUNCTION 3.4.10 Specific registers Specific registers are registers that are protected from being written with illegal data due to inadvertent program loop (runaway), etc. The V850E/IA1 has three specific registers, the power save control register (PSC) (refer to 8.5.2 Control registers), clock control register (CKC) (refer to 8.3.4 Clock control register (CKC)), and flash programming mode control register (FLPMC) (refer to 16.7.12 Flash programming mode control register (FLPMC)).
Page 110: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850E/IA1 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8-space chip select function •...
Page 111: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH.
Page 112: Chip Select Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signal.
Page 113 CHAPTER 4 BUS CONTROL FUNCTION Address Initial value CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 FFFFF060H 2C11H Address Initial value CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60...
Page 114 CHAPTER 4 BUS CONTROL FUNCTION The following diagram shows the CS signal, which is enabled for area 0 when the CSC0 register is set to 0703H. When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed.
Page 115: Bus Cycle Type Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/IA1, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O Connected external devices are specified by bus cycle type configuration registers 0, 1 (BCT0, BCT1). (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units.
Page 116: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks required to access each resource is shown below. Bus Cycle Status Instruction Fetch Operand Data Access Resource (Bus Width) Note 1 Internal ROM (32 bits) Note 2 Internal RAM (32 bits) −...
Page 117: Bus Sizing Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 118: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.5.4 Bus width The V850E/IA1 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower side. (1) Byte access (8 bits) (a) When the data bus width is 16 bits (little endian) <1>...
Page 119 CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) When the data bus width is 16 bits (little endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1st access 2nd access Address Address Address 2n + 1...
Page 120 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the data bus width is 16 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data...
Page 121 CHAPTER 4 BUS CONTROL FUNCTION (a) When the data bus width is 16 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data...
Page 122 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External...
Page 123 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data...
Page 124: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states in the starting bus cycle for each CS space.
Page 125 CHAPTER 4 BUS CONTROL FUNCTION (2) Address wait control register (AWC) In the V850E/IA1, address setup wait and address hold wait states can be inserted before and after the T1 cycle, respectively. These wait states can be set for each CS space via the AWC register. This register can be read/written in 16-bit units.
Page 126: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits.
Page 127: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, a set number of idle states (TI) can be inserted into the starting bus cycle after the T3 state to secure the data output float delay time (t ) of the memory when each CS space is read accessed.
Page 128: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Hold Function 4.8.1 Function outline If pins PCM2 and PCM3 are specified in the control mode, the HLDAK and HLDRQ functions become valid. If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold state).
Page 129: Operation In Power Save Mode
CHAPTER 4 BUS CONTROL FUNCTION 4.8.3 Operation in power save mode In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not accepted and set since the HLDRQ pin cannot be accepted even if it becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold state is set.
Page 130: Bus Priority Order
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority Order There are four external bus cycles: bus hold, DMA cycle, operand data access, and instruction fetch. In order of priority, bus hold is the highest, followed by DMA cycle, operand data access, and instruction fetch, in that order.
Page 131: Boundary Operation Conditions
CHAPTER 4 BUS CONTROL FUNCTION 4.10 Boundary Operation Conditions 4.10.1 Program space (1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), a data to be fetched is undefined and the operation is not guaranteed.
Page 132: Chapter 5 Memory Access Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 2 states. • A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings.
Page 133: Sram, External Rom, External I/O Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-1. SRAM, External ROM, External I/O Access Timing (1/5) (a) On a read (1 wait insertion) CLKOUT (Output) A16 to A23 (Output) Address AD0 to AD15 (I/O) Address Data ASTB (Output)
Page 134 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/5) (b) On a read (0 wait, address setup wait, address hold wait state insertion) TASW TAHW CLKOUT (Output) Address A16 to A23 (Output) AD0 to AD15 (I/O) Address Data ASTB (Output)
Page 135 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (3/5) (c) On a write (1 wait insertion) CLKOUT (Output) Address A16 to A23 (Output) Note Address Data AD0 to AD15 (I/O) ASTB (Output) RD (Output) UWR, LWR (Output) CSn (Output) WAIT (Input)
Page 136 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/5) (d) On a write (0 wait insertion, for 8-bit data bus) CLKOUT (Output) Address A16 to A23 (Output) Address AD8 to AD15 (I/O) Note Address Data AD0 to AD7 (I/O)
Page 137 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (5/5) (e) Bus hold timing CLKOUT (Output) HLDRQ (Input) HLDAK (Output) Note 1 Undefined Address A16 to A23 (Output) Note 2 Undefined Undefined Address AD0 to AD15 (I/O) ASTB (Output) RD (Output) UWR, LWR (Output)
Page 138: Chapter 6 Dma Functions (Dma Controller)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, among memories or among I/Os, based on DMA requests issued by the on-chip peripheral I/O (such as serial interface, real-time pulse unit, and A/D converter), or software triggers (memory refers to internal RAM or external memory).
Page 139: Configuration
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register (DSAnH/DSAnL) control control DMA destination address register (DDAnH/DDAnL) DMA transfer count Count register (DBCn) control DMA channel control register (DCHCn) DMA addressing control...
Page 140: Control Registers
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 141 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. Address Initial value DSA0L SA15 SA14 SA13 SA12 SA11 SA10 FFFFF080H Undefined DSA1L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H Undefined DSA2L...
Page 142: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL.
Page 143 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. Address Initial value DDA0L DA15 DA14 DA13 DA12 DA11 DA10 FFFFF084H Undefined DDA1L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH Undefined DDA2L...
Page 144: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channel n (n = 0 to 3). They store the remaining transfer counts during DMA transfer.
Page 145: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. These registers can be read/written in 16-bit units.
Page 146 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit Position Bit Name Function 7, 6 SAD1, Sets the count direction of the source address for DMA channel n (n = 0 to 3). SAD0 SAD1 SAD0 Count Direction Increment Decrement Fixed Setting prohibited 5, 4 DAD1,...
Page 147: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 148 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> <3> <2> <1> <0> Address Initial value DCHC0 MLE0 INIT0 STG0 FFFFF0E0H DCHC1 MLE1 INIT1 STG1 FFFFF0E2H DCHC2 MLE2 INIT2 STG2 FFFFF0E4H DCHC3 MLE3 INIT3 STG3 FFFFF0E6H Bit Position Bit Name Function This status bit indicates whether DMA transfer through DMA channel n has ended or not. This bit is read-only.
Page 149: Dma Disable Status Register (Ddis)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register during forcible interruption by NMI input (n = 0 to 3). This register is read-only in 8-bit units. Be sure to set bits 4 to 7 to 0.
Page 150: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read/written in 8-bit units.
Page 151 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit Position Bit Name Function 5 to 0 IFCn5 to IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTDET0 INTDET1 INTTM00 INTCM003 INTTM01 INTCM013 INTP100/INTCC100 INTP101/INTCC101 INTCM100 INTCM101 INTP110/INTCC110 INTP111/INTCC111 INTCM110 INTCM111 INTTM20 INTTM21 INTP20/INTCC20...
Page 152: Dma Bus States
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 DMA Bus States 6.4.1 Types of bus states The DMAC bus states consist of the following 10 states. (1) TI state The TI state is an idle state, during which no access request is issued. The DMA request signals are sampled at the rising edge of the CLKOUT signal.
Page 153: Dmac Bus Cycle State Transition
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (10) TE state The TE state corresponds to DMA transfer completion. Various internal signals are initialized (n = 0 to 3). After entering the TE state, the bus invariably enters the TI state. 6.4.2 DMAC bus cycle state transition Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership is released.
Page 154: Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5 Transfer Mode 6.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 155 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-4 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0 and 3 are used for a single transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
Page 156: Single-Step Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. Once a DMA transfer request signal is received, transfer is performed again. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 157: Transfer Types
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Types 6.6.1 Two-cycle transfer In two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the destination address is output and writing is performed from the DMAC to the destination.
Page 158: Transfer Object
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.7 Transfer Object 6.7.1 Transfer type and transfer object Table 6-1 lists the relationships between transfer type and transfer object (√: transfer enabled, ×: transfer disabled). Table 6-1. Relationship Between Transfer Type and Transfer Object Destination Two-Cycle Transfer Internal ROM...
Page 159: External Bus Cycles During Dma Transfer (Two-Cycle Transfer)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.7.2 External bus cycles during DMA transfer (two-cycle transfer) The external bus cycles during DMA transfer (two-cycle transfer) are shown below. Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Transfer Object External Bus Cycle Note On-chip peripheral I/O, internal RAM None...
Page 160 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8. Buffer Register Configuration Data read Address/ Data write Master Slave count register register controller The actual DMA transfer is performed based on the settings of the slave register. The settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made.
Page 161: Dma Transfer Start Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request from software If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3). •...
Page 162: Dma Transfer End
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 DMA Transfer End When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt (INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3). 6.13 Forcible Termination In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register (n = 0 to 3).
Page 163: Interrupt Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (6) Execution of program and DMA transfer in internal RAM If the following conditions are both met, the CPU may deadlock due to conflicting operations of the internal bus (during deadlock, only reset is acknowledged (NMI and interrupt are not acknowledged)). If only either one of the conditions is met, the CPU will not deadlock.
Page 164: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 53 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 165 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit − − Reset Interrupt RESET RESET input 0000H 00000000H Undefined −...
Page 166 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit Maskable Interrupt INTP30/ CC3IC0 INTP30 pin/CC30 match Pin/RPU 0260H 00000260H nextPC INTCC30 Interrupt INTP31/...
Page 167: Non-Maskable Interrupt
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 168: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR.
Page 169 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request held pending regardless NMI request NMI request of the value of the NP bit of the PSW Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service program is being executed...
Page 170: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 171: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 172: Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/IA1 has 52 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 173 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-4. Servicing Configuration of Maskable Interrupt INT input INTC acknowledged xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 174: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 175: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/IA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 176 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 177 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 178 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt requests b and c are Servicing of interrupt request b Interrupt request c (level 1) acknowledged first according to their priorities.
Page 179: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Caution Read the xxIFn bit of the xxICn register in the interrupt disabled (DI) state.
Page 180 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> <6> <2> <1> <0> FFFFF110H P0IC0 P0IF0 P0MK0 P0PR02 P0PR01 P0PR00 FFFFF112H P0IC1 P0IF1 P0MK1 P0PR12 P0PR11 P0PR10 FFFFF114H P0IC2 P0IF2 P0MK2 P0PR22 P0PR21 P0PR20...
Page 181 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> <6> <2> <1> <0> FFFFF164H CSIIC1 CSIIF1 CSIMK1 CSIPR12 CSIPR11 CSIPR10 FFFFF166H SRIC0 SRIF0 SRMK0 SRPR02 SRPR01 SRPR00 FFFFF168H STIC0 STIF0 STMK0 STPR02 STPR01 STPR00...
Page 182: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. IMRm can be read/written in 16-bit units (m = 0 to 3).
Page 183: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 184: Maskable Interrupt Status Flag (Id)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. Initial value 00000020H Bit Position Bit Name...
Page 185: Interrupt Trigger Mode Selection
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.8 Interrupt trigger mode selection The valid edge of the INTPn, ADTRG0, ADTRG1, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11, TCLR3, and TI3 pins can be selected by program. The edge that can be selected as the valid edge is one of the following (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111).
Page 186 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Address Initial value INTM1 ES31 ES30 ES21 ES20 ES11 ES10 ES01 ES00 FFFFF882H INTP3/ADTRG1 INTP2/ADTRG0 INTP1 INTP0 Address Initial value INTM2 ES61 ES60 ES51 ES50 ES41 ES40 FFFFF884H INTP6 INTP5 INTP4 Bit Position Bit Name Function 7 to 0 ESn1, ESn0...
Page 187 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Signal edge selection registers 10, 11 (SESA10, SESA11) These registers specify the valid edge of external interrupt requests (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below.
Page 188 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) Address Initial value SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES1011 IES1010 IES1001 IES1000 FFFFF5EDH TIUD10, TCUD10 TCLR10 INTP101 INTP100 Address Initial value SESA11 TESUD11 TESUD10 CESUD11 CESUD10 IES1111 IES1110 IES1101 IES1100 FFFFF60DH TIUD11, TCUD11 TCLR11 INTP111 INTP110 Bit Position...
Page 189 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit Position Bit Name Function 3, 2 IES1n11, Specifies the valid edge of the pin selected using the CSLn bit of the CSL1n register IES1n10 (INTP1n1, INTP1n0). IES1n11 IES1n10 Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges 1, 0...
Page 190 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Valid edge selection register (SESC) This register specifies the valid edge for external interrupt requests (INTP30, INTP31, TCLR3, and TI3), input via external pins. The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges).
Page 191 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) These registers specify the valid edge for external interrupt requests input to timer 2 (INTP20 to INTP25). The correspondence between each register and the external interrupt request that register controls is shown below.
Page 192 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) Address Initial value FEM0 DFEN00 EDGE010 EDGE000 TMS010 TMS000 FFFFF630H INTP20 Address Initial value FEM1 DFEN01 EDGE011 EDGE001 TMS011 TMS001 FFFFF631H INTP21 Address Initial value FEM2 DFEN02 EDGE012 EDGE002 TMS012 TMS002 FFFFF632H INTP22 Address Initial value FEM3 DFEN03...
Page 193 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit Position Bit Name Function Note 1, 0 TMS01n, Selects the capture input TMS00n TMS01n TMS00n Operation Used as a pin Digital filter (noise eliminator specification) Timer-based capture to sub-channel 1 Timer-based capture to sub-channel 2 Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers.
Page 194: Software Exception
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 195: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 196: Exception Status Flag (Ep)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial value 00000020H Bit Position Bit Name...
Page 197: Exception Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/IA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 198 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 199: Debug Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation (1) Saves the restored PC to DBPC.
Page 200 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 201: Multiple Interrupt Servicing Control
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first.
Page 202: Interrupt Response Time
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 203 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline) 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 IFX IDX Interrupt acknowledgement operation INT1 INT2 INT3 INT4 Instruction (start instruction of interrupt servicing routine) Interleave Note access...
Page 204: Periods In Which Interrupts Are Not Acknowledged
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sampling instruction and the next instruction (interrupt is held pending). The interrupt request non-sampling instructions are as follows.
Page 205: Chapter 8 Clock Generation Function
CHAPTER 8 CLOCK GENERATION FUNCTION The clock generator (CG) generates and controls the internal system clock (f ) that is supplied to each internal unit, such as the CPU. 8.1 Features • Multiplier function using a phase locked loop (PLL) synthesizer •...
Page 206: Input Clock Selection
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3 Input Clock Selection The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 5.0 MHz crystal resonator or ceramic resonator to pins X1 and X2 enables a 50 MHz internal system clock (f ) to be generated when the multiplier is 10.
Page 207: Peripheral Command Register (Phcmd)
CHAPTER 8 CLOCK GENERATION FUNCTION (4 to 5 MHz) value for which 10 × × × × f Caution When using the PLL mode, only an f does not exceed the system clock maximum frequency (50 MHz) can be used for the oscillation frequency or external clock frequency.
Page 208: Clock Control Register (Ckc)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.4 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (f ) in PLL mode. It can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous program execution.
Page 209 CHAPTER 8 CLOCK GENERATION FUNCTION Data is set in the clock control register (CKC) according to the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1). <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3>...
Page 210: Peripheral Status Register (Phs)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Peripheral status register (PHS) If a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protection error is generated, setting the status flag (PRERR) to 1.
Page 211: Pll Lockup
CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called a lockup state, and the stabilized state is called a lock state.
Page 212: Power Save Control
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5 Power Save Control 8.5.1 Overview The power save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues.
Page 213 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 214 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1. Clock Generator Operation Using Power Save Control Clock Source Power Save Mode Oscillator Clock Clock Synthesizer Supply to Supply Peripheral to CPU √ √ √ √ PLL mode Oscillation with Normal operation resonator √...
Page 215: Control Registers
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.2 Control registers (1) Power save mode register (PSMR) This is an 8-bit register that controls power save mode. It is effective only when the STB bit of the PSC register is set to 1. Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation instruction (SET1/CLR1/NOT1 instruction).
Page 216 CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power save control register (PSC) This is an 8-bit register that controls the power save function. This register, which is one of the specific registers, is effective only when accessed by a specific sequence during a write operation. This register can be read/written in 8-bit or 1-bit units.
Page 217 CHAPTER 8 CLOCK GENERATION FUNCTION [Sample coding] <1> ST.B r11, PSMR [r0] ; Set PSMR register <2> MOV 0x07, r10 ; Prepare data for setting specific register in arbitrary general-purpose register <3> ST.B r10, PRCMD [r0] ; Write PRCMD register <4>...
Page 218: Halt Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.3 HALT mode (1) Setting and operation status In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU continues, operation continues.
Page 219 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTPn), or RESET pin input (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority.
Page 220: Idle Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.4 IDLE mode (1) Setting and operation status In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall system to stop. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator’s oscillation stabilization time or the PLL lockup time need not be secured.
Page 221 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request Note (INTPn) , or RESET pin input (n = 0 to 6, 20 to 25). Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the IDLE mode cannot be released.
Page 222: Software Stop Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.5 Software STOP mode (1) Setting and operation status In software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.5.2 Control registers).
Page 223 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of software STOP mode Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt Note request (INTPn) , or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s oscillation stabilization time must be secured (n = 0 to 6, 20 to 25).
Page 224: Securing Oscillation Stabilization Time
CHAPTER 8 CLOCK GENERATION FUNCTION 8.6 Securing Oscillation Stabilization Time 8.6.1 Oscillation stabilization time security specification Two specification methods can be used to secure the time from when software STOP mode is released until the stopped oscillator stabilizes. (1) Securing the time using an on-chip time base counter Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn).
Page 225: Time Base Counter (Tbc)
CHAPTER 8 CLOCK GENERATION FUNCTION (2) Securing the time according to the signal level width (RESET pin input) Software STOP mode is released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low level width of the signal that is input to the pin.
Page 226: Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1 Timer 0 9.1.1 Features (timer 0) Timers 00, 01 (TM00, TM01) are 16-bit timer/counters with a 3-phase PWM output function that have the following functions. • 3-phase PWM output function PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) •...
Page 227: Function Overview (Timer 0)
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1.2 Function overview (timer 0) • 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels • Compare registers: 4 registers × 2 channels • 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers × 2 channels •...
Page 228: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1.3 Basic configuration The basic configuration is shown below. Figure 9-1. Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) BFCMn3 INTCM0n3 CM0n3 INTTM0n TM0n Output control by external input (ESOn), 1/16 TM0n timer operation...
Page 229 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) BFCMn3 INTCM0n3 CM0n3 Clear Output control by TM0n external input (ESOn), TM0n timer operation 1/16 1/32 ALVTO DTRRn BFCMn0 CM0n0 Underflow DTMn0 TO0n0 (U phase) TO0n1...
Page 230 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timers 00, 01 (TM00, TM01) TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3 (CM0n3) (n = 0, 1). TM0n start/stop is controlled by the TM0CEn bit of timer control register 0n (TMC0n). Division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 231 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Dead-time timers 00 to 02, 10 to 12 (DTM00 to DTM02, DTM10 to DTM12) DTMn0 to DTMn2 are dedicated 12-bit down timers that generate dead time suitable for inverter control application. DTMn0 to DTMn2 operate as one-shot timers. Counting by a dead-time timer is enabled or disabled by the TM0CEDn bit of timer control register 0n (TMC0n) and cannot be controlled by software.
Page 232 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Compare registers 003, 013 (CM003, CM013) CM0n3 is a 16-bit register that always compare its value with the value of TM0n. If the values match, CM0n3 outputs an interrupt signal (INTCM0n3). CM0n3 controls the maximum count value of TM0n, and if the values match, it performs the following operations at the next timer count clock.
Page 233 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (7) Buffer registers CM03, CM13 (BFCM03, BFCM13) BFCMn3 is a 16-bit register that transfers data to the compare register at any timing. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register. BFCMn3 can be read/written in 16-bit units.
Page 234: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1.4 Control registers (1) Timer 0 clock selection register (PRM01) The PRM01 register is used to select the base clock (f ) of timer 0 (TM0n). It can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timer.
Page 235 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer control registers 00, 01 (TMC00, TMC01) TMC0n register is a 16-bit register that sets the operation of timer 0 (TM0n). The TMC0n register can be read/written in 16-bit units. If the higher 8 bits of the TMC0n register are used as the TMC0nH register and the lower 8 bits as the TMC0nL register, the register can be read/written in 8-bit or 1-bit units.
Page 236 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/4) Bit Position Bit Name Function 13 to 11 CUL02 to CUL00 Cautions 1. INTTM0n and INTCM0n3 interrupts can be culled with the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. Even when BFTE3 bit = 1, BFTEN bit = 1 (settings to transfer data from BFCMn0 to BFCMn3 registers to CM0n0 to CM0n3 registers), transfer is not performed with the generation timing of culled INTTM0n and INTCM0n3 interrupts if the MBFTE bit = 0.
Page 237 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3/4) Bit Position Bit Name Function BFTE3 Specifies transfer of data from BFCMn3 register to CM0n3 register. 0: Transfer disabled 1: Transfer enabled The transfer timing from the BFCMn3 register to the CM0n3 register is as follows. BFCMn3 →...
Page 238 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4/4) Bit Position Bit Name Function 1, 0 MOD01, Specifies the operation mode of TM0n. MOD00 BFCMn3 → Operation Mode TM0n Timer Clear BFCMn0 to BFCMn2 → Operation Source CM0n3 Timing CM0n0 to CM0n2 Timing −...
Page 239 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-5. Interrupt Culling Processing (a) PWM mode 0 (symmetric triangular wave) CM0n3 TM0n count value 0000H Interrupt request INTTM0n INTTM0n INTTM0n INTTM0n occurrence occurrence occurrence occurrence CUL02 to CUL00 Interrupt culling Interrupt culling 1/1 cycle 1/2 cycle Remark n = 0, 1...
Page 240 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-6. Interrupt Culling Ratio Change Timing (Relationship Between STINTn Bit Setting and CUL Bit Change): PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit CM0n3 TM0n count value 0000H INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n...
Page 241 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer unit control registers 00, 01 (TUC00, TUC01) TUC0n register is an 8-bit register that controls TO0n0 to TO0n5 outputs. TUC0n can be read/written in 8-bit or 1-bit units. However, bit 0 is read-only. <1>...
Page 242 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer output mode registers 0, 1 (TOMR0, TOMR1) The TOMRn register controls timer output from the TO0n0 to TO0n5 pins. To prevent abnormal output from pins TO0n0 to TO0n5 due to illegal access, data write to the TOMRn register consists of the following two sequences.
Page 243 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function ALVVB Specifies the output level of the TO0n3 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When the ALVVB bit = 1, the output level of the TO0n3 output is the same as TO0n2.
Page 244 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Examples of the output waveforms of TO000 and TO001 when the higher 4 bits (ALVTO, ALVUB, ALVVB, and ALVWB) of the TOMRn register are set in PWM mode 0 (symmetric triangular waves) are shown below. Figure 9-7.
Page 245 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-8. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (With Dead Time (TM0CED0 Bit = 0)) (a) TOMR0 register value = 80H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period...
Page 246 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Data setting to timer output mode registers 0, 1 (TOMR0, TOMR1) is done in the following sequence. <1> Prepare the data to be set to timer output mode registers 0, 1 (TOMR0, TOMR1) in a general-purpose register.
Page 247 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) PWM output enable registers 0, 1 (POER0, POER1) The POERn register is used to make the external pulse output (TO0n0 to TO0n5) status inactive by software. POERn can be read/written in 8-bit or 1-bit units. <5>...
Page 248 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) The PSTOn register is used to perform settings to output the desired waveforms to the external pulse output pins (TO0n0 to TO0n5) by software. PSTOn can be read/written in 8-bit or 1-bit units.
Page 249 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1/2) <7> <2> <1> <0> Address Initial value PSTO0 TORTO0 UPORT0 VPORT0 WPORT0 FFFFF57EH <7> <2> <1> <0> Address Initial value PSTO1 TORTO1 UPORT1 VPORT1 WPORT1 FFFFF5BEH Bit Position Bit Name Function TORTOn Specifies TO0n0 to TO0n5 output control.
Page 250 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function WPORTn Specifies the TO0n4 (W phase)/TO0n5 (W phase) pin output value. WPORTn Operation TO0n4 Inverted level of ALVTO bit setting TO0n5 When ALVWB = 0 Level of ALVTO bit setting When ALVWB = 1 Inverted level of ALVTO bit setting TO0n4...
Page 251 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-9. When UPORTn = 1 Is Set Immediately Before TORTOn = 0 (Switched by Active Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 1 Note 2 Note 2 Note 1 Note 2 Note 3 Note 4...
Page 252 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-10. When UPORTn = 0 Is Set Immediately Before TORTOn = 0 (Switched by Inactive Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 3 Note 1 Note 1 Note 2 Note 4 INTCM0n3...
Page 253 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-11. When UPORTn = 0 Is Set Immediately Before TORTOn = 1 CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 1 Note 1 Note 2 Note 1 Note 3 INTCM0n3 Note 4 INTTM0n...
Page 254 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-12. Software Output Waveforms of TO000 and TO001 (Without Dead Time (TM0CED0 = 1)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 (b) TOMR0 register value = 00H UPORT0 ←...
Page 255 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-13. Software Output Waveforms of TO000 and TO001 (With Dead Time (TM0CED0 = 0)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 Dead-time period Dead-time period (b) TOMR0 register value = 00H UPORT0 ←...
Page 256 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-14. Software Output Waveforms of TO000 and TO001 When “1” Is Written to UPORT0 Bit While TORTO0 = 1 (When TOMR0 Register Value = 80H) (a) Without dead time (TM0CED0 = 1) UPORT0 ←...
Page 257 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (7) TOMR write enable registers 0, 1 (SPEC0, SPEC1) The SPECn register enables write to the TOMRn register. Unless write to the TOMRn register is performed following immediately after write to the SPECn register (any data can be written), write processing to the TOMRn register is not performed normally.
Page 258: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1.5 Operation Remarks 1. In the description of the operation in 9.1.5, it is assumed that each bit that affects the output of TO0n0 to TO0n5 is set as follows. ALVTO = 1, ALVUB = 0, ALVVB = 0, ALVWB = 0, TORTOn = 0 2.
Page 259 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) [Setting procedure] (a) Set PWM mode 0 (symmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 260 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Operation] In PWM mode 0, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1).
Page 261 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Output waveform width in respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 −...
Page 262 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-15. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx CM0nx BFCMn3 CM0n3 Interrupt request INTCM0n3 INTTM0n INTCM0n3...
Page 263 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-16. Overall Operation Image of PWM Mode 0 (Symmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 CM0n1 CM0n1 TM0n CM0n0 CM0n0 CM0n0 CM0n0 count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time...
Page 264 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2 (BFCMn0 to BFCMn2) is shown. (a) When CM0nx (BFCMnx) ≥ ≥ ≥ ≥ CM0n3 is set Figure 9-17.
Page 265 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) When CM0nx (BFCMnx) = 0000H is set Figure 9-18. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx = 0000H) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCMnx 0000H...
Page 266 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value CM0nx CM0nx CM0nx CM0nx match match match match CM0nx match CM0nx match 0000H 0000H BFCM0nx 0000H 0000H CM0nx...
Page 267 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) PWM mode 1: Triangular wave modulation (right-left asymmetric waveform control) [Setting procedure] (a) Set PWM mode 1 (asymmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 268 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Operation] In PWM mode 1, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1).
Page 269 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Output waveform width in respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 −...
Page 270 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-20. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 (f) CM0n3 (g) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx CM0nx BFCMn3 CM0n3 Interrupt request INTCM0n3 INTTM0n INTCM0n3...
Page 271 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-21. Overall Operation Image of PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n1 CM0n1 CM0n0 CM0n0 count value CM0n0 CM0n0 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time...
Page 272 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (a) When BFCMnx ≥ ≥ ≥ ≥ CM0n3 is set in software processing started by INTCM0n3 Figure 9-22. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx ≥ ≥ ≥ ≥ CM0n3) CM0n3 CM0n3 TM0n...
Page 273 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) When BFCMnx > CM0n3 is set in software processing started by INTTM0n Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx...
Page 274 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-24. Change Timing from 100% Duty State (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCM0nx CM0nx Interrupt request INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3...
Page 275 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (c) When BFCMnx = 0000H is set in software processing started by INTCM0n3 Figure 9-25. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (1) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx...
Page 276 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx match match match match match 0000H 0000H 0000H 0000H BFCM0nx CM0nx 0000H 0000H 0000H 0000H...
Page 277 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (d) When BFCMnx = 0000H is set in software processing started by INTTM0n Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) CM0n3 CM0n3 TM0n count value 0000H CM0nx match...
Page 278 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-28. Change Timing from 100% Duty State (2) (PWM Mode 1) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match 0000H 0000H 0000H 0000H 0000H BFCM0nx CM0nx 0000H 0000H 0000H 0000H 0000H Interrupt request INTCM0n3...
Page 279 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (e) When BFCMnx = CM0n3 is set in software processing started by INTTM0n Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) CM0n3 CM0n3 count value 0000H CM0nx CM0nx match match...
Page 280 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) PWM mode 2: Sawtooth wave modulation [Setting procedure] (a) Set PWM mode 2 (sawtooth wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register. (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register.
Page 281 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Operation] In PWM mode 2, TM0n performs up count operation, and when it matches the value of CM0n3, match interrupt INTCM0n3 is generated and TM0n is cleared (n = 0, 1). The PWM cycle in this mode is ((BFCMn3 value + 1) × TM0n count clock). Concerning setting of data to CM0n3, the next PWM cycle width is set to BFCMn3.
Page 282 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) [Output waveform width in respect to set value] • PWM cycle = (BFCMn3 + 1) × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = (CM0nX + 1) ×...
Page 283 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx match match BFCMnx CM0nx BFCMn3 CM0n3 INTCM0n3 INTCM0n3 Interrupt request Set by rising edge of TM0CEn bit DTMnx Positive phase...
Page 284 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-31. Overall Operation Image of PWM Mode 2 (Sawtooth Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n0 CM0n0 count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output...
Page 285 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (a) When BFCMnx > CM0n3 is set Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx Interrupt request INTCM0n3 INTCM0n3 INTCM0n3...
Page 286 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCM0nx CM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Note DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase...
Page 287 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) When BFCMnx = CM0n3 is set Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx Interrupt request INTCM0n3 INTCM0n3 INTCM0n3...
Page 288 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (c) When BFCMnx = 0000H is set Figure 9-35. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match BFCMnx...
Page 289: Operation Timing
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1.6 Operation timing (1) TM0CEn bit write and TM0n timer operation timing Figure 9-36 shows the timing from write of the TM0CEn bit of the TMC0n register until the TM0n timer starts operating. Figure 9-36.
Page 290 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Interrupt generation timing The interrupt generation timing with the count clock setting (PRM02 to PRM00 bits of the TMC0n register) to TM0n in the various modes is described below. Figure 9-37. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (a) When count clock = f CM0n3...
Page 291 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-38. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave) (a) When count clock = f CM0n3 0002H TM0n 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H INTCM0n3 (b) When count clock = f 0002H...
Page 292 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Relationship between interrupt generation and STINTn bit of TMC0n register The interrupt generation timing for the setting of the STINTn bit of the TMC0n register and the interrupt culling ratio setting (bits CUL02 to CUL00) in the various modes is described below. If, to realize the INTTM0n and INTCM0n3 interrupt culling function for TM0n, bits CUL02 to CUL00 of the TMC0n register are set for a culling ratio other than 1/1, and count operation is started, the interrupt output order differs according to the setting of the STINTn bit when counting starts.
Page 293 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-40. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n...
Page 294 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-41. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/1 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 295 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-42. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 296 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) TO0n0 to TO0n5 output timing Figure 9-43. TO0n0 to TO0n5 Output Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit 0008H CM0n3 0003H CM0nx TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0002H...
Page 297 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-44. TO0n0 to TO0n5 Output Timing in PWM Mode 2 (Sawtooth Wave) TM0CEn bit 000AH CM0n3 CM0nx 0005H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0002H DTRRn DTMnx...
Page 298: Timer 1
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2 Timer 1 9.2.1 Features (timer 1) Timers 10, 11 (TM10, TM11) are 16-bit up/down counters that perform the following operations. • General-purpose timer mode Free-running timer PWM output • Up/down counter mode UDC mode A UDC mode B 9.2.2 Function overview (timer 1)
Page 299 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) • 2-phase encoder input The 2-phase encoder signal from external is used as the count clock of the timer counter with the external clock input pins (TIUD1n, TCUD1n). The counter mode can be selected from among the four following modes. •...
Page 300: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.3 Basic configuration The basic configuration is shown below. Table 9-4. Timer 1 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Interrupt Signal Note 1 Note 2 − − Timer 1 TM10 Read/write /16,...
Page 301 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-45. Block Diagram of Timer 1 Internal bus Edge INTP1n0/ detector CC1n0 Selector INTCC1n0 Note INTP1n1 Edge CC1n1 TM1UBDn Selector detector INTCC1n1 TCLR1n/ Edge TCLR INTP1n1 detector Clear TM1OVFn TM1UDFn TCUD1n/ Edge 1/2, 1/4, 1/8, 1/16, detector INTP1n0...
Page 302 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timers 10, 11 (TM10, TM11) TM1n is a 2-phase encoder input up/down counter and general-purpose timer. TM1n can be read/written in 16-bit units. Cautions 1. Write to TM1n is enabled only when the TM1CEn bit of the TMC1n register is “0” (count operation disabled).
Page 303 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Up/down counter mode (UDC mode) In the UDC mode, TM1n functions as a 16-bit up/down counter, counting based on the TCUD1n and TIUD1n input signals. Two operation modes can be set with the MSEL bit of the TUMn register for this mode. (i) UDC mode A (when CMD bit = 1, MSEL bit = 0) TM1n can be cleared by setting the CLR1 and CLR0 bits of the TMC1n register.
Page 304 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Compare registers 100, 110 (CM100, CM110) CM1n0 is a 16-bit register that always compares its value with the value of TM1n. When the value of a compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing in the various modes is described below.
Page 305 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Capture/compare registers 100, 110 (CC100, CC110) CC1n0 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n0 can be read/written in 16-bit units. Cautions 1.
Page 306 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Capture/compare registers 101, 111 (CC101, CC111) CC1n1 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n1 can be read/written in 16-bit units. Cautions 1.
Page 307: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 (TM1n) and timer 2 (TM2n). This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timers 1 and 2.
Page 308 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer unit mode registers 0, 1 (TUM0, TUM1) The TUMn register is an 8-bit register used to specify the TM1n operation mode or to control the operation of the PWM output pin. TUMn can be read/written in 8-bit or 1-bit units.
Page 309 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer control registers 10, 11 (TMC10, TMC11) The TMC1n register is used to enable/disable TM1n operation and to set transfer and timer clear operations. TMC1n can be read/written in 8-bit or 1-bit units. Caution Changing the value of bits of the TMC1n register other than the TM1CEn bit during TM1n operation (TM1CEn bit = 1) is prohibited.
Page 310 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 1, 0 CLR1, CLR0 Controls TM1n clear operation in UDC mode A. CLR1 CLR0 Specify TM1n Clear Source Clear only by external input (TCLR1n) Clear upon match of TM1n count value and CM1n0 set value Clear by TCLR1n input or upon match of TM1n count value and CM1n0 set value...
Page 311 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Capture/compare control registers 0, 1 (CCR0, CCR1) The CCRn register specifies the operation mode of the capture/compare registers (CC1n0, CC1n1). CCRn can be read/written in 8-bit or 1-bit units. Caution Overwriting the CCRn register during TM1n operation (TM1CEn bit = 1) is prohibited. Address Initial value CCR0...
Page 312 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Signal edge selection registers 10, 11 (SESA10, SESA11) The SESA1n register is used to specify the valid edge of external interrupt requests from external pins (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11). The correspondences between each register and the external interrupt requests it controls are as follows.
Page 313 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 5, 4 CESUDn1, Specifies valid edge of pins TCLR10, TCLR11. CESUDn0 CESUDn1 CESUDn0 Valid Edge Falling edge Rising edge Low level High level The set values of bits CESUDn1 and CESUDn0 and the TM1n operation are related as follows.
Page 314 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (6) Prescaler mode registers 10, 11 (PRM10, PRM11) The PRM1n register is used to perform the following selections. • Selection of count clock in the general-purpose timer mode (CMD bit of TUMn register = 0) •...
Page 315 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (a) In general-purpose timer mode (CMD bit of TUMn register = 0) The count clock is fixed to the internal clock. The clock rate of TM1n is specified with bits PRM12 to PRM10. (b) UDC mode (CMD bit of TUMn register = 1) The TM1n count sources in the UDC mode are as follows.
Page 316 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (7) Status registers 0, 1 (STATUS0, STATUS1) The STATUSn register indicates the operating status of TM1n. STATUSn is read-only in 8-bit or 1-bit units. Caution Overwriting the STATUSn register during TM1n operation (TM1CEn bit = 1) is prohibited. <2>...
Page 317 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (8) CC101 capture input selection register (CSL10) The CSL10 register specifies capture input that is input to TM10. CSL10 can be read/written in 8-bit or 1-bit units. Address Initial value CSL10 CSL0 FFFFF5F6H Bit Position Bit Name Function...
Page 318: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.5 Operation (1) Basic operation The following two operation modes can be selected for TM1n (n = 0, 1). (a) General-purpose timer mode (CMD bit of TUMn register = 0) In the general-purpose timer mode, the TM1n operates either as a 16-bit interval timer or as a PWM output timer (count operation is up count only).
Page 319 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Operation in general-purpose timer mode TM1n can perform the following operations in the general-purpose timer mode. (a) Interval operation TM1n and CM1n0 always compare their values and the INTCM1n0 interrupt is generated upon occurrence of a match.
Page 320 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (d) Capture function TM1n connects two capture/compare register (CC1n0, CC1n1) channels. When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in synchronization with the corresponding capture trigger signal. Furthermore, an interrupt request (INTCC1n0, INTCC1n1) is generated by the INTP1n0, INTP1n1 input signals.
Page 321 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-46. TM1n Block Diagram (During PWM Output Operation) INTCM1n0 Clear TM1n (16 bits) ALVT10 TUMn register /128 Compare register (CM1n0) TO1n Compare register INTCM1n1 (CM1n1) Caution Be sure to set the count clock of TM1n to 8 MHz or lower. Remarks 1.
Page 322 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Operation in UDC mode (a) Overview of operation in UDC mode The count clock input to TM1n in the UDC mode (CMD bit of TUMn register = 1) can only be external input from the TIUD1n and TCUD1n pins.
Page 323 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Up/down count operation in UDC mode TM1n up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting. (i) Mode 1 (PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin.
Page 324 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-49. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TM1n 0007H 0006H 0005H 0004H 0005H 0006H 0007H Down count Up count...
Page 325 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (iii) Mode 3 (PRM12 = 1, PRM11 = 1, PRM10 = 0) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1n and TCUD1n pins, the level of the TCUD1n pin is sampled at the input of the valid edge of the TIUD1n pin (refer to Figure 9-51).
Page 326 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (iv) Mode 4 (PRM12 = 1, PRM11 = 1, PRM10 = 1) In mode 4, when two signals out of phase are input to the TIUD1n and TCUD1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 9-53.
Page 327 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (c) Operation in UDC mode A (i) Interval operation The operations at the count clock following match of the TM1n count value and the CM1n0 set value are as follows. • In case of up count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated. •...
Page 328 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (iii) Compare function TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TM1n count value and the set value of one of the compare registers match, a match Note Note interrupt (INTCM1n0, INTCM1n1, INTCC1n0...
Page 329 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (d) Operation in UDC mode B (i) Basic operation The operations at the next count clock after the count value of TM1n and the CM1n0 set value match when TM1n is in UDC mode B are as follows. •...
Page 330: Supplementary Description Of Internal Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.6 Supplementary description of internal operation (1) Clearing of count value in UDC mode B When TM1n is in UDC mode B, the count value clear operation is as follows. • In case of TM1n up count operation: TM1n is cleared upon match with CM1n0 •...
Page 331 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Clearing of count value upon occurrence of compare match The internal operation during TM1n clear operation upon occurrence of a compare match is as follows. Figure 9-58. Count Value Clear Operation upon Compare Match Clear TM1n (Not clear TM1n) Count clock...
Page 332 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Transfer operation The internal operation during TM1n transfer operation is as follows. Figure 9-59. Internal Operation During Transfer Operation Transfer operation is performed. (Transfer operation is not performed.) Count clock (rising edge set as valid edge) FFFFH FFFEH TM1n...
Page 333 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Interrupt signal output upon compare match An interrupt signal is output when the count value of TM1n matches the set value of the CM1n0, CM1n1, Note Note CC1n0 , or CC1n1 register. The interrupt generation timing is as follows. Note When CC1n0 and CC1n1 are set to the compare register mode.
Page 334: Timer 2
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.3 Timer 2 9.3.1 Features (timer 2) Timers 20, 21 (TM20, TM21) are 16-bit general-purpose timer units that perform the following operations. • Pulse interval or frequency measurement and programmable pulse output • Interval timer •...
Page 335 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) • Interrupt request sources • Compare-match interrupt request: 6 types Perform comparison with sub-channel n capture/compare register and generate the INTCC2n interrupt upon compare match. • Timer/counter overflow interrupt request: 2 types The INTTM20 (INTTM21) interrupt is generated when the count value of TM20 (TM21) becomes FFFFH. •...
Page 336: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.3.3 Basic configuration The basic configuration is shown below. Table 9-8. Timer 2 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Other Functions Interrupt Signal Note 1 Note 2 − − Timer 2 TM20 INTTM20...
Page 337 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) The following shows the capture/compare operation sources. Table 9-9. Capture/Compare Operation Sources Register Sub-channel Timer to Be Captured Timer to Be Compared Timer Captured in 32-Bit Cascade Connection − CVSE00 TM20 TM20 CVPEn0 TM21 when BFEEy bit of TM20 when TB1Ey, TB0Ey TM21...
Page 338 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-62. Block Diagram of Timer 2 ECLR 1/2, 1/4, 1/8, CNT = MAX. INTTM20 1/16, 1/32, TCOUNTE0 TM20 1/64, 1/128 edge selection CNT = 0 (16-bit) TCOUNTE1 edge selection INTCC20 TI2/ Input filter TINE0 INTP20 edge selection...
Page 339 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Table 9-11. Meaning of Signals in Block Diagram Signal Name Meaning Note 1 CASC TM21 count signal input in 32-bit mode Count value of timer 2 (CNT = MAX.: Maximum value count signal output of timer 2 (generated when TM2n = FFFFH), CNT = 0: Zero count signal output of timer 2 (generated when TM2n = 0000H)) TM2n count signal input in 16-bit mode...
Page 340 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timers 20, 21 (TM20, TM21) The features of TM2n are listed below. • Free-running counter that enables counter clearing by compare match of sub-channel 0 and sub-channel 5 • Can be used as a 32-bit capture timer when TM20 and TM21 are connected in cascade. •...
Page 341 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4) The CVPEn0 register is a sub-channel n 16-bit main capture/compare register. In the capture register mode, this register captures the value of TM21 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34).
Page 342 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer 2 sub-channel n sub capture/compare register (CVSEn0) (n = 1 to 4) The CVSEn0 register is a sub-channel n 16-bit sub capture/compare register. In the compare register mode, this register can be used as a buffer. In the capture register mode, this register captures the value of TM20 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34).
Page 343: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.3.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 and timer 2. This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using timer 1 and timer 2.
Page 344 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer 2 count clock/control edge selection register 0 (CSE0) The CSE0 register is used to specify the TM2n count clock and the control valid edge (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the CSE0 register are used as the CSE0H register, and the lower 8 bits are used as the CSE0L register, they can be read/written in 8-bit or 1-bit units.
Page 345 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer 2 sub-channel input event edge selection register 0 (SESE0) The SESE0 register specifies the valid edge of the external capture signal input (TINEn) for the sub-channel n capture/compare register performing capture (n = 0 to 5). This register can be read/written in 16-bit units.
Page 346 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Timer 2 time base control register 0 (TCRE0) The TCRE0 register controls the operation of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TCRE0 register are used as the TCRE0H register, and the lower 8 bits are used as the TCRE0L register, they can be read/written in 8-bit or 1-bit units.
Page 347 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1/2) <14> <13> <6> <5> Address Initial value TCRE0 CASE1 CLRE1 CEE1 ECRE1 ECEE1 OSTE1 UDSE11 UDSE10 CLRE0 CEE0 ECRE0 ECEE0 OSTE0 UDSE01 UDSE00 FFFFF646H 0000H Bit Position Bit Name Function CASE1 Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of TM20 (carry count)).
Page 348 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 11, 3 ECEEn Specifies TM2n count operation enable/disable through ECLR signal input. 0: TM2n count operation not enabled 1: TM2n count operation enabled Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n count operation using ECLR signal input is not performed.
Page 349 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (6) Timer 2 output control register 0 (OCTLE0) The OCTLE0 register controls timer output from the TO2n pin (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the OCTLE0 register are used as the OCTLE0H register, and the lower 8 bits are used as the OCTLE0L register, they can be read/written in 8-bit or 1-bit units.
Page 350 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (7) Timer 2 sub-channel 0, 5 capture/compare control register (CMSE050) The CMSE050 register controls timer 2 sub-channel 0 capture/compare register (CVSE00) and timer 2 sub- channel 5 capture/compare register (CVSE50). This register can be read/written in 16-bit units. Address Initial value CMSE050...
Page 351 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (8) Timer 2 sub-channel 1, 2 capture/compare control register (CMSE120) The CMSE120 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1, 2). This register can be read/written in 16-bit units.
Page 352 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En).
Page 353 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (9) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340) The CMSE340 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 3, 4). This register can be read/written in 16-bit units.
Page 354 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En).
Page 355 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (10) Timer 2 time base status register 0 (TBSTATE0) The TBSTATE0 register indicates the status of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TBSTATE0 register are used as the TBSTATE0H register, and the lower 8 bits are used as the TBSTATE0L register, they can be read/written in 8-bit or 1-bit units.
Page 356 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) The CCSTATE0 register indicates the status of the timer 2 sub-channel sub capture/compare register (CVSEn0) and the timer 2 sub-channel main capture/compare register (CVPEn0) (n = 1 to 4). This register can be read/written in 16-bit units.
Page 357 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (12) Timer 2 output delay register 0 (ODELE0) The ODELE0 register sets the output delay operation synchronized with the clock to the TO2n pin’s output delay circuit (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the ODELE0 register are used as the ODELE0H register, and the lower 8 bits are used as the ODELE0L register, they can be read/written in 8-bit or 1-bit units.
Page 358 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (13) Timer 2 software event capture register (CSCE0) The CSCE0 register sets capture operation by software in the capture register mode. This register can be read/written in 16-bit units. Address Initial value CSCE0 SEVE5 SEVE4 SEVE3...
Page 359: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.3.5 Operation (1) Edge detection The edge detection timing is shown below. Figure 9-63. Edge Detection Timing Note TINEx, TCLR2, TCOUNTEn MUXTB0 ED1, ED2 ECLR Note The set values of the TESnE1, TESnE0 bits and the CESE1, CESE0 bits of the CSE0 register, and the IESEx1, IESEx0 bits of the SESE0 register are shown.
Page 360 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Basic operation of timer 2 Figures 9-64 to 9-67 show the basic operation of timer 2. Figure 9-64. Timer 2 Up Count Timing (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, CASE1 Bit = 0) Note 1 OSTEn bit Note 1...
Page 361 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-65. External Control Timing of Timer 2 (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note ECEEn bit Note ECREn bit Note CLREn bit ECLR...
Page 362 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-66. Operation in Timer 2 Up/Down Count Mode (When TCRE0 Register’s ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note 1 UDSEn1, UDSEn0 bits don't care...
Page 363 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-67. Timing in 32-Bit Cascade Operation Mode (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 1) Note CASC...
Page 364 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Operation of capture/compare register (sub-channels 1 to 4) Sub-channels 1 to 4 receive the count value of the timer 2 multiplex count generator. The multiplex count generator is an internal unit of TM2n that supplies the multiplex count value MUXCNT to sub-channels 1 to 4.
Page 365 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-69. Multiplex Count Timing CNT (0) FFFEH FFFFH 0000H 0001H 1234H 1235H CNT (1) MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H 1235H 0001H 1235H...
Page 366 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-70. Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, and CMSEx0 Register’s CCSEy Bit = 0, BFEEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1 MUXCNT...
Page 367 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Note 1 Figure 9-71. Capture Operation: Mode with 16-Bit Buffer (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1...
Page 368 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-72. Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register’s TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) TCOUNTE0 = TCOUNTE1...
Page 369 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-73. Capture Operation: Capture Control by Software and Trigger Timing (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT...
Page 370 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-74. Compare Operation: Buffer-Less Mode (When CMSEx0 Register’s CCSEy Bit = 1, LNKEy Bit = Arbitrary, BFEEy Bit = 0) MUXTB0 MUXTB1 MUXCNT Note 1 TB0Ey bit Note 1 TB1Ey bit WRITE_ENABLE_S RELOAD_PRIMARY CVSEm0 register CVPEm0 register...
Page 371 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-75. Compare Operation: Mode with Buffer (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, CMSEx0 Register’s CCSEy Bit = 1, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT Note LNKEy bit WRITE_ENABLE_S RELOAD2A...
Page 372 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Operation of capture/compare register (sub-channels 0, 5) Figures 9-76 and 9-77 show the operation of the capture/compare register (sub-channels 0, 5). Figure 9-76. Capture Operation: Timer 2 Count Value Read Timing (When CMSE050 Register’s CCSEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) Note 1 LNKEy...
Page 373 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-77. Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE050 Register’s CCSEy Bit = 1, EEVEy Bit = Arbitrary, and CSCE0 Register’s SEVEy Bit = Arbitrary) CPU write C/C CVSEy0 register MATCH Note 1...
Page 374 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Operation of output circuit Figures 9-78 to 9-81 show the output circuit operation. Figure 9-78. Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits...
Page 375 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-79. Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits TO2n timer output Note 2 (ALVEn bit = 0...
Page 376 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-81. Signal Output Operation: During Delay Output Operation (When OCTLE0 Register’s OTMEn1, OTMEn0 Bits = 0, ALVEn = 0, SWFEn Bit = 0) Note ODELEn2 to ODELEn0 bits TO2n timer output Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1.
Page 377: Timer 3
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4 Timer 3 9.4.1 Features (timer 3) Timer 3 (TM3) is a 16-bit timer/counter that can perform the following operations. • Interval timer function • PWM output • External signal cycle measurement 9.4.2 Function overview (timer 3) •...
Page 378: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.3 Basic configuration Table 9-12. Timer 3 Configuration List Timer Count Clock Register Read/Write Generated Capture Timer Output Interrupt Trigger Note 1 Note 2 Signal − − Timer 3 Read INTTM3 /16, CC30 Read/write INTCC30 INTP30...
Page 379 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timer 3 (TM3) TM3 functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TM3 can be used as pulse output. TM3 is read-only in 16-bit units.
Page 380 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Selection of the internal count clock TM3 operates as a free-running timer. When an internal clock is specified as a count clock by timer control register 31 (TMC31), TM3 is counted up for each input clock cycle specified by the CS2 to CS0 bits of the TMC30 register. A division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 381 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Capture/compare registers 30 and 31 (CC30 and CC31) These capture/compare registers 30 and 31 are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 and CMS0 bit specifications of timer control register 31 (TMC31).
Page 382 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Setting these registers to compare registers (CMS1 and CMS0 of TMC31 = 1) When these registers are set to compare registers, the TM3 and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLR bit of timer control register 31 (TMC31) is set (1), the TM3 value is cleared (0) at the same time as a match with the CC30 register (it is not cleared (0) by a match with the CC31 register).
Page 383: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.4 Control registers (1) Timer 3 clock selection register (PRM03) The PRM03 register is used to select the base clock (f ) of timer 3 (TM3). This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 384 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer control register 30 (TMC30) The TMC30 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. The TM3CAE bit and other bits cannot be set at the same time. Be sure to set the TM3CAE bit and then set the other bits and the other registers of TM3.
Page 385 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit Position Bit Name Function 6 to 4 CS2 to CS0 Selects the internal count clock for TM3. Count Clock /128 /256 Caution Do not change the CS2 to CS0 bits during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit to “0”.
Page 386 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer control register 31 (TMC31) The TMC31 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the bits of the TMC31 register during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit of the TMC30 register to “0”.
Page 387 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Address Initial value TMC31 ENT1 CCLR ECLR CMS1 CMS0 FFFFF688H Bit Position Bit Name Function Sets the operation when TM3 overflows. 0: Continue count operation after overflow (free-running mode) 1: After overflow, timer holds 0000H and stops count operation (overflow stop mode).
Page 388 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Valid edge selection register (SESC) This register specifies the valid edge of external interrupt requests (TI3, TCLR3, INTP30, INTP31) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 389: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.5 Operation (1) Count operation Timer 3 can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer control register 3n (TMC3n) (n = 0, 1). When it operates as a free-running timer, if the CC30 or CC31 register and the TM3 count value match, an interrupt signal is generated and the timer output signal (TO3) can be set or reset.
Page 390 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Overflow When the TM3 register has counted the count clock from FFFFH to 0000H, the TM3OVF bit of the TMC30 register is set (1), and an overflow interrupt (INTTM3) is generated at the same time. However, if the CC30 register is set to compare mode (CMS0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLR bit = 1), then the TM3 register is considered to be cleared and the TM3OVF bit is not set (1) when the TM3 register changes from FFFFH to 0000H.
Page 391 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Capture operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 392 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-87. TM3 Capture Operation Example (When Both Edges Are Specified) (TM3 count values) ∆ ∆ Count start Overflow TM3CE ← 1 TM3OVF ← 1 Interrupt request (INTP31) Capture register (CC31) Remark D0 to D2: TM3 count values User’s Manual U14492EJ3V0UD...
Page 393 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Compare operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 394 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-88. Compare Operation Example (2/2) (b) If CCLR bit = 1 and CC30 is 0000H Count up FFFFH 0000H 0000H 0001H Compare register 0000H (CC30) INTTM3 Match detection (INTCC30) Remark The match is detected immediately after the count up, and the match detection signal is generated.
Page 395 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) External pulse output Timer 3 has one timer output pin (TO3). An external pulse output (TO3) is generated when a match of the two compare registers (CC30 and CC31) and the TM3 register is detected. If a match is detected when the TM3 count value and the CC30 value are compared, the output level of the TO3 pin is set.
Page 396: Application Examples
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.6 Application examples (1) Interval timer By setting the TMC30 and TMC31 registers as shown in Figure 9-90, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the CC30 register as the interval.
Page 397 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-91. Interval Timer Operation Timing Example Count clock TM3 register 0000H 0001H 0000H 0001H 0000H 0001H Count start Clear Clear CC30 register INTCC30 interrupt Interval time Interval time Interval time Remark p: Setting value of CC30 register (0000H to FFFFH) Count clock cycle Interval time = (p + 1) ×...
Page 398 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) PWM output By setting the TMC30 and TMC31 registers as shown in Figure 9-92, timer 3 can output a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register with the values that were set in advance in the CC30 and CC31 registers as the intervals.
Page 399 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-93. PWM Output Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt (output) Remarks 1. p: Setting value of CC30 register (0000H to FFFFH) q: Setting value of CC31 register (0000H to FFFFH) p ≠...
Page 400 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Cycle measurement By setting the TMC30 and TMC31 registers as shown in Figure 9-94, timer 3 can measure the cycle of signals input to the INTP30 pin or INTP31 pin. The valid edge of the INTP30 pin is selected according to the IES301 and IES300 bits of the SESC register, and the valid edge of the INTP31 pin is selected according to the IES311 and IES310 bits of the SESC register.
Page 401 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-95. Cycle Measurement Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear INTP30 (input) CC30 register INTCC30 interrupt INTTM3 interrupt (D1 – D0) × t {(10000H – D1) + D2} × t (D3 –...
Page 402: Precautions
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.7 Precautions Various precautions concerning timer 3 are shown below. (1) If a conflict occurs between the reading of the CC30 register and a capture operation when the CC30 register is used in capture mode, an external trigger (INTP30) valid edge is detected and an external interrupt request signal (INTCC30) is generated however, the timer value is not stored in the CC30 register.
Page 403: Timer 4
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5 Timer 4 9.5.1 Features (timer 4) Timer 4 (TM4) functions as a 16-bit interval timer. 9.5.2 Function overview (timer 4) • 16-bit interval timer: 1 channel • Compare register: 1 • Count clock selected from divisions of internal system clock (set the frequency of the count clock to 16 MHz or less) •...
Page 404: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5.3 Basic configuration Table 9-14. Timer 4 Configuration List Timer Count Clock Register Read/Write Generated Capture Timer Output Other Interrupt Trigger Functions Signal − − − − Timer 4 /4, f /8, f /16, f /32, Read...
Page 405 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timer 4 (TM4) TM4 is a 16-bit timer. It is mainly used as an interval timer for software. Starting and stopping TM4 is controlled by the TM4CE0 bit of the timer control register 4 (TMC4). A division by the prescaler can be selected for the count clock from among f /4, f /8, f...
Page 406 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Compare register 4 (CM4) CM4 and the TM4 register count value are compared, and an interrupt request signal (INTCM4) is generated when a match occurs. TM4 is cleared, synchronized with this match. If the TM4CAE0 bit of the TMC4 register is set to 0, a reset is performed asynchronously, and the registers are initialized.
Page 407 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-97. Example of Timing During TM4 Operation (a) When TM4 < < < < CM4 TM4CAE0 TM4CE0 INTCM4 Remark M = TM4 value when overwritten N = CM4 value when overwritten M < N (b) When TM4 >...
Page 408: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5.4 Control register (1) Timer control register 4 (TMC4) The TMC4 register controls the operation of timer 4. This register can be read/written in 8-bit or 1-bit units. Caution The TM4CAE0 bit and other bits cannot be set at the same time. Be sure to set the TM4CAE0 bit and then set the other bits and the other registers of TM4.
Page 409: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5.5 Operation (1) Compare operation TM4 can be used for a compare operation in which the value that was set in a compare register (CM4) is compared with the TM4 count value. If a match is detected by the compare operation, an interrupt (INTCM4) is generated. The generation of the interrupt causes TM4 to be cleared (0) at the next count timing.
Page 410 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-98. TM4 Compare Operation Example (2/2) (b) When CM4 is set to 0 Count clock Count up TM4 clear Clear FFFFH Match detection (INTCM4) Overflow Interval time = (FFFFH + 2) × Count clock cycle Remark User’s Manual U14492EJ3V0UD...
Page 411: Application Example
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5.6 Application example (1) Interval timer This section explains an example in which timer 4 is used as an interval timer with 16-bit precision. Interrupt requests (INTCM4) are output at equal intervals (refer to Figure 9-98 TM4 Compare Operation Example).
Page 412: Timer Connection Function
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.6 Timer Connection Function 9.6.1 Overview The V850E/IA1 provides a function to connect timer 1 and timer 2. Figure 9-99. Block Diagram of Timer Connection Function Timer connection selector Timer 2 Capture 0 CVSE10/ CVPE10 Capture 1...
Page 413: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.6.2 Control register (1) Timer connection selection register 0 (TMIC0) The TMIC0 register enables/disables input of the INTCM100, INTCM101 signals to the CVSEn0/CVPEn0 registers (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Address Initial value TMIC0...
Page 414: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features The serial interface function provides three types of serial interfaces combining a total of six transmit/receive channels. All six channels can be used simultaneously. The three interface formats are as follows. (1) Asynchronous serial interfaces (UART0 to UART2): 3 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels (3) FCAN controller: 1 channel Remark...
Page 415: Asynchronous Serial Interface 0 (Uart0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interface 0 (UART0) 10.2.1 Features • Transfer rate: 300 bps to 1562.5 Kbps (using a dedicated baud rate generator and an internal system clock of 50 MHz) • Full-duplex communications On-chip reception buffer register 0 (RXB0) On-chip transmission buffer register 0 (TXB0) •...
Page 416: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UART0 is controlled by the asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and asynchronous serial interface transmission status register 0 (ASIF0). Receive data is maintained in the reception buffer register 0 (RXB0), and transmit data is written to the transmission buffer register 0 (TXB0).
Page 417 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Transmission buffer register 0 (TXB0) TXB0 is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXB0. The transmission completion interrupt request (INTST0) is generated synchronized with the completion of transmission of one frame.
Page 418: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) Asynchronous serial interface mode register 0 (ASIM0) The ASIM0 register is an 8-bit register that controls the UART0 transfer operation. This register can be read/written in 8-bit or 1-bit units. Caution When using UART0, be sure to set the external pins related to the UART0 function to the control mode before setting clock selection register 0 (CKSR0) and baud rate generator control register 0 (BRGC0), and then set the UARTCAE0 bit to 1.
Page 419 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit Position Bit Name Function RXE0 Enables/disables reception. 0: Disable reception 1: Enable reception Cautions 1. Set the RXE0 bit to 1 after setting the UARTCAE0 bit to 1 at startup. Set the UARTCAE0 bit to 0 after setting the RXE0 bit to 0 to stop.
Page 420 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit Position Bit Name Function • 0 parity 4, 3 PS1, PS0 During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. •...
Page 421 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register 0 (ASIS0) The ASIS0 register, which consists of 3-bit error flags (PE, FE, and OVE), indicates the error status when UART0 reception is completed. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 422 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmission status register 0 (ASIF0) The ASIF0 register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXB0 register after data is transferred from the TXB0 register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 423 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception buffer register 0 (RXB0) The RXB0 register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. When reception is enabled (RXE0 bit = 1 in the ASIM0 register), receive data is transferred from the reception shift register to the RXB0 register, synchronized with the completion of the shift-in processing of one frame.
Page 424 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transmission buffer register 0 (TXB0) The TXB0 register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE0 bit = 1 in the ASIM0 register), the transmit operation is started by writing data to TXB0 register.
Page 425: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0. • Reception error interrupt (INTSER0) • Reception completion interrupt (INTSR0) • Transmission completion interrupt (INTST0) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 426: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 10-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asynchronous serial interface mode register 0 (ASIM0).
Page 427 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation When UARTCAE0 bit is set to 1 in the ASIM0 register, a high level is output from the TXD0 pin. Then, when TXE0 bit is set to 1 in the ASIM0 register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register 0 (TXB0).
Page 428 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXD0 (output) Parity Stop INTST0 (output) (b) Stop bit length: 2 Stop Parity TXD0 (output) Start INTST0 (output) User’s Manual U14492EJ3V0UD...
Page 429 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UART0 can write the next transmit data to the TXB0 register at the timing that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTST0 interrupt service after the transmission of one data frame.
Page 430 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-4. Continuous Transmission Processing Flow Set registers Write transmit data to TXB0 register When reading ASIF0 register, TXBF0 = 0? Interrupt occurrence Required number of transfers performed? When reading When reading ASIF0 register, ASIF0 register, TXSF0 = 0? TXSF0 = 1? Write transmit data to...
Page 431 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure to start continuous transmission is shown below. Figure 10-5. Continuous Transmission Starting Procedure Start Start Stop Stop TXD0 (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTST0 (output) TXB0 register Data (1) Data (2)
Page 432 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 10-6. Continuous Transmission End Procedure Start Start Stop Stop TXD0 (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10> <11>...
Page 433 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation An awaiting reception state is set by setting UARTCAE0 bit to 1 in the ASIM0 register and then setting RXE0 bit to 1 in the ASIM0 register. To start a receive operation, detect a start bit first. The start bit is detected by sampling RXD0 pin.
Page 434 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Asynchronous Serial Interface Reception Completion Interrupt Timing Start RXD0 (input) Parity Stop INTSR0 (output) RXB0 register Cautions 1. Even if a reception error occurs, be sure to read reception buffer register 0 (RXB0). If RXB0 is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely.
Page 435 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSR0 interrupt and generated as an INTSER0 interrupt by clearing the ISRM bit of the ASIM0 register to 0. Figure 10-8. When Reception Error Interrupt Is Separated from INTSR0 Interrupt (ISRM Bit = 0) (a) No error occurs during reception (b) An error occurs during reception INTSR0 (output)
Page 436 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 437 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXD0 signal is sampled at the rising edge of the prescaler output base clock. If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 10-11).
Page 438: Dedicated Baud Rate Generator 0 (Brg0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.6 Dedicated baud rate generator 0 (BRG0) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UART0. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 439 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers. The base clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSR0 register. The 8-bit counter divisor value can be set according to the MDL7 to MDL0 bits of the BRGC0 register.
Page 440 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate generator control register 0 (BRGC0) The BRGC0 register is an 8-bit register that controls the baud rate (serial transfer speed) of UART0. This register can be read/written in 8-bit units. Caution If the MDL7 to MDL0 bits are to be overwritten, the TXE0 bit and RXE0 bit of the ASIM0 register should be set to 0 first.
Page 441 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained according to the following formula. Baud rate = [bps] 2 × k = Frequency [Hz] of base clock selected according to TPS3 to TPS0 bits of CKSR0 register k = Value set according to MDL7 to MDL0 bits of BRGC0 register (k = 8, 9, 10, ..., 255) (d) Baud rate error The baud rate error is obtained according to the following formula.
Page 442 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 10-3. Baud Rate Generator Setting Data = 50 MHz = 40 MHz = 33 MHz = 10 MHz Baud Rate (bps) 0.15 0.16 –0.07 0.16 0.15 0.16 –0.07 0.16 1200 0.15 0.16...
Page 443 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 444 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum baud rate (BRmax) that can be received is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. −...
Page 445: Precautions
CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 446: Asynchronous Serial Interfaces 1, 2 (Uart1, Uart2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Asynchronous Serial Interfaces 1, 2 (UART1, UART2) 10.3.1 Features • Clocked (synchronous) mode/asynchronous mode can be selected • Operation clock Synchronous mode: Baud rate generator/external clock selectable Asynchronous mode: Baud rate generator • Transfer rate 600 bps to 153600 bps (in asynchronous mode, f = 50 MHz) •...
Page 447: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 Configuration UART1 and UART2 are controlled by asynchronous serial interface mode registers 10, 11, 20, and 21 (ASIM10, ASIM11, ASIM20, ASIM21) and asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2). Receive data is held in the reception buffer registers (RXB1, RXBL1, RXB2, RXBL2), and transmit data is held in the transmission shift registers (TXS1, TXSL1, TXS2, TXSL2).
Page 448 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-15. Block Diagram of Asynchronous Serial Interfaces 1, 2 Internal bus PEn FEn OVEn Asynchronous Asynchronous Reception buffers n, Ln serial interface mode serial interface status (RXBn, RXBLn) registers n0, n1 register n (ASIMn0, ASIMn1) (ASISn) Transmission Reception...
Page 449: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers (1) Asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20) The ASIMn0 register is an 8-bit register that controls the UART1, UART2 transfer operation (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 450 CHAPTER 10 SERIAL INTERFACE FUNCTION <6> Address Initial value ASIM10 RXE1 SCLS FFFFFA28H <6> Address Initial value ASIM20 RXE2 SCLS FFFFFA48H Bit Position Bit Name Function RXEn Enables/disables reception. 0: Disable reception 1: Enable reception 5, 4 PS1, PS0 Specifies parity bit length. Operation No parity, extension bit operation 0 parity...
Page 451 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode registers 11, 21 (ASIM11, ASIM21) The ASIMn1 register is an 8-bit register that controls the UART1 and UART2 transfer modes. This register can be read/written in 8-bit or 1-bit units. Address Initial value ASIM11...
Page 452 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) The ASISn register is a register that is configured of a UARTn transmission status flag (SOTn), reception status flag (SIRn), a bit (RB8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (PEn, FEn, OVEn) that indicate the error status at reception end (n = 1, 2).
Page 453 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <2> <1> <0> Address Initial value ASIS1 SOT1 SIR1 OVE1 FFFFFA2CH <7> <6> <2> <1> <0> Address Initial value ASIS2 SOT2 SIR2 OVE2 FFFFFA4CH Bit Position Bit Name Function Status flag indicating transmission status SOTn 0: Transmission end timing (when INTSTn is generated) Note...
Page 454 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) 2-frame continuous reception buffer registers 1, 2 (RXB1, RXB2)/reception buffer registers L1, L2 (RXBL1, RXBL2) The RXBn register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (UMSR bit of ASIMn1 register = 1), during 9-bit extended data reception (EBS bit of ASIMn1 register = 1)) (n = 1, 2).
Page 455 CHAPTER 10 SERIAL INTERFACE FUNCTION [2-frame continuous reception buffer register 1] Address Initial value RXB1 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA20H Undefined [Reception buffer register L1] Address Initial value RXBL1 RXB7 RXB6...
Page 456 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Cautions <1> Operation upon occurrence of overrun error during 2-frame continuous reception • During normal reception Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 •...
Page 457 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmission shift registers L1, L2 (TXSL1, TXSL2) The TXSn register is a 9-bit/2-frame continuous transmission processing shift register (n = 1, 2). Transmission is started by writing data to this register. A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of transmission of 1 frame or 2 frames including the TXSn data.
Page 458: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Interrupt requests The following two types of interrupt request are generated from UARTn (n = 1, 2). • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The reception completion interrupt has higher default priority than the transmission completion interrupt. Table 10-5.
Page 459: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Operation (1) Data format Full-duplex serial data is transmitted and received. Figure 10-16 shows the format of transmit/receive data. One data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). When 2 data frame transfer is set, both frames have the above-described format.
Page 460 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-6. ASIMn0, ASIMn1 Register Settings and Data Format ASIMn0, ASIMn1 Register Settings Data Format CL Bit PS1 Bit PS0 Bit SL Bit EBS Bit D0 to D6    DATA Stop bit  ...
Page 461 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation The transmission operation is started by writing data to 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmission shift registers L1, L2 (TXSL1, TXSL2). Following data write, the start bit is transmitted from the next shift timing. Since the UARTn does not have a CTS (transmission enable signal) input pin, use a port when the other party confirms the reception enabled status (n = 1, 2).
Page 462 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-17. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) When stop bit length = 1 bit TXDn (output) Start Parity Stop INTSTn interrupt Flag in transmission (SOTn) (b) When stop bit length = 2 bits TXDn (output) Start Parity...
Page 463 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission of 3 or more frames In addition to the 1-frame/2-frame transmission function, UARTn also enables continuous transmission of 3 or more frames, using the method shown below (n = 1, 2). (a) How to continuously transmit 3 or more frames (when the stop bit is 1 bit (SL bit = 0)) Three frames can be continuously transmitted by writing transmit data to the TXSn/TXSLn register in the period between the generation of the transmission completion interrupt request (INTSTn) and 4 ×...
Page 464 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation The reception wait status is entered by setting the RXEn bit of the ASIMn0 register to 1 (n = 1, 2). To start the reception operation, first perform start bit detection. Start bit detection is done by performing sampling of the RXDn pin.
Page 465 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Reception completion interrupt request When reception of one frame of data has been completed (stop bit detection) when the RXEn bit of the ASIMn0 register = 1, the receive data in the shift register is transferred to RXBn/RXBLn and a reception completion interrupt request (INTSRn) is generated after 1 frame or 2 frames of data have been transferred to RXBn/RXBLn.
Page 466 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-19. Asynchronous Serial Interface Reception Completion Interrupt Timing (a) When stop bit length = 1 bit RXDn (input) Start Parity Stop INTSRn interrupt Flag in reception (SIRn) (b) When stop bit length = 2 bits RXDn (input) Start Parity...
Page 467 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Reception errors The three types of error flags of parity errors, framing errors, and overrun errors are affected in synchronization with reception operation. As a result of data reception, the PEn, FEn, and OVEn flags of the ASISn register are set (1) and a reception completion interrupt request (INTSRn) is generated at the same time.
Page 468 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Odd parity <1> During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1” within the transmit data including the parity bit is odd. The parity bit value is as follows. •...
Page 469: Synchronous Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Synchronous mode The synchronous mode can be set with the ASCKn pin, which is the serial clock I/O pin (n = 1, 2). The synchronous mode is set with the MOD bit of the ASIMn1 register, and the serial clock to be used for synchronization is selected with the SCLS bit of the ASIMn0 register.
Page 470 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (1/3) (a) In 1-frame transmission/reception mode Serial clock Transmit data Stop bit Transmission register write signal Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception completion interrupt...
Page 471 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (2/3) (b) In 2-frame continuous transmission/reception mode Serial clock Transmit data Stop bit Stop bit Transmission register write signal Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception...
Page 472 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (3/3) (c) Transmission/reception timing and transmit data timing during serial clock output Serial clock (output) System clock Transmit data Transmission timing Reception timing Note Note The transmit data is delayed by 1 system clock in relation to the serial clock. (d) Transmission/reception timing and transmit data timing using external serial clock External serial clock System clock...
Page 473 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception (a) During normal operation (in 1-frame reception mode) Receive data START STOP Flag in reception (SIRn) Reception completion interrupt (INTSRn) Error interrupt (b) In 2-frame continuous reception mode Receive data START...
Page 474: Dedicated Baud Rate Generators 1, 2 (Brg1, Brg2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Dedicated baud rate generators 1, 2 (BRG1, BRG2) (1) Configuration of baud rate generators 1, 2 (BRG1, BRG2) For UART1 and UART2, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (f ) for each channel.
Page 475 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generators 1, 2 (BRG1, BRG2) BRGn is configured of an 8-bit timer counter for baud rate signal generation, a prescaler mode register that controls the generation of the baud rate signal (PRSMn), a prescaler compare register that sets the value of the 8-bit timer counter (PRSCMn), and a prescaler (n = 1, 2).
Page 476 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter (n = 1, 2). These registers can be read/written in 8-bit units. Cautions 1.
Page 477 CHAPTER 10 SERIAL INTERFACE FUNCTION (f) Baud rate setting value The formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> Formula for calculating baud rate in asynchronous mode Baud rate = [bps] 2 ×...
Page 478 CHAPTER 10 SERIAL INTERFACE FUNCTION <4> Baud rate setting example In an actual system, the output of a prescaler module, etc. is connected to input clock. Table 10-8 shows the baud rate generator setting data at this time. Table 10-8. Baud Rate Generator Setting Data (BRG = f /2) (1/2) (a) When f = 32 MHz...
Page 479 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-8. Baud Rate Generator Setting Data (BRG = f /2) (2/2) (c) When f = 50 MHz Desired Baud Rate Actual Baud Rate BGCSm Bit PRSCMn Error (m = 0, 1) Register Setting Synchronous Asynchronous Synchronous Asynchronous...
Page 480 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 481 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × × −...
Page 482: Clocked Serial Interfaces 0, 1 (Csi0, Csi1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 10.4.1 Features • High-speed transfer: Maximum 4 Mbps • Half-duplex communications • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits can be set •...
Page 483: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed by writing/reading the SIOn register (n = 0, 1). (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn.
Page 484 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Clocked serial interface initial transmission buffer register L (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register.
Page 485 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-25. Block Diagram of Clocked Serial Interface Serial clock controller SCKn Clock start/stop control Selector & clock phase control Interrupt INTCSIn controller BRG3 SCKn Transmission control Transmission data control Control signal Initial transmission SO selection buffer register (SOTBFn/SOTBFLn) Transmission...
Page 486: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Control registers (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSIn operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Caution Overwriting the TRMDn, CCL, DIRn, CSIT, and AUTO bits of the CSIMn register can be done only when the CSOTn bit = 0.
Page 487 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <4> <0> Address Initial value CSIM0 CSICAE0 TRMD0 DIR0 CSIT AUTO CSOT0 FFFFF900H <7> <6> <4> <0> Address Initial value CSICAE1 TRMD1 DIR1 CSIT AUTO CSOT1 CSIM1 FFFFF910H Bit Position Bit Name Function CSICAEn Enables/disables CSIn operation.
Page 488 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units. Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register = 0.
Page 489 CHAPTER 10 SERIAL INTERFACE FUNCTION Address Initial value CSIC0 CKS2 CKS1 CKS0 FFFFF901H Address Initial value CSIC1 CKS2 CKS1 CKS0 FFFFF911H Bit Position Bit Name Function 4, 3 CKP, DAP Specifies operation mode. Operation Mode SCKn (I/O) SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIn (input) SCKn (I/O) SOn (output)
Page 490 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Clocked serial interface reception buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 491 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Clocked serial interface reception buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 492 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface read-only reception buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 493 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Clocked serial interface read-only reception buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 494 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Clocked serial interface transmission buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 495 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Clocked serial interface transmission buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 496 CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Clocked serial interface initial transmission buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 497 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit or 1-bit units.
Page 498 CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only in 16-bit units.
Page 499 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only in 8-bit or 1-bit units.
Page 500: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Operation (1) Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by reading the receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). Note 2 In the transmission/reception mode (TRMDn bit of CSIMn register = 1), transfer is started by writing to the transmit data buffer register (SOTBn/SOTBLn).
Page 501 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) (55H)
Page 502 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) (55H)
Page 503 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions. •...
Page 504 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (I/O) SIn (input) SOn (output) DO6 DO5 DO4 DO3 DO2 DO1 Reg_R/W INTCSIn interrupt CSOTn bit (d) When CKP bit = 1, DAP bit = 1 SCKn (I/O)
Page 505 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSIn is set (1) upon completion of data transmission/reception. Caution The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 506 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1.
Page 507 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 508 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. Repeat Transfer (Receive-Only) Timing Chart SCKn (I/O) SIn (input) din-1 din-2 din-3 din-4 din-5 SIOLn din-5 register SIRBLn din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg_RD SIRBn (dummy) SIRBn (d1) SIRBn (d2) SIRBn (d3) SIOn (d5) CSOTn bit INTCSIn...
Page 509 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMDn bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3>...
Page 510 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Repeat Transfer (Transmission/Reception) Timing Chart SCKn (I/O) SOn (output) dout-1 dout-2 dout-3 dout-4 dout-5 din-1 din-2 din-3 din-4 din-5 SIn (input) SOTBFLn dout-1 register SOTBLn dout-2 dout-3 dout-4 dout-5 register SIOLn din-5 register SIRBLn din-1 din-2...
Page 511 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 10-31. Figure 10-31. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) INTCSIn...
Page 512 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 6.5 SCKn cycles (d) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O)
Page 513 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 514 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 10-33). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 515: Output Pins
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.5 Output pins (1) SCKn pin When the CSIn operation is disabled (CSICAEn bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). Table 10-9. SCKn Pin Output Status CKS2 CKS1 CKS0...
Page 516: Dedicated Baud Rate Generator 3 (Brg3)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.6 Dedicated baud rate generator 3 (BRG3) (1) Configuration of baud rate generator 3 (BRG3) The CSI0 and CSI1 serial clocks can be selected from the dedicated baud rate generator output or internal system clock (f The serial clock source is specified with registers CSIC0 and CSIC1.
Page 517 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generator 3 (BRG3) BRG3 is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register 3 (PRSM3) that controls baud rate signal generation, a prescaler compare register 3 (PRSCM3) that sets the value of the 8-bit timer counter, and a prescaler.
Page 518 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare register 3 (PRSCM3) PRSCM3 is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSM3 register. Therefore, do not write to the PRSCM3 register during transmission.
Page 519 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Baud rate setting value Table 10-11. Baud Rate Generator Setting Data (a) When f = 32 MHz BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 (b) When f = 40 MHz BGCS1...
Page 520: Chapter 11 Fcan Controller
CHAPTER 11 FCAN CONTROLLER The V850E/IA1 features a 1 channel on-chip FCAN (Full Controller Area Network) controller that complies with the CAN specification Ver. 2.0, PartB active. 11.1 Function Overview Table 11-1 presents an overview of V850E/IA1 functions. Table 11-1. Overview of Functions Function Description Protocol...
Page 521: Configuration
11.2 Configuration FCAN is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface as a means of transmitting and receiving signals. (2) MAC (Memory Access Controller) This functional block controls access to the CAN module and to the CAN RAM within the FCAN.
Page 522 CHAPTER 11 FCAN CONTROLLER Figure 11-1. Block Diagram of FCAN Interrupt request INTCREC CAN bus (NEC peripheral I/O bus) INTCTRX INTCERR INTCMAC FCAN controller CAN_H CTXD (Memory Access Controller) interface module transceiver CAN_L CRXD CAN RAM Message CMASK0 buffer 0...
Page 523: Configuration Of Messages And Buffers
CHAPTER 11 FCAN CONTROLLER 11.3 Configuration of Messages and Buffers Table 11-2. Configuration of Messages and Buffers Note Address (m = 2, 6, A, E) Register Name xxxxm800H to xxxxm81FH Message buffer 0 field xxxxm820H to xxxxm83FH Message buffer 1 field xxxxm840H to xxxxm85FH Message buffer 2 field xxxxm860H to xxxxm87FH...
Page 524: Time Stamp Function
CHAPTER 11 FCAN CONTROLLER 11.4 Time Stamp Function The FCAN controller supports a time stamp function. This function is needed to build a global time system. The time stamp function is implemented using a 16-bit free-running time stamp counter. Two types of time stamp function can be selected for message reception in the FCAN controller. Use bit 3 (TMR) of the CAN1 control register (C1CTRL) to set the desired time stamp function.
Page 525 CHAPTER 11 FCAN CONTROLLER Figure 11-3. Time Stamp Function Setting for Message Reception (When C1CTRL Register’s TMR Bit = 1) ACK field Message CAN message buffer n <1> Time stamp M_TIMEn counter <Explanation> <1> When the EOF is detected on the CAN bus (a valid message is acknowledged), the captured time stamp counter value is copied to the M_TIMEn register in CAN message buffer n when a message is stored in CAN message buffer n.
Page 526 CHAPTER 11 FCAN CONTROLLER Figure 11-4. Time Stamp Function Setting for Message Transmission (When M_CTRL Register’s ATS Bit = 1) ACK field Message <2> <1> Time stamp Temporary counter buffer <Explanation> <1> The time stamp counter value is captured to the temporary buffer when the SOF is detected on the CAN bus. Note <2>...
Page 527: Message Processing
CHAPTER 11 FCAN CONTROLLER 11.5 Message Processing A modular system is used for the FCAN controller. Consequently, messages can be placed at any location within the message area. The messages can be linked to mask functions that are in turn linked to CAN modules. The FCAN system is a multiplexed communication system.
Page 528: Mask Function
CHAPTER 11 FCAN CONTROLLER If ID based on location in memory is the same for multiple messages, the message buffer having the lowest message number is selected. When a message is stored, multiple message buffers are allocated to the same ID. At this time, data is stored in the message buffers, starting from the message buffer with the lowest message number, as long as data is not already stored in all the allocated message buffers (as long as the DN bit of the M_STATn register is not set to 1).
Page 529 CHAPTER 11 FCAN CONTROLLER <3> Mask setting for mask 1 (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9...
Page 530: Protocol
CHAPTER 11 FCAN CONTROLLER 11.7 Protocol FCAN is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. The CAN specification is generally divided into two layers (physical layer and data link layer). The data link layer is further divided into logical link control and medium access control. The composition of these layers is illustrated in Figure 11-6 below.
Page 531: Message Formats
CHAPTER 11 FCAN CONTROLLER 11.7.2 Message formats Four types of frames are used in CAN protocol messages. The output conditions for each type of frame are as follows. • Data frame: Frame used for transmit data • Remote frame: Frame used for transmit requests from receiving side •...
Page 532 CHAPTER 11 FCAN CONTROLLER <2> Remote frame A remote frame is transmitted when the receiving node issues a transmit request. A remote frame is similar to a data frame, except that the “data field” is deleted and the RTR bit of the “arbitration field”...
Page 533 CHAPTER 11 FCAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame or remote frame, and protocol mode. This field includes an identifier, frame setting (RTR bit), and protocol mode setting bit. Figure 11-10. Arbitration Field (In Standard Format Mode) Arbitration field (Control field) Identifier...
Page 534 CHAPTER 11 FCAN CONTROLLER <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). r1 and r0 are fixed as dominant (D). The data length code bits (DLC3 to DLC0) set the byte count. Remark DLC3 to DLC0: Bits 3 to 0 in CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) (see 11.10 (2))
Page 535 CHAPTER 11 FCAN CONTROLLER <4> Data field The data field contains the amount of data set by the control field. Up to 8 units of data can be set. Remark Data units in the data field are each 8 bits long and are ordered MSB first. Figure 11-13.
Page 536 CHAPTER 11 FCAN CONTROLLER <6> ACK field The ACK field is used to confirm normal reception. It includes a 1-bit ACK slot and a 1-bit ACK delimiter. Figure 11-15. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit)
Page 537 CHAPTER 11 FCAN CONTROLLER <8> Interframe space The interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next one. • Error active node When the bus is idle, transmit enable mode is set for each node. Transmission then starts from a node that has received a transmit request.
Page 538 CHAPTER 11 FCAN CONTROLLER Table 11-7. Operation When Third Bit of Intermission Is “Dominant (D)” Transmit Status Operation No pending transmissions Receive operation is performed when start of frame output by other node is detected. Pending transmission exists Identifier is transmitted when start of frame output by local node is detected.
Page 539 CHAPTER 11 FCAN CONTROLLER <10> Overload frame An overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. If a bit error is detected in intermission mode, it is output starting from the bit following the bit where the bit error was detected.
Page 540: Functions
CHAPTER 11 FCAN CONTROLLER 11.8 Functions 11.8.1 Determination of bus priority (1) When one node has started transmitting • In bus idle mode, the node that outputs data first starts transmission. (2) When several nodes have started transmitting • The node that has the longest string of consecutive “dominant (D)” bits starting from the first bit in the arbitration field has top priority for bus access (“dominant (D)”...
Page 541: Can Sleep Mode/Can Stop Mode Function
CHAPTER 11 FCAN CONTROLLER 11.8.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function is able to set the FCAN controller to sleep (standby) mode to reduce power consumption. The CAN sleep mode is set via the procedure stipulated in the CAN specification. The CAN sleep mode can be set to wake up by the bus operation, however the CAN stop mode cannot be set to wake up by the bus operation (this is controlled via CPU access).
Page 542 CHAPTER 11 FCAN CONTROLLER (4) Error statuses (a) Types of error statuses The three types of error statuses are listed below. Error active Error passive Bus off • Error status is controlled by the transmit error counter and receive error counter (see 11.10 (23) CAN1 error count register (C1ERC)).
Page 543 CHAPTER 11 FCAN CONTROLLER (b) Error counter The error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. The count up/count down timing occurs at the first bit of the error delimiter.
Page 544: Baud Rate Control Function
CHAPTER 11 FCAN CONTROLLER 11.8.7 Baud rate control function (1) Prescaler The V850E/IA1 includes a prescaler for dividing the CAN module clock (f ). This prescaler generates a clock (f ) that is based on a division ratio ranging from 2 to 128 applied to the CAN module clock when the C1BRP register’s TLM bit = 0 and based on a division ratio ranging from 2 to 256 applied to the CAN module clock when the TLM bit = 1 (refer to 11.10 (26) CAN1 bit rate prescaler register (C1BRP)).
Page 545 CHAPTER 11 FCAN CONTROLLER (3) Data bit synchronization • Since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. • As for the transmitting node, data is transmitted in sync with the transmitting node’s bit timing. (a) Hardware synchronization This is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode.
Page 546 CHAPTER 11 FCAN CONTROLLER (b) Resynchronization Resynchronization is performed when a level change is detected on the bus during a receive operation. • The edge’s phase error is produced by the relative positions of the detected edge and sync segment. <Phase error symbols>...
Page 547: Cautions On Bit Set/Clear Function
CHAPTER 11 FCAN CONTROLLER 11.9 Cautions on Bit Set/Clear Function The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them.
Page 548 CHAPTER 11 FCAN CONTROLLER Figure 11-24. 16-Bit Data During Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Bit Status After Bit Set/Clear Operation...
Page 549: Control Registers
CHAPTER 11 FCAN CONTROLLER 11.10 Control Registers (1) FCAN clock selection register (PRM04) The PRM04 register is used to select the base clock (f MEM1 The clock is selected according to the clock frequency. This register can be read/written in 8-bit or 1-bit units. Caution Set this register before using FCAN.
Page 550 CHAPTER 11 FCAN CONTROLLER (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) The M_DLCn register sets the byte count in the data field of CAN message buffer n (n = 00 to 31). When receiving, the receive data field’s byte count is set (to 1). These registers can be read/written in 8-bit units.
Page 551 CHAPTER 11 FCAN CONTROLLER Table 11-14. Addresses of M_DLCn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_DLC00 xxxxm804H M_DLC16 xxxxmA04H M_DLC01 xxxxm824H M_DLC17 xxxxmA24H M_DLC02...
Page 552 CHAPTER 11 FCAN CONTROLLER (3) CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) The M_CTRLn register is used to set the frame format of the data field in messages stored in CAN message buffer n (n = 00 to 31). These registers can be read/written in 8-bit units.
Page 553 CHAPTER 11 FCAN CONTROLLER (2/2) Bit Position Bit Name Function Specifies whether or not to add a time stamp when transmitting. 0: Time stamp not added when transmitting 1: Time stamp added when transmitting Cautions 1. The ATS bit is used only for transmit messages. 2.
Page 554 CHAPTER 11 FCAN CONTROLLER Table 11-15. Addresses of M_CTRLn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_CTRL00 xxxxm805H M_CTRL16 xxxxmA05H M_CTRL01 xxxxm825H M_CTRL17 xxxxmA25H M_CTRL02...
Page 555 CHAPTER 11 FCAN CONTROLLER (4) CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) The M_TIMEn register is the register where the time stamp counter value is written upon completion of data reception (n = 00 to 31). These registers can be read/written in 16-bit units.
Page 556 CHAPTER 11 FCAN CONTROLLER (5) CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) (n = 00 to 31) The M_DATAnx registers are areas where up to 8 bytes of transmit or receive data is stored (n = 00 to 31, x = 0 to 7).
Page 557 CHAPTER 11 FCAN CONTROLLER Table 11-17. Addresses of M_DATAnx (n = 00 to 31, x = 0 to 7) Register Note Note Note Note Note Note Note Note M_DATAn0 M_DATAn1 M_DATAn2 M_DATAn3 M_DATAn4 M_DATAn5 M_DATAn6 M_DATAn7 Name (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E)
Page 558 CHAPTER 11 FCAN CONTROLLER (6) CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) The M_IDLn and M_IDHn registers are areas used to set identifiers (n = 00 to 31). These registers can be read/written in 16-bit units. When in standard format mode, any data can be stored in the following areas.
Page 559 CHAPTER 11 FCAN CONTROLLER Table 11-18. Addresses of M_IDLn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_IDL00 xxxxm810H M_IDL16 xxxxmA10H M_IDL01 xxxxm830H M_IDL17 xxxxmA30H M_IDL02...
Page 560 CHAPTER 11 FCAN CONTROLLER (7) CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFn register is used to set the message buffer type and mask (n = 00 to 31). These registers can be read/written in 8-bit units. Address Initial value M_CONFn...
Page 561 CHAPTER 11 FCAN CONTROLLER Table 11-20. Addresses of M_CONFn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_CONF00 xxxxm814H M_CONF16 xxxxmA14H M_CONF01 xxxxm834H M_CONF17 xxxxmA34H M_CONF02...
Page 562 CHAPTER 11 FCAN CONTROLLER (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). These registers are read-only in 8-bit units. Cautions 1. Writing directly to M_STATn register cannot be performed. Writing must be performed using CAN status set/clear register n (SC_STATn).
Page 563 CHAPTER 11 FCAN CONTROLLER Table 11-21. Addresses of M_STATn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) M_STAT00 xxxxm815H M_STAT16 xxxxmA15H M_STAT01 xxxxm835H M_STAT17 xxxxmA35H M_STAT02...
Page 564 CHAPTER 11 FCAN CONTROLLER (9) CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31) The SC_STATn register is used to set/clear the transmit/receive status information (n = 00 to 31). These registers are write-only in 16-bit units. Address Initial value SC_STATn clear clear...
Page 565 CHAPTER 11 FCAN CONTROLLER Table 11-22. Addresses of SC_STATn (n = 00 to 31) Note Note Register Name Address (m = 2, 6, A, E) Register Name Address (m = 2, 6, A, E) SC_STAT00 xxxxm816H SC_STAT16 xxxxmA16H SC_STAT01 xxxxm836H SC_STAT17 xxxxmA36H SC_STAT02...
Page 566 CHAPTER 11 FCAN CONTROLLER (10) CAN interrupt pending register (CCINTP) The CCINTP register is used to confirm the pending status of various interrupts. This register is read-only in 16-bit units. Address Initial value Note CAN1 CAN1 CAN1 xxxxmC00H 0000H CCINTP INTMAC Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers.
Page 567 CHAPTER 11 FCAN CONTROLLER (11) CAN global interrupt pending register (CGINTP) The CGINTP register is used to confirm the pending status of MAC error interrupts. This register can be read/written in 8-bit units. Cautions 1. When “1” is written to a bit in the CGINTP register, that bit is cleared (to 0). When “0” is written to it, the bit’s value does not change.
Page 568 CHAPTER 11 FCAN CONTROLLER (12) CAN1 interrupt pending register (C1INTP) The C1INTP register is used to confirm the pending status of interrupts issued to FCAN. This register can be read/written in 8-bit units. Cautions 1. When “1” is written to a bit in the C1INTP register, that bit is cleared (to 0). When “0” is written to it, the bit’s value does not change.
Page 569 CHAPTER 11 FCAN CONTROLLER (13) CAN stop register (CSTOP) The CSTOP register controls clock supply to the entire CAN system. This register can be read/written in 16-bit units. Cautions 1. Be sure to set the CSTP bit (to 1) if the FCAN function will not be used. 2.
Page 570 CHAPTER 11 FCAN CONTROLLER (14) CAN global status register (CGST) The CGST register indicates global status information. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 571 CHAPTER 11 FCAN CONTROLLER (2/3) (a) Read Bit Position Bit Name Function MERR This is the status flag that indicates an MAC error. 0: Error has not occurred after the MERR bit has been cleared. 1: Error occurred at least once after the MERR bit was cleared. Caution An MAC error occurs when access to an invalid RAM address is attempted.
Page 572 CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write Bit Position Bit Name Function Sets/clears the EFSD bit. 11, 3 set EFSD, clear EFSD set EFSD clear EFSD Operation EFSD bit cleared (to 0) EFSD bit set (to 1) Other than above No change in EFSD bit value Sets/clears the TSM bit.
Page 573 CHAPTER 11 FCAN CONTROLLER (15) CAN global interrupt enable register (CGIE) The CGIE register is used to issue interrupt requests for global interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 574 CHAPTER 11 FCAN CONTROLLER (16) CAN main clock selection register (CGCS) The CGCS register is used to select the main clock. This register can be read/written in 16-bit units. (1/2) Address Initial value Note CGTS CGTS CGTS CGTS CGTS CGTS CGTS CGTS GTCS...
Page 575 CHAPTER 11 FCAN CONTROLLER (2/2) Bit Position Bit Name Function 3 to 0 MCP3 to Specifies the clock to memory access controller (f ) (see Figure 11-25). MCP0 MCP3 MCP2 MCP1 MCP0 Selection of Clock to Memory Access Controller (f MEM1 MEM1 MEM1...
Page 576 CHAPTER 11 FCAN CONTROLLER (17) CAN time stamp count register (CGTSC) The CGTSC register indicates the contents of the time stamp counter. This register can be read at any time. This register can be written to only when clearing bits. The clear function writes 0 to all bits in the CGTSC register.
Page 577 CHAPTER 11 FCAN CONTROLLER (18) CAN message search start/result register (CGMSS (during write)/CGMSR (during read)) The CGMSS/CGMSR register indicates the message search start/result status. Messages in the message buffer that match the specified search criteria can be searched quickly. These registers can be read/written in 16-bit units. (1/2) Address Initial value...
Page 578 CHAPTER 11 FCAN CONTROLLER (2/2) (b) Write Bit Position Bit Name Function CIDE Checks message identifier (ID) format flag. 0: Message identifier format flag not checked 1: Only message with standard format identifier checked CTRQ Checks transmit request and message ready flag. 0: Transmit request and message ready flag not checked 1: Transmit request and message ready flag checked CMSK...
Page 579 CHAPTER 11 FCAN CONTROLLER (19) CAN1 address mask a registers L and H (C1MASKLa and C1MASKHa) The C1MASKLa and C1MASKHa registers are used to extend the number of receivable messages by masking part of the message’s identifier (ID) and then ignoring the masked parts (a = 0 to 3). These registers can be read/written in 16-bit units.
Page 580 CHAPTER 11 FCAN CONTROLLER Table 11-23. Addresses of C1MASKLa and C1MASKHa (a = 0 to 3) Note Register Name Address (m = 2, 6, A, E) C1MASKL0 xxxxmC40H C1MASKH0 xxxxmC42H C1MASKL1 xxxxmC44H C1MASKH1 xxxxmC46H C1MASKL2 xxxxmC48H C1MASKH2 xxxxmC4AH C1MASKL3 xxxxmC4CH C1MASKH3 xxxxmC4EH Note CAN message buffer registers can be allocated to the xxxx addresses as...
Page 581 CHAPTER 11 FCAN CONTROLLER (20) CAN1 control register (C1CTRL) The C1CTRL register is used to control the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1CTRL register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 582 CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit Position Bit Name Function BOFF This is the bus off status flag. 0: Transmit error counter < 256 (not bus off status) 1: Transmit error counter ≥ 256 (bus off status) TSTAT This is the transmit status flag.
Page 583 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit Position Bit Name Function SLEEP This is the CAN sleep mode control bit. 0: Normal operation mode 1: Switch to CAN sleep mode. Change in CAN bus performs wake-up. Cautions 1. CAN sleep mode is canceled under the following conditions. •...
Page 584 CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write (2/2) Bit Position Bit Name Function 12, 4 set OVM, Sets/clears the OVM bit. clear OVM clear Operation OVM bit cleared (to 0) OVM bit set (to 1) Other than above OVM bit not changed 11, 3 set TMR, Sets/clears the TMR bit.
Page 585 CHAPTER 11 FCAN CONTROLLER (21) CAN1 definition register (C1DEF) The C1DEF register is used to define the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1DEF register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 586 CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit Position Bit Name Function Specifies the CAN module operation mode. 0: Normal operating mode 1: Diagnostic processing mode Caution When in diagnostic processing mode (MOM bit = 1), the C1BRP register can be accessed only when the CAN module has been set to initialization mode (i.e., when the C1CTRL register’s ISTAT bit = INIT bit = 1).
Page 587 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit Position Bit Name Function WAKE Indicates CAN sleep mode cancellation status. 0: Normal operation 1: CAN sleep mode canceled Indicates overrun error status. 0: Normal operation 1: Overrun occurred during RAM access Caution When an overrun error has occurred, the OVR bit is set (to 1) and an error interrupt occurs at the same time.
Page 588 CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write Bit Position Bit Name Function 15, 7 set DGM, Sets/clears the DGM bit. clear DGM set DGM clear DGM Operation DGM bit cleared (to 0) DGM bit set (to 1) Other than above DGM bit not changed 14, 6 set MOM,...
Page 589 CHAPTER 11 FCAN CONTROLLER (22) CAN1 information register (C1LAST) The C1LAST register indicates the CAN module’s error information and the number of the message buffer received last. This register is read-only in 16-bit units. Address Initial value Note C1LAST LERR3 LERR2 LERR1 LERR0...
Page 590 CHAPTER 11 FCAN CONTROLLER (23) CAN1 error count register (C1ERC) The C1ERC register indicates the count values of the transmission/reception error counters. This register is read-only in 16-bit units. Address Initial value Note C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7...
Page 591 CHAPTER 11 FCAN CONTROLLER (24) CAN1 interrupt enable register (C1IE) The C1IE register is used to enable/disable the CAN module’s interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1IE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function.
Page 592 CHAPTER 11 FCAN CONTROLLER (2/3) (b) Write (1/2) Bit Position Bit Name Function 14, 6 Sets/clears the E_INT6 bit. E_INT6, set E_INT6 clear E_INT6 Operation clear E_INT6 interrupt cleared (to 0) E_INT6 E_INT6 interrupt set (to 1) Other than above E_INT6 interrupt not changed 13, 5 Sets/clears the E_INT5 bit.
Page 593 CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write (2/2) Bit Position Bit Name Function 8, 0 Sets/clears the E_INT0 bit. E_INT0, set E_INT0 clear E_INT0 Operation clear E_INT0 interrupt cleared (to 0) E_INT0 E_INT0 interrupt set (to 1) Other than above E_INT0 interrupt not changed User’s Manual U14492EJ3V0UD...
Page 594 CHAPTER 11 FCAN CONTROLLER (25) CAN1 bus active register (C1BA) The C1BA register indicates frame information output via the CAN bus. This register is read-only in 16-bit units. Address Initial value Note C1BA CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3...
Page 595 CHAPTER 11 FCAN CONTROLLER (26) CAN1 bit rate prescaler register (C1BRP) The C1BRP register is used to set the transmission baud rate for the CAN module. Use the C1BRP register to select the CAN protocol layer base system clock (f ).
Page 596 CHAPTER 11 FCAN CONTROLLER (1/2) Address Initial value C1BRP Note BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 xxxxmC5CH 0000H (TLM = 0) C1BRP BTYPE BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 (TLM = 1) Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers.
Page 597 CHAPTER 11 FCAN CONTROLLER (2/2) (b) When TLM = 1 Bit Position Bit Name Function Specifies transfer layer mode. 1: 8-bit prescaler mode BTYPE Specifies CAN bus type. 0: Low speed (≤ 125 kbps) 1: High speed (> 125 kbps) 7 to 0 BRP7 to Specifies CAN protocol layer base system clock (f...
Page 598 CHAPTER 11 FCAN CONTROLLER (27) CAN1 bus diagnostic information register (C1DINF) The C1DINF register indicates all CAN bus bits, including stuff bits, delimiters, etc. This information is used only for diagnostic purposes. Because the number of bits starting from SOF is added at each frame, the actual number of bits is the value obtained by subtracting the previous data.
Page 599 CHAPTER 11 FCAN CONTROLLER (28) CAN1 synchronization control register (C1SYNC) The C1SYNC register controls the data bit time for transmission speed. This register can be read/written in 16-bit units. Cautions 1. The CPU is able to read the C1SYNC register at any time. 2.
Page 600 CHAPTER 11 FCAN CONTROLLER (2/2) Bit Position Bit Name Function 9 to 5 SPT4 to Specifies position of sampling points. SPT0 SPT4 SPT3 SPT2 SPT1 SPT0 Position of Sampling Point BTL × 5 BTL × 6 BTL × 7 BTL × 8 BTL ×...
Page 601: Operations
CHAPTER 11 FCAN CONTROLLER 11.11 Operations 11.11.1 Initialization processing Figure 11-26 shows a flowchart of initialization processing. The register setting flow is shown in Figures 11-27 to 11-36. Figure 11-26. Initialization Processing START Set CAN main clock selection register : See Figure 11-27 CAN Main Clock Selection Register (CGCS) Settings (CGCS) Set CAN global interrupt enable register : See Figure 11-28 CAN Global Interrupt Enable Register (CGIE) Settings...
Page 602 CHAPTER 11 FCAN CONTROLLER Figure 11-27. CAN Main Clock Selection Register (CGCS) Settings START Select clock for memory access controller /(n + 1) MEM1 (MCP0 to MCP3) n = 0 to 15 (set using bits MCP0 to MCP3) GTCS1, GTCS0 = 00: f GTS1 Select global timer clock GTCS1, GTCS0 = 01: f...
Page 603 CHAPTER 11 FCAN CONTROLLER Figure 11-29. CAN Global Status Register (CGST) Settings START Start FCAN operation set GOM = 1 clear GOM = 0 Use time stamp function? set TSM = 1 clear TSM = 0 Figure 11-30. CAN1 Bit Rate Prescaler Register (C1BRP) Settings START Transfer speed is 125 kbps or less...
Page 604 CHAPTER 11 FCAN CONTROLLER Figure 11-31. CAN1 Synchronization Control Register (C1SYNC) Settings START 1 bit time = BTL × (m + 1) Set data bit time (DBT4 to DBT0) m = 7 to 24 (set using bits DBT4 to DBT0) Sampling point = BTL ×...
Page 605 CHAPTER 11 FCAN CONTROLLER Figure 11-32. CAN1 Interrupt Enable Register (C1IE) Settings START Interrupt enable flag Enable interrupt for end of transmission for E_INT0? clear E_INT0 = 1 set E_INT0 = 1 set E_INT0 = 0 clear E_INT0 = 0 Interrupt enable flag Enable interrupt for end of reception...
Page 606 CHAPTER 11 FCAN CONTROLLER Figure 11-33. CAN1 Definition Register (C1DEF) Settings START Set to diagnostic processing mode? clear MOM = 1 set MOM = 1 Normal operation mode Diagnostic processing mode set MOM = 0 clear MOM = 0 Note Store to buffer used for diagnostic processing mode?
Page 607 CHAPTER 11 FCAN CONTROLLER Figure 11-34. CAN1 Control Register (C1CTRL) Settings START Set time stamp for Store timer value receiving when SOF occurs? Store timer value when clear TMR = 1 set TMR = 1 EOF occurs set TMR = 0 clear TMR = 0 Set overwrite for Store message...
Page 608 CHAPTER 11 FCAN CONTROLLER Figure 11-35. CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings START Standard frame Mask setting for extended frame (x = 0 to 28) (y = 0 to 17) CMIDy = 1 Mask setting for standard frame (x = 18 to 28)
Page 609 CHAPTER 11 FCAN CONTROLLER Figure 11-36. Message Buffer Settings START Set message Standard frame? ID type IIDE = 0 (standard) IDE = 1 (extended) (M_IDHn) (M_IDHn) Set identifier (standard, extended) See Figure 11-37 CAN Message Configuration Set message configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings Set message length See Figure 11-38 CAN Message Control...
Page 610 CHAPTER 11 FCAN CONTROLLER Figure 11-37. CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings START Release CAN Use message buffer? message buffer MA = 0 MA = 1 MT2 to MT0 = 000 Transmit message Receive message MT2 to MT0 = 001 (no mask setting) Receive message...
Page 611 CHAPTER 11 FCAN CONTROLLER Figure 11-38. CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Settings START Transmit/receive data frame? RTR = 0 RTR = 1 Transmit/receive remote frame Disable interrupt? IE = 0 IE = 1 Enable interrupt Set remote frame auto Remote frame auto acknowledge function...
Page 612: Transmit Setting
CHAPTER 11 FCAN CONTROLLER 11.11.2 Transmit setting Transmit messages are output from the target message buffer. Figure 11-39. Transmit Setting START Select transmit message buffer Set data (M_DATAnm) Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Set transmit request flag set TRQ = 1, clear TRQ = 0 (SC_STATn)
Page 613: Receive Setting
CHAPTER 11 FCAN CONTROLLER 11.11.3 Receive setting Receive messages are retrieved from the target message buffer. Figure 11-40. Receive Setting START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Confirm end of reception (reception completion interrupt or reception completion interrupt pending flag) : Detection methods...
Page 614: Can Sleep Mode
CHAPTER 11 FCAN CONTROLLER 11.11.4 CAN sleep mode In CAN sleep mode, the FCAN controller can be set to standby mode. A wake-up occurs when there is a bus operation. Figure 11-41. CAN Sleep Mode Settings START set SLEEP = 1 clear SLEEP = 0 (C1CTRL) SLEEP = 1...
Page 615: Can Stop Mode
CHAPTER 11 FCAN CONTROLLER Figure 11-43. Clearing of CAN Sleep Mode by CPU START clear SLEEP = 1 set SLEEP = 0 (C1CTRL) SLEEP = 0 (C1CTRL) End of CAN sleep mode clearing operation 11.11.5 CAN stop mode In CAN stop mode, the FCAN controller can be set to standby mode. No wake-up occurs when there is a bus operation (stop mode is controlled by CPU access only).
Page 616 CHAPTER 11 FCAN CONTROLLER Figure 11-45. Clearing of CAN Stop Mode START clear STOP = 1 set STOP = 0 clear SLEEP = 1 set SLEEP = 0 (C1CTRL) End of CAN stop mode clearing operation User’s Manual U14492EJ3V0UD...
Page 617: Rules For Correct Setting Of Baud Rate
CHAPTER 11 FCAN CONTROLLER 11.12 Rules for Correct Setting of Baud Rate The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that settings are within the range of limit values.
Page 618 CHAPTER 11 FCAN CONTROLLER Given the above limit values, the following three settings are possible. Prescaler SPT (MAX.) Calculated SPT 8/12 = 67% 12/16 = 75% 17/24 = 71% 16 MHz/83 kbps ≅ 192 = 64 × 3 <1> = 48 × 4 <2>...
Page 619 CHAPTER 11 FCAN CONTROLLER (ii) DBT (data bit time) setting DBT is calculated as below. • DBT = BTL × (a + 1) : [7 ≤ a ≤ 24] Value a is set using bits 4 to 0 (DBT4 to DBT0) of the C1SYNC register. DBT = BTL ×...
Page 620: Prioritization Of Message Buffers During Receive Comparison
CHAPTER 11 FCAN CONTROLLER Figure 11-46. C1SYNC Register Settings C1SYNC SAMP SJW1 SJW0 SPT4 SPT3 Setting SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 Setting 11.13 Prioritization of Message Buffers During Receive Comparison Several message buffers can be constructed for receiving messages. In such cases, a system of prioritization in receiving messages must be established for these message buffers.
Page 621: Reception Of Remote Frames
CHAPTER 11 FCAN CONTROLLER 11.13.2 Reception of remote frames Table 11-25. Prioritization of Message Buffers When Receiving Remote Frames Priority Ranking Description 1 (High) Receive messages can be stored in transmit message buffers when the receive messages meet the following conditions. •...
Page 622: Ensuring Data Consistency
CHAPTER 11 FCAN CONTROLLER 11.14 Ensuring Data Consistency When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent. Two methods are used to ensure data consistency: sequential data read and burst read mode. 11.14.1 Sequential data read When the CPU performs sequential access of a CAN message buffer, data is read from the buffer in the order shown in Figure 11-47 below.
Page 623: Burst Read Mode
CHAPTER 11 FCAN CONTROLLER 11.14.2 Burst read mode Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the synchrony of data. Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied from the message buffer area to a temporary read buffer.
Page 624: Interrupt Conditions
CHAPTER 11 FCAN CONTROLLER 11.15 Interrupt Conditions 11.15.1 Interrupts that are generated for FCAN controller When interrupts are enabled (condition <1>: M_CTRLn register’s IE bit = 1, conditions other than <1>: C1IE register’s interrupt enable flag = 1), interrupts will be generated under the following conditions (n = 00 to 31). <1>...
Page 625: How To Shut Down Fcan Controller
CHAPTER 11 FCAN CONTROLLER 11.16 How to Shut Down FCAN Controller The following procedure should be used to stop CAN bus operations in order to stop the clock supply to the CAN interface (to set low power mode). <1> FCAN controller’s initialization mode setting •...
Page 626: Cautions On Use
CHAPTER 11 FCAN CONTROLLER 11.17 Cautions on Use <1> Bit manipulation is prohibited for all FCAN controller registers. <2> Do not read the same register of the FCAN controller twice or more in a row. If the same register is read twice or more in a row, and even if the value of the register is changed while it is being read the second or subsequent time, the new value is not reflected, and the same value as the one read the first time is always read.
Page 627: Chapter 12 Nbd Function ( Μ Μ Μ Μ Pd70F3116)
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) The V850E/IA1 provides the Non Break Debug (NBD) function for on-chip data tuning. 12.1 Overview The NBD function encompasses the following functions. (1) RAM monitoring function This function makes an arbitrary RAM area readable or writable using an NBD tool via DMA. [Corresponding RAM area] XFFFC000H to XFFFE7FFH If executed using an address outside the above, the function instantly returns “ready”.
Page 628: Nbd Function Register Map
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) Figure 12-1. Image of NBD Space V850E/IA1 possible NBD dedicated interface (7 ways) unit tool NBD : Non Break Debug Caution The debug function does not operate under the following conditions. •...
Page 629: Nbd Function Protocol
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) 12.3 NBD Function Protocol The basic protocol of the NBD function is shown below. (1) Basic protocol Figure 12-2. Basic Protocol (1) On a read CLK_DBG SYNC AD0_DBG to Control Address section section AD3_DBG...
Page 630 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (2) Command packet NBD Bus Line AD3_DBG AD2_DBG AD1_DBG AD0_DBG aux3 aux2 aux1 aux0 SIZ1 SIZ0 10th 11th 12th 13th 14th 15th 16th Caution Values are for command packet maximum setup. •...
Page 631 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (d) SIZ0, SIZ1: Access data size specification SIZ1 SIZ0 Target Space Access NBD Space Access Note 1 8-bit length 8-bit length Note 1 Note 2 16-bit length Setting prohibited 32-bit length Note 2 Setting prohibited Notes 1.
Page 632: Nbd Function
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) 12.4 NBD Function 12.4.1 RAM monitoring, accessing NBD space The NBD function performs read and write operations on internal RAM data via DMA (direct memory access) for addresses in internal RAM. It also performs reading or writing to NBD space. (1) RAM monitoring The following are the commands for reading and writing to internal RAM areas from the NBD tool.
Page 633 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (2) Access to NBD space The following are the commands for reading and writing NBD space from the NBD tool. For NBD space, an access address is 12-bit fixed-length and the access data is 8-bit fixed-length. (a) Write command The address (NBD space address: 12 bits) at which a write to NBD space is to be made and the data are received from the NBD tool as a command packet.
Page 634: Event Detection Function
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) Table 12-8. Data Packet ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG Caution Read data is 8-bit fixed-length. 12.4.2 Event detection function By having a comparator (24-bit address setting) for match detection on-chip at a single point, this function detects match of the address setting registers shown below and outputs a match trigger (falling edge) to the NBD tool.
Page 635 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (b) NBD event address register (EVTU_A) The EVTU_A register sets the value of the address that is the subject of the event. NBD space address Initial value EVTU_A7 to EVAU7 EVAU6 EVAU5 EVAU4...
Page 636: Chip Id Registers (Tid0 To Tid2)
The chip ID registers (TID0 to TID2) are read-only registers. NBD space address TID0 000H • MC7 to MC0: Semiconductor manufacturer classification code NEC Electronics: 4EH NBD space address TID1 001H • FC7 to FC0: CPU classification code V850E1 CPU: 01H...
Page 637: Control Registers
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) 12.5 Control Registers (1) RAM access data buffer register L (NBDL) NBDL register operates as buffer between DMA and the NBD tool when reading or writing RAM via DMA from the NBD tool. NBDL register can be read/written in 16-bit units.
Page 638 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (3) DMA source address setting register SL (NBDMSL) NBDMSL register specifies a DMA source address. It can be written from the NBD tool and read by DMA (CPU). It can be read only in 16-bit units. Address Initial value NBDMSL...
Page 639 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (5) DMA destination address setting register DL (NBDMDL) NBDMDL register specifies a DMA destination address. It can be written from the NBD tool and read by DMA (CPU). It can be read only in 16-bit units. Address Initial value NBDMDL...
Page 640: Restrictions On Nbd
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) 12.6 Restrictions on NBD 12.6.1 General restrictions (1) CLK_DBG operates at less than half the speed of the internal system clock (f ) and is 12.5 MHz maximum. (2) If a command packet is sent during a reset period, “ready” is not returned afterwards. Reset again. 12.6.2 Restrictions related to read or write of RAM by NBD (1) Initialize DMA in user software.
Page 641: Initialization Required For Dma (2 Channels)
CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) 12.7 Initialization Required for DMA (2 Channels) (1) The DMA initialization in a setting change request must be performed by user software. (2) Assign DMA two channels in NBD. At this time, assign an NBDAD interrupt to a higher priority channel than an NBDREW interrupt. (3) Initialize registers of the channel to which the NBDAD interrupt is assigned.
Page 642 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) Examples of DMA initialization on 32-bit transfer, 16-bit transfer, and 8-bit transfer are shown below. (a) Example of 32-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0]...
Page 643 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (b) Example of 16-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0] 0x00000FFF , r24 –- DMACH0 Source Address –- st.h r24 , DSAH0[r0] 0x0000F088 ,...
Page 644 CHAPTER 12 NBD FUNCTION ( µ µ µ µ PD70F3116) (c) Example of 8-bit transfer DMA initialization -- DMA INITIAL -– 0x0000FA64 , r24 -- DMACH0 Source Address –- st.h r24 , DSAL0[r0] 0x00000FFF , r24 –- DMACH0 Source Address –- st.h r24 , DSAH0[r0] 0x0000F088 ,...
Page 645: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Features • Two 10-bit resolution on-chip A/D converters (A/D converter 0 and 1) Simultaneous sampling by two circuits is possible. • Analog input: 8 channels per circuit • On-chip A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) 10 bits ×...
Page 646 CHAPTER 13 A/D CONVERTER (6) A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) ADCR0n and ADCR1n are 10-bit registers that hold A/D conversion results (n = 0 to 7). Whenever an A/D conversion terminates, the conversion result from the successive approximation register (SAR) is loaded. RESET input sets these registers to 0000H.
Page 647 CHAPTER 13 A/D CONVERTER Figure 13-1. Block Diagram of A/D Converter 0 or 1 ANIn0 ANIn1 ANIn2 ANIn3 Comparator Sample and and D/A ANIn4 hold circuit REFn converter ANIn5 ANIn6 ANIn7 SAR (10) INTADn ADCRn0 ITRG0 Controller ADCRn1 ADCRn2 ADTRGn INTDETn ADCRn3 Trigger source switching...
Page 648 CHAPTER 13 A/D CONVERTER Figure 13-2. Block Diagram of Trigger Source Switching Circuit in Timer Trigger Mode ADTRG0 A/D converter 0 ITRG0 INTCM003 INTCM013 ADTRG1 A/D converter 1 ITRG0 INTTM00 INTTM01 ITRG0 ITRG22 ITRG21 ITRG20 ITRG12 ITRG11 ITRG10 Internal bus Caution For the selection of the trigger source in timer trigger mode, refer to 13.3 (5) A/D internal trigger selection register (ITRG0).
Page 649: Control Registers
CHAPTER 13 A/D CONVERTER 13.3 Control Registers (1) A/D scan mode registers 00 and 10 (ADSCM00, ADSCM10) The ADSCMn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operation. The ADSCMn0 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn0 register are used as the ADSCMn0H register, and the lower 8 bits are used as the ADSCMn0L register, they can be read/written in 8-bit or 1-bit units.
Page 650 CHAPTER 13 A/D CONVERTER (1/2) <15> <14> <12> <11> Address Initial value ADSCM00 ADCE0 ADCS0 ADMS0 ADPLM0 TRG2 TRG1 TRG0 SANI3 SANI2 SANI1 SANI0 ANIS3 ANIS2 ANIS1 ANIS0 FFFFF200H 0000H <15> <14> <12> <11> Address Initial value ADSCM10 ADCE1 ADCS1 ADMS1 ADPLM1 TRG2...
Page 651 CHAPTER 13 A/D CONVERTER (2/2) Bit Position Bit Name Function 7 to 4 SANI3 to Specifies conversion start analog input pin in scan mode. SANI0 These bits are ignored in select mode. SANI3 SANI2 SANI1 SANI0 Scan Start Analog Input Pin ANIn0 ANIn1 ANIn2...
Page 652 CHAPTER 13 A/D CONVERTER (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) The ADSCMn1 registers are 16-bit registers that set the conversion time of the A/D converter. The ADSCMn1 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn1 register are used as the ADSCMn1H register, and the lower 8 bits are used as the ADSCMn1L register, the ADSCMn1H register can be read/written in 8-bit or 1-bit units, and the ADSCMn1L register is read-only in 8-bit units.
Page 653 CHAPTER 13 A/D CONVERTER (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) The ADETMn registers are 16-bit registers that set voltage detection mode. In voltage detection mode, the analog input pin for which voltage detection is being performed and a reference voltage value are compared and an interrupt is set in response to the comparison result.
Page 654 CHAPTER 13 A/D CONVERTER (4) A/D conversion result registers 00 to 07 and 10 to 17 (ADCR00 to ADCR07, ADCR10 to ADCR17) The ADCR0n and ADCR1n registers are 10-bit registers that hold the results of A/D conversions (n = 0 to 7). One A/D converter is equipped with eight 10-bit registers for 8 channels, and A/D converters 0 and 1 together have sixteen 10-bit registers.
Page 655 CHAPTER 13 A/D CONVERTER The correspondence between each analog input pin and the ADCR0n and ADCR1n registers is shown below. Table 13-3. Correspondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers A/D Converter Analog Input Pin A/D Conversion Result Register A/D converter 0 ANI00 ADCR00...
Page 656 CHAPTER 13 A/D CONVERTER (5) A/D internal trigger selection register (ITRG0) The ITRG0 register is the register that switches the trigger source in timer trigger mode. The timer trigger source of A/D converters 0 and 1 can be set using the ITRG0 register. This register can be read/written in 8-bit or 1-bit units.
Page 657 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to an analog input pin (ANI0n or ANI1n) and the value of the A/D conversion result register (ADCR0n or ADCR1n) is as follows (n = 0 to 7): ADCR = INT ( ×...
Page 658: Interrupt Requests
CHAPTER 13 A/D CONVERTER 13.4 Interrupt Requests A/D converters 0 and 1 generate two kinds of interrupts. • A/D conversion termination interrupts (INTAD0, INTAD1) • Voltage detection interrupts (INTDET0, INTDET1) (1) A/D conversion termination interrupts (INTAD0, INTAD1) In A/D conversion enabled status, an A/D conversion termination interrupt is generated when a specified number of A/D conversions have terminated.
Page 659: A/D Converter Operation
CHAPTER 13 A/D CONVERTER 13.5 A/D Converter Operation 13.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the ADSCM00 Note 1 or ADSCM10 register .
Page 660: Operation Modes And Trigger Modes
CHAPTER 13 A/D CONVERTER 13.5.2 Operation modes and trigger modes Diverse conversion operations can be specified for A/D converters 0 and 1 by specifying operation modes and trigger modes. Operation modes and trigger modes are set using the ADSCM00 or ADSCM10 register. The relationship between operation modes and trigger modes is shown below.
Page 661 CHAPTER 13 A/D CONVERTER (2) Operation modes The two operation modes, which are the modes that set the ANI00 to ANI07 and ANI10 to ANI17 pins, are select mode and scan mode. These modes are set using the ADSCM00 and ADSCM10 registers. (a) Select mode Select mode A/D converts one analog input specified in the ADSCM00 or ADSCM10 register.
Page 662 CHAPTER 13 A/D CONVERTER (b) Scan mode Scan mode sequentially selects and A/D converts pins from the A/D conversion start analog input pin through the A/D conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register. It stores the A/D conversion result in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 663: Operation In A/D Trigger Mode
CHAPTER 13 A/D CONVERTER 13.6 Operation in A/D Trigger Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. 13.6.1 Operation in select mode One analog input specified in the ADSCM00 or ADSCM10 register is A/D converted at a time and the result is stored in an ADCR0n or ADCR1n register.
Page 664: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.6.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 665: Operation In A/D Trigger Polling Mode
CHAPTER 13 A/D CONVERTER 13.7 Operation in A/D Trigger Polling Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. Both select mode and scan mode are available in A/D trigger polling mode. Since the ADCS0 or ADCS1 bit of the ADSCM00 or ADSCM10 register remains 1 after an INTAD0 or INTAD1 interrupt in this mode, it is not necessary to write 1 in the ADCE0 or ADCE1 bit as an A/D conversion restart operation.
Page 666: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.7.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7).
Page 667: Operation In Timer Trigger Mode
CHAPTER 13 A/D CONVERTER 13.8 Operation in Timer Trigger Mode The A/D converter can set an interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a conversion trigger for up to 8 channels (a total of 16 channels in 2 circuits) of analog input (ANI00 to ANI07, ANI10 to ANI17).
Page 668: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.8.2 Operation in scan mode Using the interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a trigger, the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 669: Operation In External Trigger Mode
CHAPTER 13 A/D CONVERTER 13.9 Operation in External Trigger Mode In external trigger mode, analog input (ANI00 to ANI07, ANI10 to ANI17) is A/D converted on ADTRG0 or ADTRG1 pin input timing. The valid edge of an external input signal in external trigger mode can be specified as a rising edge, a falling edge, or a rising or falling edge in the ES21 or ES20 bit of the INTM1 register for A/D converter 0 and in the ES31 or ES30 bit of the INTM1 register for A/D converter 1.
Page 670: Operation In Scan Mode
CHAPTER 13 A/D CONVERTER 13.9.2 Operation in scan mode Using an ADTRG0 or ADTRG1 signal as a trigger, pins from the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 671: Precautions On Operation
CHAPTER 13 A/D CONVERTER 13.10 Precautions On Operation 13.10.1 Stopping A/D conversion operation If 0 is written in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register during A/D conversion operation, it stops A/D conversion operation and an A/D conversion result is not stored in the ADCR0n or ADCR1n register (n = 0 to 7).
Page 672: Compare Match Interrupt In Timer Trigger Mode
CHAPTER 13 A/D CONVERTER 13.10.5 Compare match interrupt in timer trigger mode A TM0n timer 0 register underflow interrupt (INTTM00 or INTTM01) and CM003 or CM013 interrupt (INTCM003 or INTCM013) is an A/D conversion start trigger that starts conversion operation (n = 0, 1). At this time, the CM003 or CM013 match interrupt (INTCM003 or INTCM013) also functions as a compare register match interrupt for the CPU.
Page 673: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.11 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 674 CHAPTER 13 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 675 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale − 3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 13-19. Full-Scale Error Full-scale error (n = 0, 1) –0...
Page 676 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 677: Chapter 14 Port Functions
CHAPTER 14 PORT FUNCTIONS 14.1 Features • Input dedicated ports: 8 I/O ports: 75 • Ports alternate as I/O pins of other peripheral functions • Input or output can be specified in bit units 14.2 Basic Configuration of Ports The V850E/IA1 has a total of 83 on-chip input/output ports (ports 0 to 4, DH, DL, CS, CT, CM), of which 8 are input-only ports.
Page 678 CHAPTER 14 PORT FUNCTIONS Port Name Pin Name Port Function Function in Control Mode Block Type Port 0 P00 to P07 8-bit input NMI input, real-time pulse unit (RPU) output stop signal input, external interrupt input, A/D converter (ADC) external trigger input Port 1 P10 to P15 6-bit I/O...
Page 679 CHAPTER 14 PORT FUNCTIONS (2) Functions of each port pin after reset and registers that set port or control mode Port Name Pin Name Pin Function After Reset Mode-Setting Register Single-Chip Single-Chip ROMless ROMless Mode 0 Mode 1 Mode 0 Mode 1 −...
Page 680 CHAPTER 14 PORT FUNCTIONS Port Name Pin Name Pin Function After Reset Mode-Setting Register Single-Chip Single-Chip ROMless ROMless Mode 0 Mode 1 Mode 0 Mode 1 Port 4 P40/SI0 P40 (Input mode) PMC4 P41/SO0 P41 (Input mode) P42/SCK0 P42 (Input mode) P43/SI1 P43 (Input mode) P44/SO1...
Page 681 CHAPTER 14 PORT FUNCTIONS (3) Port block diagrams Figure 14-1. Type A Block Diagram PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 682 CHAPTER 14 PORT FUNCTIONS Figure 14-2. Type B Block Diagram PMCmn PMmn PORT Address Noise elimination Input signal in Edge detection control mode Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 683 CHAPTER 14 PORT FUNCTIONS Figure 14-3. Type C Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 684 CHAPTER 14 PORT FUNCTIONS Figure 14-4. Type D Block Diagram MODE0 to MODE2 PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number Figure 14-5. Type E Block Diagram PMmn PORT Address Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 685 CHAPTER 14 PORT FUNCTIONS Figure 14-6. Type F Block Diagram Noise elimination Address Input signal in Edge detection control mode Figure 14-7. Type G Block Diagram PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 686 CHAPTER 14 PORT FUNCTIONS Figure 14-8. Type H Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 687 CHAPTER 14 PORT FUNCTIONS Figure 14-9. Type J Block Diagram MODE0 to MODE2 PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 688 CHAPTER 14 PORT FUNCTIONS Figure 14-10. Type M Block Diagram SCKx, ASCKy output enable signal PMCmn PMmn Output signal in control mode PORT Address Input signal in control mode Remark mn: 34, 37, 42, 45 0 (When mn = 42) 1 (When mn = 45) 1 (When mn = 34) 2 (When mn = 37)
Page 689 CHAPTER 14 PORT FUNCTIONS Figure 14-11. Type N Block Diagram PFCmn PMCmn PMmn Output signal in PORT control mode Address Input signal in Noise elimination control mode Edge detection Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 690 CHAPTER 14 PORT FUNCTIONS Figure 14-12. Type O Block Diagram MODE0 to MODE2 I/O control PMCmn PMmn Output signal in control mode PORT Address Input signal in control mode I/O control Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 691 CHAPTER 14 PORT FUNCTIONS Figure 14-13. Type P Block Diagram MODE0 to MODE2 I/O control PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14492EJ3V0UD...
Page 692: Pin Functions Of Each Port
CHAPTER 14 PORT FUNCTIONS 14.3 Pin Functions of Each Port 14.3.1 Port 0 Port 0 is an 8-bit input dedicated port in which all pins are fixed for input. Address Initial value FFFFF400H Undefined Besides functioning as an input port, in control mode, it also can operate as the real-time pulse unit (RPU) output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input.
Page 693: Port 1
CHAPTER 14 PORT FUNCTIONS 14.3.2 Port 1 Port 1 is a 6-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value – – FFFFF402H Undefined Bit Position Bit Name Function 5 to 0 I/O port (n = 5 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU) I/O and...
Page 694 CHAPTER 14 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 6 and 7. Caution The PMC11, PMC12, PMC14, and PMC15 bits also serve as external interrupts (INTP100, INTP101, INTP110, and INTP111).
Page 695 CHAPTER 14 PORT FUNCTIONS (c) Port 1 function control register (PFC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits other than 0 and 3. Caution When port mode is specified by the port 1 mode control register (PMC1), the setting of this register is invalid.
Page 696: Port 2
CHAPTER 14 PORT FUNCTIONS 14.3.3 Port 2 Port 2 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF404H Undefined Bit Position Bit Name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the real-time pulse unit (RPU) I/O and external interrupt request input.
Page 697 CHAPTER 14 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read/written in 8-bit or 1-bit units. Caution The PMC20, PMC25, and PMC26 bits also serve as external interrupts (INTP20, INTP25, and INTP30). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control register (xxICn)).
Page 698 CHAPTER 14 PORT FUNCTIONS (c) Port 2 function control register (PFC2) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 0, 5, and 6. Caution When port mode is specified by the port 2 mode control register (PMC2), the setting of this register is invalid.
Page 699: Port 3
CHAPTER 14 PORT FUNCTIONS 14.3.4 Port 3 Port 3 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF406H Undefined Bit Position Bit Name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (UART0 to UART2) I/O.
Page 700 CHAPTER 14 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read/written in 8-bit or 1-bit units. Address Initial value PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF446H Bit Position Bit Name Function PMC37 Specifies operation mode of P37 pin.
Page 701: Port 4
CHAPTER 14 PORT FUNCTIONS 14.3.5 Port 4 Port 4 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value FFFFF408H Undefined Bit Position Bit Name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (CSI0, CSI1, FCAN) I/O.
Page 702 CHAPTER 14 PORT FUNCTIONS (b) Port 4 mode control register (PMC4) This register can be read/written in 8-bit or 1-bit units. Address Initial value PMC4 PMC47 PMC46 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF448H Bit Position Bit Name Function PMC47 Specifies operation mode of P47 pin.
Page 703: Port Dh
CHAPTER 14 PORT FUNCTIONS 14.3.6 Port DH Port DH is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 FFFFF006H Undefined Bit Position Bit Name Function 7 to 0...
Page 704 CHAPTER 14 PORT FUNCTIONS (b) Port DH mode control register (PMCDH) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 FFFFF046H 00H/FFH Note 00H: Single-chip mode 0 FFH: Single-chip mode 1, ROMless mode 0 or 1 Bit Position Bit Name...
Page 705: Port Dl
CHAPTER 14 PORT FUNCTIONS 14.3.7 Port DL Port DL is a 16-bit or 8-bit I/O port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit I/O port that can specify input or output in 1-bit units.
Page 706 CHAPTER 14 PORT FUNCTIONS (a) Port DL mode register (PMDL) The PMDL register can be read/written in 16-bit units. When using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, it can be read/written in 8-bit or 1-bit units.
Page 707: Port Cs
CHAPTER 14 PORT FUNCTIONS 14.3.8 Port CS Port CS is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 FFFFF008H Undefined Bit Position Bit Name Function 7 to 0...
Page 708 CHAPTER 14 PORT FUNCTIONS (2) Setting in I/O mode and control mode Port CS is set in I/O mode using the port CS mode register (PMCS). In control mode, it is set using the port CS mode control register (PMCCS). (a) Port CS mode register (PMCS) This register can be read/written in 8-bit or 1-bit units.
Page 709: Port Ct
CHAPTER 14 PORT FUNCTIONS 14.3.9 Port CT Port CT is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 FFFFF00AH Undefined Bit Position Bit Name Function 7 to 0...
Page 710 CHAPTER 14 PORT FUNCTIONS (b) Port CT mode control register (PMCCT) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 FFFFF04AH 00H/53H Note 00H: Single-chip mode 0 53H: Single-chip mode 1, ROMless mode 0 or 1 Bit Position Bit Name Function...
Page 711: Port Cm
CHAPTER 14 PORT FUNCTIONS 14.3.10 Port CM Port CM is a 5-bit I/O port in which input or output can be specified in 1-bit units. Address Initial value – – – PCM4 PCM3 PCM2 PCM1 PCM0 FFFFF00CH Undefined Bit Position Bit Name Function 4 to 0...
Page 712 CHAPTER 14 PORT FUNCTIONS (b) Port CM mode control register (PMCCM) This register can be read/written in 8-bit or 1-bit units. Note Address Initial value PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 FFFFF04CH 00H/0FH Note 00H: Single-chip mode 0 0FH: Single-chip mode 1, ROMless mode 0 or 1 Bit Position Bit Name Function...
Page 713: Noise Eliminator
CHAPTER 14 PORT FUNCTIONS 14.4 Noise Eliminator 14.4.1 Interrupt pins A timing controller to guarantee the noise elimination times shown below is added to the pins that operate as NMI and valid edge inputs in port control mode. Signal input that changes in less than these elimination times is not accepted internally.
Page 714: Timer 10, Timer 11, Timer 3 Input Pins
CHAPTER 14 PORT FUNCTIONS 14.4.2 Timer 10, timer 11, timer 3 input pins Noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10, timer 11, and timer 3. A signal input that changes in less than these elimination times is not accepted internally. Noise Elimination Time Sampling Clock Timer 10...
Page 715 CHAPTER 14 PORT FUNCTIONS Figure 14-14. Example of Noise Elimination Timing Noise elimination clock Input signal 2 clocks 2 clocks 3 clocks 3 clocks 4 clocks 4 clocks 5 clocks 5 clocks Internal signal Timers 1 to 3 rising edge detection Timers 1 to 3 falling edge detection Caution If there are three or less noise elimination clocks while the timers 1 to 3 input signals...
Page 716 CHAPTER 14 PORT FUNCTIONS (1) Timer 10 noise elimination time selection register (NRC10) The NRC10 register is used to set the clock source of timer 10 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Address Initial value NRC10...
Page 717 CHAPTER 14 PORT FUNCTIONS (3) Timer 3 noise elimination time selection register (NRC3) The NRC3 register is used to set the clock source of timer 3 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Address Initial value NRC3...
Page 718: Timer 2 Input Pins
CHAPTER 14 PORT FUNCTIONS 14.4.3 Timer 2 input pins A noise eliminator using analog filtering and digital filtering using clock sampling are added to the timer 2 input pins. A signal input that changes in less than these elimination times is not accepted internally. Analog Filter Noise Digital Filter Elimination Time...
Page 719 CHAPTER 14 PORT FUNCTIONS (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) The FEMn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination times and the input valid edge. These registers can be read/written in 8-bit or 1-bit units.
Page 720 CHAPTER 14 PORT FUNCTIONS (2/2) Bit Position Bit Name Function 3, 2 EDGE01n, Specifies the INTP2n pin valid edge. EDGE00n EDGE01n EDGE00n Operation Note Interrupt due to INTCC2n Rising edge Falling edge Both rising and falling edges Note Specify when selecting INTCC2n according to match of TM20, TM21 and sub-channel compare registers (TMS01n, TMS00n bit settings) (n = 0 to 5).
Page 721: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION When a low level is input to the RESET pin, there is a system reset and each hardware item of the V850E/IA1 is initialized to its initial status. When the RESET pin changes from low level to high level, reset status is released and the CPU starts program execution.
Page 722 CHAPTER 15 RESET FUNCTION (1) Reset signal acknowledgment RESET Analog Analog Analog delay delay delay Elimination as noise Internal system Note reset signal Reset acknowledgment Reset release Note The internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET pin.
Page 723: Initialization
CHAPTER 15 RESET FUNCTION 15.3 Initialization Initialize the contents of each register as needed within a program. Table 15-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O after reset. Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/6) On-Chip Hardware Register Name Initial Value After Reset...
Page 724 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Interrupt/exception Signal edge selection register n (SESA1n) (n = 10, 11) peripheral control function Valid edge selection register (SESC) Timer 2 input filter mode register n (FEMn) (n = 0 to 5)
Page 725 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 2 Timer 2 clock stop register 0 (STOPTE0) 0000H peripheral Timer 2 clock stop register 0L (STOPTE0L) Timer 2 clock stop register 0H (STOPTE0H) Timer 2 count clock/control edge selection register 0 (CSE0) 0000H...
Page 726 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (4/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 3 Valid edge selection register (SESC) peripheral Timer 3 clock selection register (PRM03) Timer 3 noise elimination time selection register (NRC3) Timer 4 Timer 4 (TM4)
Page 727 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (5/6) On-Chip Hardware Register Name Initial Value After Reset On-chip Serial interface Transmission shift register Ln (TXSLn) (n = 1, 2) Undefined peripheral function (UART1, Prescaler mode register n (PRSMn) (n = 1, 2)
Page 728 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (6/6) On-Chip Hardware Register Name Initial Value After Reset On-chip A/D converter A/D voltage detection mode register n (ADETMn) (n = 0, 1) 0000H peripheral A/D voltage detection mode register nL (ADETMnL) (n = 0, 1)
Page 729: Chapter 16 Flash Memory ( Μ Μ Μ Μ Pd70F3116)
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) The µ PD70F3116 is the flash memory version of the V850E/IA1 and it has an on-chip 256 KB flash memory configured as two 128 KB areas. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions.
Page 730 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) When the flash programming adapter (FA-144GJ-8EU) is used for writing, connect the pins as follows. Table 16-1. Connection of V850E/IA1 Flash Programming Adapter (FA-144GJ-8EU) FA-144GJ-8EU V850E/IA1 Silk Name UART0 CSI0 Pin Name Pin No.
Page 731: Programming Environment
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850E/IA1. Figure 16-1. Environment for Writing Program to Flash Memory Regulator RS-232-C Axxxx Bxxxxx Regulator...
Page 732 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) (2) CSI0 Transfer rate: up to 2 MHz (MSB first) Figure 16-3. Communication with Dedicated Flash Programmer (CSI0) Regulator Regulator Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET RESET V850E/IA1 Dedicated flash programmer SCK0 Caution Supply the operating clock of the V850E/IA1 via the oscillator configured on the...
Page 733: Pin Connection
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode (single-chip modes 0, 1 or ROMless modes 0, 1) to the flash memory programming mode.
Page 734 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) Figure 16-6. Conflict of Signals (Serial Interface Input Pin) V850E/IA1 Conflict of signals Dedicated flash programmer connection pin Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs.
Page 735: Reset Pin
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 736: Power Supply
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.5.8 Power supply Supply the power supply (V , AV , AV , AV , AV , CV , and CV ) the same as in REF0 REF1 Note normal operation mode. Connect V and GND of the dedicated flash programmer to V , and V of the dedicated flash programmer is provided with a power supply monitoring function).
Page 737: Flash Memory Programming Mode
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/IA1 in the flash memory programming mode. To switch to this mode, set the MODE0, MODE1, MODE2, and V pins before canceling reset.
Page 738: Communication Commands
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.6.4 Communication commands The V850E/IA1 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/IA1 is called a “command”. The response signal sent from the V850E/IA1 to the dedicated flash programmer is called the “response command”.
Page 739: Flash Memory Programming By Self-Programming
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) The V850E/IA1 sends back response commands for the commands issued from the dedicated flash programmer. The following shows the response commands the V850E/IA1 sends out. Table 16-5. Response Commands Response Command Name Function ACK (acknowledge) Acknowledges command/data, etc.
Page 740: Self-Programming Function
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.2 Self-programming function The µ PD70F3116 provides self-programming functions, as shown in Table 16-6. By combining these functions, erasing/writing flash memory becomes possible. Table 16-6. Function List Type Function Name Function Erase Area erase...
Page 741: Hardware Environment
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) The self-programming interface is outlined below. Figure 16-13. Outline of Self-Programming Interface Application program RAM parameter Entry program Self-programming interface Device internal processing Flash-memory manipulation Flash memory 16.7.4 Hardware environment To write or erase the flash memory, a high voltage must be applied to the V pin.
Page 742 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) The voltage applied to the V pin must satisfy the following conditions: • Hold the voltage applied to the V pin at 0 V in the normal operation mode and hold the V voltage only while the flash memory is being manipulated.
Page 743: Software Environment
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 16-7. Software Environmental Conditions Item Description Location of entry Execute the entry program in memory other than the block 0 space and flash memory area.
Page 744: Self-Programming Function Number
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 16-8.
Page 745: Calling Parameters
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 16-9.
Page 746: Contents Of Ram Parameters
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 16-10.
Page 747: Errors During Self-Programming
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 16-11.
Page 748: Area Number
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.11 Area number The area numbers and memory map of the µ PD70F3116 are shown below. Figure 16-16. Area Configuration 0 x 3 F F F F (End address of area 1) Area 1 (128 KB) 0 x 2 0 0 0 0 (Start address of area 1)
Page 749: Flash Programming Mode Control Register (Flpmc)
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.12 Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only).
Page 750 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence. <1> Disable interrupts (set the NP bit and ID bit of the PSW to 1). <2>...
Page 751: Calling Device Internal Processing
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set.
Page 752 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area.
Page 753 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) (5) Internal manipulation setup parameter If the self-programming mode is switched to the normal operation mode, the µ PD70F3116 must wait for 100 µ s before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to “130”...
Page 754: Erasing Flash Memory Flow
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.14 Erasing flash memory flow The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-17.
Page 755: Continuous Writing Flow
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.15 Continuous writing flow The procedure to write data all at once to the flash memory by using the function to continuously write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure.
Page 756: Internal Verify Flow
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.16 Internal verify flow The procedure of internal verification is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-19. Internal Verify Flow Internal verify Set RAM parameter.
Page 757: Acquiring Flash Information Flow
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.17 Acquiring flash information flow The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-20.
Page 758: Self-Programming Library
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.7.18 Self-programming library V850 Series Flash Memory Self-Programming User’s Manual is available for reference when executing self- programming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program.
Page 759 CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) The configuration of the self-programming library is outlined below. Figure 16-22. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program RAM parameter Self-programming interface Device internal processing Flash memory manipulation Flash memory User’s Manual U14492EJ3V0UD...
Page 760: How To Distinguish Flash Memory And Mask Rom Versions
CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3116) 16.8 How to Distinguish Flash Memory and Mask ROM Versions It is possible to distinguish a flash memory version ( µ PD70F3116) and a mask ROM version ( µ PD703116) by means of software, using the methods shown below.
Page 761: Chapter 17 Turning On/Off Power
CHAPTER 17 TURNING ON/OFF POWER The V850E/IA1 has three types of power supply pins: 3.3 V power supply pins for internal units (V and CV ), 5 Note V power supply pins for external pins (V and AV ), and a flash programming power supply pin (V This chapter explains the I/O pin status when power is turned ON/OFF.
Page 762 CHAPTER 17 TURNING ON/OFF POWER [Other timing] • If power is supplied to the V and AV pins before the voltage on the V pins rises to the level at which the Note operation is guaranteed (3.0 to 3.6 V), the status of the I/O pin is undefined until the voltage on the V reaches 3.0 V.
Page 763: Chapter 18 Electrical Specifications
CHAPTER 18 ELECTRICAL SPECIFICATIONS 18.1 Normal Operation Mode = 25° ° ° ° C) Absolute Maximum Ratings (T Parameter Symbol Conditions Ratings Unit −0.5 to +4.6 Power supply voltage −0.5 to +7.0 −0.5 to +4.6 −0.5 to +0.5 −0.5 to V Note 1 + 0.5 −0.5 to +0.5...
Page 764 CHAPTER 18 ELECTRICAL SPECIFICATIONS Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each power supply voltage. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins ( µ PD70F3116 only) Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written.
Page 765 CHAPTER 18 ELECTRICAL SPECIFICATIONS = 25° ° ° ° C, V Capacitance (T = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance = 1 MHz I/O capacitance Unmeasured pins returned to 0 V. Output capacitance Operating Conditions Operation Mode Internal System Clock Frequency (f Operating Ambient...
Page 766 CHAPTER 18 ELECTRICAL SPECIFICATIONS µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = − − − − 40 to +85° ° ° ° C: Clock Oscillator Characteristics (T = − − − − 40 to +110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1)) (a) Ceramic resonator or crystal resonator connection Parameter Symbol...
Page 767 CHAPTER 18 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constant (a) Ceramic resonator = − − − − 40 to +85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), (i) Murata Mfg. Co., Ltd (T = − − − − 40 to +110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1)) Type Product Name Oscillation...
Page 768 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to +85°C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), DC Characteristics (T = –40 to +110°C: µ µ µ µ PD703116(A1), 70F3116(A1), = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V) (1/2) Parameter...
Page 769 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to +85°C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), DC Characteristics (T = –40 to +110°C: µ µ µ µ PD703116(A1), 70F3116(A1), = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V) (2/2) Parameter...
Page 770 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), Data Retention Characteristics (T = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1)) Parameter Symbol Conditions...
Page 771 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), AC Characteristics (T = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 772 CHAPTER 18 ELECTRICAL SPECIFICATIONS AC test output test points Pins other than (b) below 0.8V 0.8V Test points 0.2V 0.2V AD0_DBG to AD3_DBG, TRIG_DBG pins ( µ µ µ µ PD70F3116 only) 0.8V 0.8V Test points 0.2V 0.2V Load conditions (Device under test) = 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,...
Page 773 CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (1/2) = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 774 CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (2/2) <1> <2> <3> <5> <4> (PLL mode) <1> <2> <3> <4> <5> (direct mode) <11> <11> CLKOUT (output) <9> <10> <7> <8> <6> (2) Output waveform (except for CLKOUT) = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110°...
Page 775 CHAPTER 18 ELECTRICAL SPECIFICATIONS (3) Reset timing = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 776 CHAPTER 18 ELECTRICAL SPECIFICATIONS (4) Multiplex bus timing = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), (a) CLKOUT asynchronous (T = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 777 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), (b) CLKOUT synchronous (T = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 778 CHAPTER 18 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <45> A16 to A23 (output) <19> <49> <50> <46> Hi-Z AD0 to AD15 (I/O) Address Data <47> <47> <16> <17> <22> ASTB (output) <27> <48> <24> <18> <48>...
Page 779 CHAPTER 18 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <45> A16 to A23 (output) <51> AD0 to AD15 (I/O) Address Data <47> <47> <16> <17> ASTB (output) <27> <24> <48> <48> <28> <21> <29> <30> LWR (output) UWR (output) <26>...
Page 780 CHAPTER 18 ELECTRICAL SPECIFICATIONS (e) Bus hold CLKOUT (output) <54> <54> <55> <39> HLDRQ (input) <56> <56> <43> <44> HLDAK (output) <41> <42> <40> <57> Hi-Z A16 to A23 (output) Data Hi-Z AD0 to AD15 (I/O) Hi-Z ASTB (output) Hi-Z RD (output) LWR (output), UWR (output) User’s Manual U14492EJ3V0UD...
Page 781 CHAPTER 18 ELECTRICAL SPECIFICATIONS (5) Interrupt timing = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 782 CHAPTER 18 ELECTRICAL SPECIFICATIONS (6) Timer input timing = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 783 CHAPTER 18 ELECTRICAL SPECIFICATIONS (7) Timer operating frequency = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 784 CHAPTER 18 ELECTRICAL SPECIFICATIONS (8) CSI timing (2/2) <66> <68> <67> SCKn (I/O) <70> <69> (input) Input data <71> <72> (output) Output data Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1 (9) UART0 timing = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110°...
Page 785 CHAPTER 18 ELECTRICAL SPECIFICATIONS (10) UART1, UART2 timing (1/2) (a) Clocked master mode = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), = –40 to + + + + 110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 786 CHAPTER 18 ELECTRICAL SPECIFICATIONS (10) UART1, UART2 timing (2/2) <73> <75> <74> ASCKn (I/O) <77> <76> RXDn (input) Input data <78> <79> TXDn (output) Output data Remark n = 1, 2 User’s Manual U14492EJ3V0UD...
Page 787 CHAPTER 18 ELECTRICAL SPECIFICATIONS (11) NBD timing ( µ µ µ µ PD70F3116 only) = 0 to +40°C, V = CV = 3.0 to 3.6 V, V = 5 V ±0.5 V, V = CV = 0 V, output pin load capacitance: C = 100 pF) Parameter Symbol...
Page 788 CHAPTER 18 ELECTRICAL SPECIFICATIONS = –40 to + + + + 85° ° ° ° C: µ µ µ µ PD703116, 703116(A), 70F3116, 70F3116(A), A/D Converter Characteristics (T = − − − − 40 to +110° ° ° ° C: µ µ µ µ PD703116(A1), 70F3116(A1), = 5 V ±...
Page 789: Flash Memory Programming Mode ( Μ Μ Μ Μ Pd70F3116 Only)
CHAPTER 18 ELECTRICAL SPECIFICATIONS 18.2 Flash Memory Programming Mode ( µ µ µ µ PD70F3116 only) = 0 to 70° ° ° ° C (during rewrite), Basic Characteristics (T = − − − − 40 to +85° ° ° ° C (except during rewrite): µ µ µ µ PD70F3116, 70F3116(A), = −...
Page 790 CHAPTER 18 ELECTRICAL SPECIFICATIONS = 0 to 70° ° ° ° C, V Serial Write Operation Characteristics (T = CV = 3.0 to 3.6 V, = 5 V ± ± ± ± 0.5 V, V = CV = 0 V) Parameter Symbol Conditions...
Page 791: Chapter 19 Package Drawing
CHAPTER 19 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 792: Chapter 20 Recommended Soldering Conditions
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 20-1. Surface Mounting Type Soldering Conditions µ...
Page 793: Appendix A Notes On Target System Design
APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system based on this configuration.
Page 794: Appendix B Register Index
APPENDIX B REGISTER INDEX (1/11) Symbol Register Name Unit Page ADCR00 A/D conversion result register 00 ADCR01 A/D conversion result register 01 ADCR02 A/D conversion result register 02 ADCR03 A/D conversion result register 03 ADCR04 A/D conversion result register 04 ADCR05 A/D conversion result register 05 ADCR06...
Page 795 APPENDIX B REGISTER INDEX (2/11) Symbol Register Name Unit Page ASIM10 Asynchronous serial interface mode register 10 UART1 ASIM11 Asynchronous serial interface mode register 11 UART1 ASIM20 Asynchronous serial interface mode register 20 UART2 ASIM21 Asynchronous serial interface mode register 21 UART2 ASIS0 Asynchronous serial interface status register 0...
Page 796 APPENDIX B REGISTER INDEX (3/11) Symbol Register Name Unit Page CANIC1 Interrupt control register INTC CANIC2 Interrupt control register INTC CANIC3 Interrupt control register INTC CC100 Capture/compare register 100 CC101 Capture/compare register 101 CC10IC0 Interrupt control register INTC CC10IC1 Interrupt control register INTC CC110 Capture/compare register 110...
Page 797 APPENDIX B REGISTER INDEX (4/11) Symbol Register Name Unit Page CM011 Compare register 011 CM012 Compare register 012 CM013 Compare register 013 CM03IC0 Interrupt control register INTC CM03IC1 Interrupt control register INTC CM100 Compare register 100 CM101 Compare register 101 CM10IC0 Interrupt control register INTC...
Page 798 APPENDIX B REGISTER INDEX (5/11) Symbol Register Name Unit Page CVSE40 Timer 2 sub-channel 4 sub capture/compare register CVSE50 Timer 2 sub-channel 5 capture/compare register DADC0 DMA addressing control register 0 DMAC DADC1 DMA addressing control register 1 DMAC DADC2 DMA addressing control register 2 DMAC DADC3...
Page 799 APPENDIX B REGISTER INDEX (6/11) Symbol Register Name Unit Page DTFR3 DMA trigger factor register 3 DMAC DTM00 Dead-time timer 00 DTM01 Dead-time timer 01 DTM02 Dead-time timer 02 DTM10 Dead-time timer 10 DTM11 Dead-time timer 11 DTM12 Dead-time timer 12 DTRR0 Dead-time timer reload register 0 DTRR1...
Page 800 APPENDIX B REGISTER INDEX (7/11) Symbol Register Name Unit Page M_DATAn0 to CAN message data registers n0 to n7 (n = 00 to 31) FCAN M_DATAn7 M_DLC00 to CAN message data length registers 00 to 31 FCAN M_DLC31 M_IDH00 to CAN message ID registers H00 to H31 FCAN M_IDH31...
Page 801 APPENDIX B REGISTER INDEX (8/11) Symbol Register Name Unit Page Port 4 Port Port CM Port Port CS Port Port CT Port Port DH Port Port DL Port PDLH Port DLH Port PDLL Port DLL Port PFC1 Port 1 function control register Port PFC2 Port 2 function control register...
Page 802 APPENDIX B REGISTER INDEX (9/11) Symbol Register Name Unit Page PRM10 Prescaler mode register 10 PRM11 Prescaler mode register 11 PRSCM1 Prescaler compare register 1 UART1 PRSCM2 Prescaler compare register 2 UART2 PRSCM3 Prescaler compare register 3 CSI0, CSI1 PRSM1 Prescaler mode register 1 UART1 PRSM2...
Page 803 APPENDIX B REGISTER INDEX (10/11) Symbol Register Name Unit Page SOTBF1 Clocked serial interface initial transmission buffer register 1 CSI1 SOTBFL0 Clocked serial interface initial transmission buffer register L0 CSI0 SOTBFL1 Clocked serial interface initial transmission buffer register L1 CSI1 SOTBL0 Clocked serial interface transmission buffer register L0 CSI0...
Page 804 APPENDIX B REGISTER INDEX (11/11) Symbol Register Name Unit Page TMC01H Timer control register 01H TMC01L Timer control register 01L TMC10 Timer control register 10 TMC11 Timer control register 11 TMC30 Timer control register 30 TMC31 Timer control register 31 TMC4 Timer control register 4 TMIC0...
Page 805: Appendix C Instruction Set List
APPENDIX C INSTRUCTION SET LIST C.1 Functions (1) Symbols used in operand descriptions Symbol Explanation reg1 General-purpose register (Used as source register) reg2 General-purpose register (Usually used as destination register. Used as source register in some instructions.) reg3 General-purpose register (Usually stores remainder of division result or higher 32 bits of multiplication result.) bit#3 3-bit data for bit number specification...
Page 806 APPENDIX C INSTRUCTION SET LIST (3) Symbols used in operations Symbol Explanation ← Assignment GR [ ] General-purpose register SR [ ] System register zero-extend (n) Zero-extend n to word length. sign-extend (n) Sign-extend n to word length. load-memory (a, b) Read data of size “b”...
Page 807 APPENDIX C INSTRUCTION SET LIST (5) Symbols used in flag operations Symbol Explanation (Blank) No change Clear to 0. × Set or cleared according to result. Previously saved value is restored. (6) Condition codes Condition Name Condition Code Condition Expression Explanation (cond) (cccc)
Page 808: Instruction Set (Alphabetical Order)
APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (Alphabetical Order) (1/5) Mnemonic Operands Opcode Operation Execution Clock Flags × × × × r r r r r 0 0 1 1 1 0 R R R R R GR[reg2] ← GR[reg2] + GR[reg1] reg1, reg2 ×...
Page 809 APPENDIX C INSTRUCTION SET LIST (2/5) Mnemonic Operands Opcode Operation Execution Clock Flags sp ← sp + zero-extend (imm5 logically shift left by 2) DISPOSE imm5, list12 0 0 0 0 0 1 1 0 0 1 i i i i i L GR[reg in list12] ←...
Page 810 APPENDIX C INSTRUCTION SET LIST (3/5) Mnemonic Operands Opcode Operation Execution Clock Flags adr ← GR[reg1] + sign-extend (disp16) LD.W disp16[reg1], Note 11 r r r r r 1 1 1 0 0 1 R R R R R GR[reg2] ← Load-memory (adr, Word) reg2 d d d d d d d d d d d d d d d 1 Note 8...
Page 811 APPENDIX C INSTRUCTION SET LIST (4/5) Mnemonic Operands Opcode Operation Execution Clock Flags RETI if PSW.EP = 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 ← EIPC then PC 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 PSW ←...
Page 812 APPENDIX C INSTRUCTION SET LIST (5/5) Mnemonic Operands Opcode Operation Execution Clock Flags r r r r r 0 0 0 0 1 1 1 d d d d adr ← ep + zero-extend (disp5) SLD.HU disp5[ep], Note 9 GR[reg2] ← zero-extend (Load-memory (adr, reg2 Notes 18, 20 Halfword))
Page 813 APPENDIX C INSTRUCTION SET LIST Notes 1. dddddddd is the higher 8 bits of disp9. 4 if there is an instruction to overwrite the contents of the PSW immediately before If there is no wait state (3 + number of read access wait states) n is the total number of load registers in list12.
Page 814: Appendix D Index
APPENDIX D INDEX 2-frame continuous reception buffer registers ASIM0..............418 1, 2.................454 ASIM10, ASIM20 ........... 449 2-frame continuous transmission shift registers ASIM11, ASIM21 ........... 451 1, 2.................457 ASIS0 ..............421 ASIS1, ASIS2 ............452 assembler-reserved register........64 A/D conversion result registers 00 to 07 and ASTB ...............
Page 815 APPENDIX D INDEX BRG3..............516 CAN message status registers 00 to 31 ....562 BRGC0 ..............440 CAN message time stamp registers 00 to 31 ..555 BSC ............... 117 CAN sleep mode ........... 541, 614 buffer registers CM00 to CM02, CM10 to CM12..232 CAN status set/clear registers 00 to 31 ....
Page 816 APPENDIX D INDEX CKSEL ..............56 compare registers 100, 110........304 CKSR0..............439 compare registers 101, 111........304 CLK_DBG ..............58 continuous transmission operation ......429 CLKOUT ..............53 control field ............534 clock control register..........208 conversion time ............. 676 clock generation function ........205 CPU.................
Page 817 APPENDIX D INDEX description of pin functions ........48 ESO0, ESO1 ............48 DETIC0, DETIC1 ........... 179 event detection function ........634 device internal processing ........740 EVTU_A ..............635 differential linearity error ........675 EVTU_C ..............634 direct mode............ 206, 212 exception status flag..........
Page 818 APPENDIX D INDEX IDLE mode............. 212, 220 M_DATAn0 to M_DATAn7 (n = 00 to 31) ....556 idle state insertion function ........127 M_DLC00 to M_DLC31 ......... 550 illegal opcode definition .........197 M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31 . 558 image ...............70 M_STAT00 to M_STAT31 ........
Page 819 APPENDIX D INDEX operation in A/D trigger mode........ 663 PLL mode............206, 212 operation in A/D trigger polling mode ....665 PM1............... 693 operation in external trigger mode ......669 PM2............... 696 operation in timer trigger mode......667 PM3............... 699 operation mode specification........
Page 820 APPENDIX D INDEX port DL mode control register ........706 port DL mode register ..........706 quantization error........... 674 port functions ............677 ports.................39 power save control..........212 r0 to r31 ..............64 power save control register........216 RAM ................ 38 power save mode register........215 RAM access data buffer registers H, HL, HU ..
Page 821 APPENDIX D INDEX sequential data read ..........622 TBSTATE0, TBSTATE0H, TBSTATE0L ....355 serial I/O shift registers 0, 1........498 TCLR10, TCLR11............ 49 serial I/O shift registers L0, L1 ....... 499 TCLR2, TCLR3 ............50 serial interface ..........39, 414 TCRE0, TCRE0H, TCRE0L .........
Page 822 APPENDIX D INDEX timer connection function ........412 TUC00, TUC01............241 timer connection selection register 0 .....413 TUM0, TUM1 ............308 timer control register 30 .........384 turning off power............ 761 timer control register 31 .........386 turning on power............ 761 timer control register 4 ...........408 two-cycle transfer ..........
Page 823: Appendix E Revision History
APPENDIX E REVISION HISTORY The following table shows the revision history up to the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/10) Edition Major Revision from Previous Edition Applied to: •...
Page 824 APPENDIX E REVISION HISTORY (2/10) Edition Major Revision from Previous Edition Applied to: Modification of description in table in 4.5.1 Number of access clocks CHAPTER 4 edition BUS CONTROL Addition of Caution in 4.6.1 (2) Address wait control register (AWC) FUNCTION Modification of timing chart in Figure 4-2 Example of Wait Insertion Addition of description in 4.8.1 Function outline...
Page 825 APPENDIX E REVISION HISTORY (3/10) Edition Major Revision from Previous Edition Applied to: Addition of Caution and addition of Caution in bit description in 7.3.8 (4) Timer 2 input CHAPTER 7 filter mode registers 0 to 5 (FEM0 to FEM5) edition INTERRUPT/ EXCEPTION...
Page 826 APPENDIX E REVISION HISTORY (4/10) Edition Major Revision from Previous Edition Applied to: Addition of Remark in 9.1.5 Operation CHAPTER 9 edition TIMER/COUNTER Addition of Remark in Figure 9-30 Operation Timing in PWM Mode 2 (Sawtooth Wave) FUNCTION (REAL- Modification of Figure 9-45 Block Diagram of Timer 1 TIME PULSE UNIT) Modification of bit names and addition of Caution in bit description in 9.2.4 (3) Timer control registers 10, 11 (TMC10, TMC11)
Page 827 APPENDIX E REVISION HISTORY (5/10) Edition Major Revision from Previous Edition Applied to: Addition of Note and deletion of Caution in Figure 9-95 Cycle Measurement Operation CHAPTER 9 edition Timing Example TIMER/COUNTER FUNCTION (REAL- Modification of Figure 9-97 Example of Timing During TM4 Operation TIME PULSE UNIT) Modification of bit names in 9.5.4 (1) Timer control register 4 (TMC4) Modification of Figure 9-98 TM4 Compare Operation Example...
Page 828 APPENDIX E REVISION HISTORY (6/10) Edition Major Revision from Previous Edition Applied to: Addition of 10.3.7 (4) Transfer rate in 2-frame continuous reception CHAPTER 10 edition SERIAL Modification of bit names in 10.4.3 (1) Clocked serial interface mode registers 0, 1 INTERFACE (CSIM0, CSIM1) FUNCTION...
Page 829 APPENDIX E REVISION HISTORY (7/10) Edition Major Revision from Previous Edition Applied to: Modification of description on bits that can be manipulated, addition and deletion of bit CHAPTER 11 edition description, and deletion of Caution and modification of bit description in 11.10 (21) CAN1 FCAN definition register (C1DEF) CONTROLLER...
Page 830 APPENDIX E REVISION HISTORY (8/10) Edition Major Revision from Previous Edition Applied to: Addition of 13.10.6 Timing that makes the A/D conversion result undefined CHAPTER 13 A/D edition CONVERTER Addition of 13.11 How to Read A/D Converter Characteristics Table Modification of block type and addition of Caution in 14.2 (1) Functions of each port CHAPTER 14 PORT FUNCTIONS Modification of Figure 14-2 Type B Block Diagram...
Page 831 APPENDIX E REVISION HISTORY (9/10) Edition Major Revision from Previous Edition Applied to: Addition of 16.7.16 Internal verify flow CHAPTER 16 edition FLASH MEMORY Addition of 16.7.17 Acquiring flash information flow ( µ PD70F3116) Addition of 16.7.18 Self-programming library Modification of Caution in 16.8 How to Distinguish Flash Memory and Mask ROM Versions Addition of CHAPTER 17 TURNING ON/OFF POWER...
Page 832 APPENDIX E REVISION HISTORY (10/10) Edition Major Revision from Previous Edition Applied to: Modification of description in Remark in 9.1.5 (2) PWM mode 0: Triangular wave CHAPTER 9 edition modulation (right-left symmetric waveform control) TIMER/COUNTER FUNCTION (REAL- TIME PULSE UNIT) Addition of Caution to 14.2 (1) Functions of each port CHAPTER 14 PORT FUNCTIONS...

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NEC V850E/IA1 mPD703116 User Manual

Chapter 1 Introduction

Outline

Features

Applications

Ordering Information

Pin Configuration (Top View)

Configuration of Function Block

Differences between Products

Chapter 2 Pin Functions

List of Pin Functions

Pin Status

Description of Pin Functions

Types of Pin I/O Circuit and Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Function

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Bus Cycle Type Control Function

Bus Access

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Chapter 6 Dma Functions (Dma Controller)

Features

Configuration

Control Registers

DMA Bus States

Transfer Mode

Transfer Types

Transfer Object

DMA Channel Priorities

Next Address Setting Function

DMA Transfer Start Factors

Forcible Interruption

DMA Transfer End

Forcible Termination

Precautions

Chapter 7 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Multiple Interrupt Servicing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 8 Clock Generation Function

Features

Configuration

Input Clock Selection

PLL Lockup

Power Save Control

Securing Oscillation Stabilization Time

Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer Connection Function

Chapter 10 Serial Interface Function

Features

Asynchronous Serial Interface 0 (UART0)

Asynchronous Serial Interfaces 1, 2 (UART1, UART2)

Clocked Serial Interfaces 0, 1 (CSI0, CSI1)

Chapter 11 Fcan Controller

Function Overview

Configuration

Configuration of Messages and Buffers