NEC V850E/IA1 mPD70F3116 Manuals

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NEC V850E/IA1 mPD70F3116 User Manual (832 pages)

32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4.63 MB

Table of Contents
10
Chapter 1 Introduction

30
- Outline
  
  30
- Features
  
  32
- Applications
  
  33
- Ordering Information
  
  34
- Pin Configuration (Top View)
  
  35
- Configuration of Function Block
  
  37
  - Internal Block Diagram
    37
  - Internal Units
    38
- Differences between Products
  
  40
Chapter 2 Pin Functions

41
- List of Pin Functions
  
  41
- Pin Status
  
  47
- Description of Pin Functions
  
  48
- Types of Pin I/O Circuit and Connection of Unused Pins
  
  59
- Pin I/O Circuits
  
  61
Chapter 3 Cpu Function

62
- Features
  
  62
- CPU Register Set
  
  63
  - Program Register Set
    64
  - System Register Set
    65
- Operation Modes
  
  67
  - Operation Mode Specification
    68
- Address Space
  
  69
  - CPU Address Space
    69
  - Image
    70
  - Wrap-Around of CPU Address Space
    71
  - Memory Map
    72
  - Area
    73
  - External Memory Expansion
    78
  - Recommended Use of Address Space
    79
  - On-Chip Peripheral I/O Registers
    81
  - Programmable Peripheral I/O Registers
    92
  - Specific Registers
    109
  - System Wait Control Register (VSWC)
    109
  - Cautions
    109
Chapter 4 Bus Control Function

110
- Features
  
  110
- Bus Control Pins
  
  110
  - Pin Status During Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
    110
- Memory Block Function
  
  111
  - Chip Select Control Function
    112
- Bus Cycle Type Control Function
  
  115
- Bus Access
  
  116
  - Number of Access Clocks
    116
  - Bus Sizing Function
    117
  - Word Data Processing Format
    117
  - Bus Width
    118
- Wait Function
  
  124
- Idle State Insertion Function
  
  127
- Bus Hold Function
  
  128
  - Function Outline
    128
  - Bus Hold Procedure
    128
  - Operation in Power Save Mode
    129
  - Bus Hold Timing
    129
- Bus Priority Order
  
  130
- Boundary Operation Conditions
  
  131
  - Program Space
    131
  - Data Space
    131
Chapter 5 Memory Access Control Function

132
- SRAM, External ROM, External I/O Interface
  
  132
  - Features
    132
  - SRAM, External ROM, External I/O Access
    133
Chapter 6 Dma Functions (Dma Controller)

138
- Features
  
  138
- Configuration
  
  139
- Control Registers
  
  140
- DMA Bus States
  
  152
  - Types of Bus States
    152
  - DMAC Bus Cycle State Transition
    153
- Transfer Mode
  
  154
  - Single Transfer Mode
    154
  - Single-Step Transfer Mode
    156
  - Block Transfer Mode
    156
- Transfer Types
  
  157
  - Two-Cycle Transfer
    157
- Transfer Object
  
  158
  - Transfer Type and Transfer Object
    158
  - External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
    159
- DMA Channel Priorities
  
  159
- Next Address Setting Function
  
  159
- DMA Transfer Start Factors
  
  161
- Forcible Interruption
  
  161
- DMA Transfer End
  
  162
- Forcible Termination
  
  162
- Precautions
  
  162
  - Interrupt Factors
    163
Chapter 7 Interrupt/Exception Processing Function

164
- Features
  
  164
- Non-Maskable Interrupt
  
  167
  - Operation
    168
  - Restore
    170
  - Non-Maskable Interrupt Status Flag (NP)
    171
  - Edge Detection Function
    171
- Maskable Interrupts
  
  172
  - Operation
    172
  - Restore
    174
  - Priorities of Maskable Interrupts
    175
  - Interrupt Control Register (Xxicn)
    179
  - Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
    182
  - In-Service Priority Register (ISPR)
    183
  - Maskable Interrupt Status Flag (ID)
    184
  - Interrupt Trigger Mode Selection
    185
- Software Exception
  
  194
  - Operation
    194
  - Restore
    195
  - Exception Status Flag (EP)
    196
- Exception Trap
  
  197
  - Illegal Opcode Definition
    197
  - Debug Trap
    199
- Multiple Interrupt Servicing Control
  
  201
- Interrupt Response Time
  
  202
- Periods in Which Interrupts Are Not Acknowledged
  
  204
Chapter 8 Clock Generation Function

205
- Features
  
  205
- Configuration
  
  205
- Input Clock Selection
  
  206
  - Direct Mode
    206
  - PLL Mode
    206
  - Peripheral Command Register (PHCMD)
    207
  - Clock Control Register (CKC)
    208
  - Peripheral Status Register (PHS)
    210
- PLL Lockup
  
  211
- Power Save Control
  
  212
  - Overview
    212
  - Control Registers
    215
  - HALT Mode
    218
  - IDLE Mode
    220
  - Software STOP Mode
    222
- Securing Oscillation Stabilization Time
  
  224
  - Oscillation Stabilization Time Security Specification
    224
  - Time Base Counter (TBC)
    225
Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)

226
- Timer 0
  
  226
  - Features (Timer 0)
    226
  - Function Overview (Timer 0)
    227
  - Basic Configuration
    228
  - Control Registers
    234
  - Operation
    258
  - Operation Timing
    289
- Timer 1
  
  298
  - Features (Timer 1)
    298
  - Function Overview (Timer 1)
    298
  - Basic Configuration
    300
  - Control Registers
    307
  - Operation
    318
  - Supplementary Description of Internal Operation
    330
- Timer 2
  
  334
  - Features (Timer 2)
    334
  - Function Overview (Timer 2)
    334
  - Basic Configuration
    336
  - Control Registers
    343
  - Operation
    359
- Timer 3
  
  377
  - Features (Timer 3)
    377
  - Function Overview (Timer 3)
    377
  - Basic Configuration
    378
  - Control Registers
    383
  - Operation
    389
  - Application Examples
    396
  - Precautions
    402
- Timer 4
  
  403
  - Features (Timer 4)
    403
  - Function Overview (Timer 4)
    403
  - Basic Configuration
    404
  - Control Register
    408
  - Operation
    409
  - Application Example
    411
  - Precautions
    411
- Timer Connection Function
  
  412
  - Overview
    412
  - Control Register
    413
Chapter 10 Serial Interface Function

414
- Features
  
  414
- Asynchronous Serial Interface 0 (UART0)
  
  415
  - Features
    415
  - Configuration
    416
  - Control Registers
    418
  - Interrupt Requests
    425
  - Operation
    426
  - Dedicated Baud Rate Generator 0 (BRG0)
    438
  - Precautions
    445
- Asynchronous Serial Interfaces 1, 2 (UART1, UART2)
  
  446
  - Features
    446
  - Configuration
    447
  - Control Registers
    449
  - Interrupt Requests
    458
  - Operation
    459
  - Synchronous Mode
    469
  - Dedicated Baud Rate Generators 1, 2 (BRG1, BRG2)
    474
- Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
  
  482
  - Features
    482
  - Configuration
    483
  - Control Registers
    486
  - Operation
    500
  - Output Pins
    515
  - Dedicated Baud Rate Generator 3 (BRG3)
    516
Chapter 11 Fcan Controller

520
- Function Overview
  
  520
- Configuration
  
  521
- Configuration of Messages and Buffers
  
  523
- Time Stamp Function
  
  524
- Message Processing
  
  527
- Mask Function
  
  528
- Protocol
  
  530
  - Protocol Mode Function
    530
  - Message Formats
    531
- Functions
  
  540
  - Determination of Bus Priority
    540
  - Bit Stuffing
    540
  - Multi-Master
    540
  - Multi-Cast
    540
  - CAN Sleep Mode/Can Stop Mode Function
    541
  - Error Control Function
    541
  - Baud Rate Control Function
    544
- Cautions on Bit Set/Clear Function
  
  547
- Control Registers
  
  549
- Operations
  
  601
  - Initialization Processing
    601
  - Transmit Setting
    612
  - Receive Setting
    613
  - CAN Sleep Mode
    614
  - CAN Stop Mode
    615
- Rules for Correct Setting of Baud Rate
  
  617
- Prioritization of Message Buffers During Receive Comparison
  
  620
  - Reception of Data Frames
    620
  - Reception of Remote Frames
    621
- Ensuring Data Consistency
  
  622
  - Sequential Data Read
    622
  - Burst Read Mode
    623
- Interrupt Conditions
  
  624
  - Interrupts that Are Generated for FCAN Controller
    624
  - Interrupts that Are Generated for Global CAN Interface
    624
- How to Shut down FCAN Controller
  
  625
- Cautions on Use
  
  626
CHAPTER 12 NBD FUNCTION ( Μ Μ Μ Μ PD70F3116)

627
- Overview
  
  627
- NBD Function Register Map
  
  628
- NBD Function Protocol
  
  629
- NBD Function
  
  632
- Control Registers
  
  637
- Restrictions on NBD
  
  640
- Initialization Required for DMA (2 Channels)
  
  641
Chapter 13 A/D Converter

645
- Features
  
  645
- Configuration
  
  645
- Control Registers
  
  649
- Interrupt Requests
  
  658
- A/D Converter Operation
  
  659
  - A/D Converter Basic Operation
    659
  - Operation Modes and Trigger Modes
    660
- Operation in A/D Trigger Mode
  
  663
  - Operation in Select Mode
    663
  - Operation in Scan Mode
    664
- Operation in A/D Trigger Polling Mode
  
  665
  - Operation in Select Mode
    665
  - Operation in Scan Mode
    666
- Operation in Timer Trigger Mode
  
  667
  - Operation in Select Mode
    667
  - Operation in Scan Mode
    668
- Operation in External Trigger Mode
  
  669
  - Operation in Select Mode
    669
  - Operation in Scan Mode
    670
- Precautions on Operation
  
  671
- How to Read A/D Converter Characteristics Table
  
  673
Chapter 14 Port Functions

677
- Features
  
  677
- Basic Configuration of Ports
  
  677
- Pin Functions of each Port
  
  692
  - Port 0
    692
  - Port 1
    693
  - Port 2
    696
  - Port 3
    699
  - Port 4
    701
  - Port DH
    703
  - Port DL
    705
  - Port CS
    707
  - Port CT
    709
  - Port CM
    711
- Noise Eliminator
  
  713
  - Interrupt Pins
    713
  - Timer 10, Timer 11, Timer 3 Input Pins
    714
  - Timer 2 Input Pins
    718
Chapter 15 Reset Function

721
- Features
  
  721
- Pin Functions
  
  721
- Initialization
  
  723
CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3116)

729
- Features
  
  729
- Writing by Flash Programmer
  
  729
- Programming Environment
  
  731
- Communication Mode
  
  731
- Pin Connection
  
  733
  - VPP Pin
    733
  - Serial Interface Pin
    733
  - RESET Pin
    735
  - NMI Pin
    735
  - MODE0 to MODE2 Pins
    735
  - Port Pins
    735
  - Other Signal Pins
    735
  - Power Supply
    736
- Programming Method
  
  736
  - Flash Memory Control
    736
  - Flash Memory Programming Mode
    737
  - Selection of Communication Mode
    737
  - Communication Commands
    738
- Flash Memory Programming by Self-Programming
  
  739
  - Outline of Self-Programming
    739
  - Self-Programming Function
    740
  - Outline of Self-Programming Interface
    740
  - Hardware Environment
    741
  - Software Environment
    743
  - Self-Programming Function Number
    744
  - Calling Parameters
    745
  - Contents of RAM Parameters
    746
  - Errors During Self-Programming
    747
  - Flash Information
    747
  - Area Number
    748
  - Flash Programming Mode Control Register (FLPMC)
    749
  - Calling Device Internal Processing
    751
  - Erasing Flash Memory Flow
    754
  - Continuous Writing Flow
    755
  - Internal Verify Flow
    756
  - Acquiring Flash Information Flow
    757
  - Self-Programming Library
    758
- How to Distinguish Flash Memory and Mask ROM Versions
  
  760
Chapter 17 Turning On/Off Power

761
Chapter 18 Electrical Specifications

763
- Normal Operation Mode
  
  763
- Flash Memory Programming Mode ( Μ Μ Μ Μ PD70F3116 Only)
  
  789
Chapter 19 Package Drawing

791
Chapter 20 Recommended Soldering Conditions

792
Appendix A Notes on Target System Design

793
Appendix B Register Index

794
Appendix C Instruction Set List

805
- Functions
  
  805
- Instruction Set (Alphabetical Order)
  
  808
Appendix D Index

814
Appendix E Revision History

823

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NEC V850E/IA1 mPD70F3116 Manuals

NEC V850E/IA1 mPD70F3116 User Manual (832 pages)

Table of Contents

Chapter 1 Introduction

Outline

Features

Applications

Ordering Information

Pin Configuration (Top View)

Configuration of Function Block

Differences between Products

Chapter 2 Pin Functions

List of Pin Functions

Pin Status

Description of Pin Functions

Types of Pin I/O Circuit and Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Function

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Bus Cycle Type Control Function

Bus Access

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Chapter 6 Dma Functions (Dma Controller)

Features

Configuration

Control Registers

DMA Bus States

Transfer Mode

Transfer Types

Transfer Object

DMA Channel Priorities

Next Address Setting Function

DMA Transfer Start Factors

Forcible Interruption

DMA Transfer End

Forcible Termination

Precautions

Chapter 7 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Multiple Interrupt Servicing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 8 Clock Generation Function

Features

Configuration

Input Clock Selection

PLL Lockup

Power Save Control

Securing Oscillation Stabilization Time

Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer Connection Function

Chapter 10 Serial Interface Function

Features

Asynchronous Serial Interface 0 (UART0)

Asynchronous Serial Interfaces 1, 2 (UART1, UART2)

Clocked Serial Interfaces 0, 1 (CSI0, CSI1)

Chapter 11 Fcan Controller

Function Overview