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Caution When using the PLL mode, only an f
system clock maximum frequency (50 MHz) can be used for the oscillation frequency or
external clock frequency.
When 5 × × × × f
X
Remark Note the following when PLL mode is selected (f
If the V850E/IA1 need not be operated at high frequency, use f
to reduce the power consumption by lowering the system clock frequency using software.
8.3.3 Peripheral command register (PHCMD)
This is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system
so that the application system is not halted unexpectedly due to erroneous program execution. This register can be
written only in 8-bit units (when it is read, undefined data is read out).
Writing to the first specific register (CKC or FLPMC register) is only valid after first writing to the PHCMD register.
Because of this, the register value can be overwritten only with the specified sequence, preventing an illegal write
operation from being performed.
7
6
PHCMD
REG7
REG6
Bit Position
Bit Name
7 to 0
REG7 to
REG0
The generation of an illegal store operation can be checked with the PRERR bit of the peripheral status register
(PHS).
CHAPTER 8 CLOCK GENERATION FUNCTION
, 2.5 × × × × f
, or 1 × × × × f
is used, a frequency of 4 to 6.4 MHz can be used.
X
X
5
4
3
REG5
REG4
REG3
Registration code (arbitrary 8-bit data)
The specific registers targeted are as follows.
• Clock control register (CKC)
• Flash programming mode control register (FLPMC)
User's Manual U14492EJ3V0UD
(4 to 5 MHz) value for which 10 × × × × f
X
= 5 × f
= 2.5 × f
, f
XX
X
XX
= 5 × f
XX
2
1
0
REG2
REG1
REG0
Function
does not exceed the
X
= 1 × f
, or f
)
X
XX
X
= 2.5 × f
= 1 × f
, f
, or f
X
XX
X
XX
Address
Initial value
FFFFF800H Undefined
X
207
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