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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(b) Setting these registers to compare registers (CMS1 and CMS0 of TMC31 = 1)
When these registers are set to compare registers, the TM3 and register values are compared for each
count clock, and an interrupt is generated by a match. If the CCLR bit of timer control register 31
(TMC31) is set (1), the TM3 value is cleared (0) at the same time as a match with the CC30 register (it is
not cleared (0) by a match with the CC31 register).
A compare register is equipped with a set/reset output function. The corresponding timer output (TO3) is
set or reset, synchronized with the generation of a match signal.
The interrupt selection source differs according to the function of the selected register.
Cautions 1. To write to capture/compare registers 30 and 31 (CC30, CC31), always set the TM3CAE
bit to 1 first. When the TM3CAE bit is 0, even if writing to registers CC30 and CC31, the
data that is written will be invalid because the reset is asynchronous.
2. Perform a write operation to capture/compare registers 30 and 31 after setting them to
compare registers according to the TMC30, TMC31 register setting. If they are set to
capture registers (CMS1 and CMS0 bits of TMC31 register = 0), no data is written even if
a write operation is performed to CC30 and CC31.
3. When these registers are set to compare registers, INTP30 and INTP31 cannot be used
as external interrupt input pins.
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User's Manual U14492EJ3V0UD
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