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5.1.3 Register Configuration
The four interrupt priority registers (IPRA to IPRD) and four data transfer enable registers (DTEA
to DTED) are 8-bit registers located at addresses H'FFF0 to H'FFF7 in the register field in page 0
of the address space. Table 5-1 lists their attributes.
Table 5-1 Interrupt Controller Registers
Name
Interrupt
priority
register
Data transfer
enable
register
5.2 Interrupt Types
There are 22 distinct types of interrupts: 3 external interrupts originating off-chip and 19 internal
interrupts originating in the on-chip supporting modules.
5.2.1 External Interrupts
The three external interrupts are NMI, IRQ
NMI (NonMaskable Interrupt): This interrupt has the highest priority level (8) and cannot be
masked. An NMI is generated by input to the NMI pin, and can also be generated by a watchdog
timer (WDT) overflow. The input at the NMI pin is edge-sensed. A user program can select
whether to have the interrupt occur on the rising edge or falling edge of the NMI input by setting
or clearing the nonmaskable interrupt edge bit (NMIEG) in the port 1 control register (P1CR).
In the NMI exception-handling sequence, the T (Trace) bit in the CPU status register (SR) is
cleared to "0," and the interrupt mask level in I2 to I0 is set to 7, masking all other interrupts. The
interrupt controller holds the NMI request until the NMI exception-handling sequence begins, then
clears the NMI request, so if another interrupt is requested at the NMI pin during the NMI
exception-handling sequence, the NMI exception-handling sequence will be carried out again.
A watchdog timer overflow generates an NMI if the TME and WT/IT bits in the watchdog timer's
status/control register are both set to "1." See section 13, "Watchdog Timer" for details.
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Abbreviation
A
IPRA
B
IPRB
C
IPRC
D
IPRD
A
DTEA
B
DTEB
C
DTEC
D
DTED
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
, and IRQ
.
0
1
99
Address
Initial Value
H'FFF0
H'00
H'FFF1
H'00
H'FFF2
H'00
H'FFF3
H'00
H'FFF4
H'00
H'FFF5
H'00
H'FFF6
H'00
H'FFF7
H'00
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