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P1 / ø*
0
P1 /E*
0
RES
Internal reset signal
I/O ports
The dotted line indicates that P1
bit is 0, but clock output pins if the DDR bit is 1.
Figure E-10 Reset during Memory Access (Mode 7)
/ø and P1
/E are input port if the corresponding DDR
0
0
447
High impedance