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1.5.2
Generic digital interfaces supply output (V_INT)
The V_INT output pin of LEXI-R10 series modules is internally generated by a linear LDO regulator
integrated in the Power Management Unit and it is internally used to source the generic digital
interfaces of the cellular module (as the UART interfaces, the I2C interface, the GPIOs, but except the
always-on GPIOs), as described in
The internal LDO regulator that generates the V_INT output voltage is enabled when the modules are
switched on, and outside ultra-low power deep-sleep mode.
The typical operating voltage is 1.8 V, whereas the current capability is specified in the LEXI-R10
series data sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator
as a reference voltage rail for external components.
The V_INT output pin of the LEXI-R10 series modules is connected to an internal 1.8 V supply with a
current capability specified in the LEXI-R10 series data sheet [1].
LEXI-R10 series
Power Management
Unit
VCC
A14
VCC
A13
LDO regulator
VCC
A12
Figure 5: LEXI-R10 series interfaces supply output (V_INT) simplified block diagram
1.6 System function interfaces
1.6.1
Module power-on
When the LEXI-R10 series modules are in the not-powered mode (i.e. without a valid voltage supply
present at the VCC module supply input), the modules' switch on can be triggered by:
• Applying a voltage supply at the VCC supply input within the VCC voltage supply operating range
(see LEXI-R10 series data sheet [1], module supply normal operating input voltage), and then
forcing a low level at the PWR_ON input pin for a valid time (see LEXI-R10 series data sheet [1],
module switch on from power off mode).
When the LEXI-R10 series modules are in the power-off mode (i.e. switched off, but with a valid voltage
present at the VCC module supply input), the modules' switch on can be triggered by:
• Forcing a low level at the PWR_ON input pin for a valid time (see LEXI-R10 series data sheet [1],
module switch on from power off mode).
When the LEXI-R10 series modules are in ultra-low power deep-sleep mode, the modules' wake-up can
be triggered by:
• Forcing a low level at the PWR_ON input pin for a valid time (see LEXI-R10 series data sheet [1],
module wake-up from deep sleep mode), or
• In +UPSV=5 condition, applying a rising edge at the GPIO3 or GPIO6 input pin appropriately
configured by AT+UGPIOC (see section 1.10, module wake-up and low power mode control).
• Using USB interface with +UUSBSLPCONF=0 condition, via USB resume procedure
UBX-23008149 - R04
C1-Public
Figure
5.
Base-Band
processor
Generic Digital
I/O Interfaces
V_INT
A11
System description
LEXI-R10 series - System integration manual
Page 15 of 92
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